Update PCI bus driver to support non-standard PCI to PCI bridge I/O window alignment...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciEnumeratorSupport.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index 8f3ed5eb374d8baa6ce7523b69b871426644ab63..940d8d296108026c5a126b602687f1e6da40f02d 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -469,6 +469,36 @@ GatherPpbInfo (
     }\r
   }\r
 \r
+  //\r
+  // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes\r
+  // PCI bridge supporting non-stardard I/O window alignment less than 4K.\r
+  //\r
+\r
+  PciIoDevice->BridgeIoAlignment = 0xFFF;\r
+  if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe)) {\r
+    //\r
+    // Check any bits of bit 3-1 of I/O Base Register are writable.\r
+    // if so, it is assumed non-stardard I/O window alignment is supported by this bridge.\r
+    // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.\r
+    //\r
+    Value = Temp ^ (BIT3 | BIT2 | BIT1);\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
+    PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+    Value = (Value ^ Temp) & (BIT3 | BIT2 | BIT1);\r
+    switch (Value) {\r
+      case BIT3:\r
+        PciIoDevice->BridgeIoAlignment = 0x7FF;\r
+        break;\r
+      case BIT3 | BIT2:\r
+        PciIoDevice->BridgeIoAlignment = 0x3FF;\r
+        break;\r
+      case BIT3 | BIT2 | BIT1:\r
+        PciIoDevice->BridgeIoAlignment = 0x1FF;\r
+        break;\r
+    }\r
+  }\r
+\r
   Status = BarExisted (\r
             PciIoDevice,\r
             0x24,\r