/** @file\r
PCI emumeration support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
root bridge will then be created.\r
\r
@param Bridge Parent bridge instance.\r
- @param StartBusNumber Bus number of begining.\r
+ @param StartBusNumber Bus number of beginning.\r
\r
@retval EFI_SUCCESS PCI device is found.\r
@retval other Some error occurred when reading PCI bridge information.\r
}\r
\r
/**\r
- Seach required device and create PCI device instance.\r
+ Search required device and create PCI device instance.\r
\r
@param Bridge Parent bridge instance.\r
@param Pci Input PCI device information block.\r
\r
if (Descriptor->AddrSpaceGranularity == 32) {\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {\r
Type = PciBarTypePMem32;\r
}\r
\r
//\r
- // Non-prefechable\r
+ // Non-prefetchable\r
//\r
if (Descriptor->SpecificFlag == 0) {\r
Type = PciBarTypeMem32;\r
\r
if (Descriptor->AddrSpaceGranularity == 64) {\r
//\r
- // prefechable\r
+ // prefetchable\r
//\r
if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {\r
Type = PciBarTypePMem64;\r
}\r
\r
//\r
- // Non-prefechable\r
+ // Non-prefetchable\r
//\r
if (Descriptor->SpecificFlag == 0) {\r
Type = PciBarTypeMem64;\r
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
\r
//\r
- // Initalize the bridge control register\r
+ // Initialize the bridge control register\r
//\r
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);\r
\r
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
\r
//\r
- // Initalize the bridge control register\r
+ // Initialize the bridge control register\r
//\r
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
}\r
}\r
\r
/**\r
- Create device path for pci deivce.\r
+ Create device path for pci device.\r
\r
@param ParentDevicePath Parent bridge's path.\r
@param PciIoDevice Pci device instance.\r
@param PciIoDevice Pci device instance.\r
@param Command Input command register value, and\r
returned supported register value.\r
- @param BridgeControl Inout bridge control value for PPB or P2C, and\r
+ @param BridgeControl Input bridge control value for PPB or P2C, and\r
returned supported bridge control value.\r
@param OldCommand Returned and stored old command register offset.\r
@param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.\r
EFI_STATUS Status;\r
\r
//\r
- // For Root Bridge, just copy it by RootBridgeIo proctocol\r
+ // For Root Bridge, just copy it by RootBridgeIo protocol\r
// so as to keep consistent with the actual attribute\r
//\r
if (PciIoDevice->Parent == NULL) {\r
return Status;\r
}\r
//\r
- // Assume the PCI Root Bridge supports DAC and Bus Master.\r
+ // Assume the PCI Root Bridge supports DAC\r
//\r
PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE |\r
- EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);\r
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
\r
} else {\r
\r
//\r
Command = EFI_PCI_COMMAND_IO_SPACE |\r
EFI_PCI_COMMAND_MEMORY_SPACE |\r
+ EFI_PCI_COMMAND_BUS_MASTER |\r
EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
\r
- //\r
- // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.\r
- // So only test the Bus Master capability for PCI devices.\r
- //\r
- if (!IS_PCI_BRIDGE(&PciIoDevice->Pci)) {\r
- Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
- }\r
-\r
BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16;\r
\r
//\r
\r
//\r
// Set the supported attributes for specified PCI device\r
- // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.\r
//\r
- if (IS_PCI_BRIDGE(&PciIoDevice->Pci)) {\r
- Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
- }\r
PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, EFI_SET_SUPPORTS);\r
\r
//\r
PciSetDeviceAttribute (PciIoDevice, OldCommand, OldBridgeControl, EFI_SET_ATTRIBUTES);\r
\r
//\r
- // Enable other supported attributes but not defined in PCI_IO_PROTOCOL\r
- //\r
- PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
+ // Enable other PCI supported attributes but not defined in PCI_IO_PROTOCOL\r
+ // For PCI Express devices, Memory Write and Invalidate is hardwired to 0b so only enable it for PCI devices.\r
+ if (!PciIoDevice->IsPciExp) {\r
+ PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
+ }\r
}\r
\r
FastB2BSupport = TRUE;\r
return Status;\r
}\r
//\r
- // Detect Fast Bact to Bact support for the device under the bridge\r
+ // Detect Fast Back to Back support for the device under the bridge\r
//\r
Status = GetFastBackToBackSupport (Temp, PCI_PRIMARY_STATUS_OFFSET);\r
if (FastB2BSupport && EFI_ERROR (Status)) {\r
}\r
\r
//\r
- // Fix the length to support some spefic 64 bit BAR\r
+ // Fix the length to support some special 64 bit BAR\r
//\r
Value |= ((UINT32) -1 << HighBitSet32 (Value));\r
\r
break;\r
}\r
}\r
- \r
+\r
//\r
// Check the length again so as to keep compatible with some special bars\r
//\r
PciIoDevice->VfPciBar[BarIndex].BaseAddress = 0;\r
PciIoDevice->VfPciBar[BarIndex].Alignment = 0;\r
}\r
- \r
+\r
//\r
// Increment number of bar\r
//\r
\r
}\r
//\r
- // Workaround. Some platforms inplement IO bar with 0 length\r
+ // Workaround. Some platforms implement IO bar with 0 length\r
// Need to treat it as no-bar\r
//\r
if (PciIoDevice->PciBar[BarIndex].Length == 0) {\r
}\r
\r
//\r
- // Fix the length to support some spefic 64 bit BAR\r
+ // Fix the length to support some special 64 bit BAR\r
//\r
if (Value == 0) {\r
DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));\r
//\r
// Put all the resource apertures\r
// Resource base is set to all ones so as to indicate its resource\r
- // has not been alloacted\r
+ // has not been allocated\r
//\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
}\r
\r
/**\r
- Create and initiliaze general PCI I/O device instance for\r
+ Create and initialize general PCI I/O device instance for\r
PCI device/bridge device/hotplug bridge device.\r
\r
- @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ @param Bridge Parent bridge instance.\r
@param Pci Input Pci information block.\r
@param Bus Device Bus NO.\r
@param Device Device device NO.\r
//\r
ParentPciIo = &Bridge->PciIo;\r
ParentPciIo->Pci.Read (\r
- ParentPciIo, \r
+ ParentPciIo,\r
EfiPciIoWidthUint32,\r
Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,\r
1,\r
}\r
\r
//\r
- // Record the root bridgeio protocol\r
+ // Record the root bridge-io protocol\r
//\r
RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;\r
\r
} else {\r
\r
//\r
- // If unsuccessly, destroy the entire node\r
+ // If unsuccessfully, destroy the entire node\r
//\r
DestroyRootBridge (RootBridgeDev);\r
}\r
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