/** @file\r
EFI PCI IO protocol functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PciBus.h"\r
\r
+extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;\r
+\r
//\r
// Pci Io Protocol Interface\r
//\r
OUT VOID **Mapping\r
)\r
{\r
- EFI_STATUS Status;\r
- PCI_IO_DEVICE *PciIoDevice;\r
+ EFI_STATUS Status;\r
+ PCI_IO_DEVICE *PciIoDevice;\r
+ UINT64 IoMmuAttribute;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION RootBridgeIoOperation;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
+ RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;\r
if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r
- Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);\r
+ RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + EfiPciOperationBusMasterRead64);\r
}\r
\r
Status = PciIoDevice->PciRootBridgeIo->Map (\r
PciIoDevice->PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,\r
+ RootBridgeIoOperation,\r
HostAddress,\r
NumberOfBytes,\r
DeviceAddress,\r
);\r
}\r
\r
+ if (mIoMmuProtocol != NULL) {\r
+ if (!EFI_ERROR (Status)) {\r
+ switch (Operation) {\r
+ case EfiPciIoOperationBusMasterRead:\r
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;\r
+ break;\r
+ case EfiPciIoOperationBusMasterWrite:\r
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;\r
+ break;\r
+ case EfiPciIoOperationBusMasterCommonBuffer:\r
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;\r
+ break;\r
+ default:\r
+ ASSERT(FALSE);\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ mIoMmuProtocol->SetAttribute (\r
+ mIoMmuProtocol,\r
+ PciIoDevice->Handle,\r
+ *Mapping,\r
+ IoMmuAttribute\r
+ );\r
+ }\r
+ }\r
+\r
return Status;\r
}\r
\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
+ if (mIoMmuProtocol != NULL) {\r
+ mIoMmuProtocol->SetAttribute (\r
+ mIoMmuProtocol,\r
+ PciIoDevice->Handle,\r
+ Mapping,\r
+ 0\r
+ );\r
+ }\r
+\r
Status = PciIoDevice->PciRootBridgeIo->Unmap (\r
PciIoDevice->PciRootBridgeIo,\r
Mapping\r
//\r
// Check VGA and VGA16, they can not be set at the same time\r
//\r
- if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
- ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||\r
- ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
- ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {\r
- return EFI_UNSUPPORTED;\r
+ if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO)) != 0) {\r
+ if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
}\r
\r
//\r
return Status;\r
}\r
\r
+/**\r
+ Retrieve the AddrTranslationOffset from RootBridgeIo for the\r
+ specified range.\r
+\r
+ @param RootBridgeIo Root Bridge IO instance.\r
+ @param AddrRangeMin The base address of the MMIO.\r
+ @param AddrLen The length of the MMIO.\r
+\r
+ @retval The AddrTranslationOffset from RootBridgeIo for the \r
+ specified range, or (UINT64) -1 if the range is not\r
+ found in RootBridgeIo.\r
+**/\r
+UINT64\r
+GetMmioAddressTranslationOffset (\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo,\r
+ UINT64 AddrRangeMin,\r
+ UINT64 AddrLen\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
+\r
+ Status = RootBridgeIo->Configuration (\r
+ RootBridgeIo,\r
+ (VOID **) &Configuration\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return (UINT64) -1;\r
+ }\r
+\r
+ while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
+ if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&\r
+ (Configuration->AddrRangeMin <= AddrRangeMin) &&\r
+ (Configuration->AddrRangeMin + Configuration->AddrLen >= AddrRangeMin + AddrLen)\r
+ ) {\r
+ return Configuration->AddrTranslationOffset;\r
+ }\r
+ Configuration++;\r
+ }\r
+\r
+ //\r
+ // The resource occupied by BAR should be in the range reported by RootBridge.\r
+ //\r
+ ASSERT (FALSE);\r
+ return (UINT64) -1;\r
+}\r
+\r
/**\r
Gets the attributes that this PCI controller supports setting on a BAR using\r
SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
OUT VOID **Resources OPTIONAL\r
)\r
{\r
- UINT8 *Configuration;\r
PCI_IO_DEVICE *PciIoDevice;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AddressSpace;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
}\r
\r
if (Resources != NULL) {\r
- Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
- if (Configuration == NULL) {\r
+ Descriptor = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ if (Descriptor == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- AddressSpace = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
-\r
- AddressSpace->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- AddressSpace->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
+ *Resources = Descriptor;\r
\r
- AddressSpace->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
- AddressSpace->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r
- AddressSpace->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r
+ Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Descriptor->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
+ Descriptor->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
+ Descriptor->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r
+ Descriptor->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r
\r
switch (PciIoDevice->PciBar[BarIndex].BarType) {\r
case PciBarTypeIo16:\r
//\r
// Io\r
//\r
- AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
break;\r
\r
- case PciBarTypeMem32:\r
+ case PciBarTypePMem32:\r
//\r
- // Mem\r
+ // prefechable\r
//\r
- AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
//\r
- // 32 bit\r
+ // Fall through\r
//\r
- AddressSpace->AddrSpaceGranularity = 32;\r
- break;\r
-\r
- case PciBarTypePMem32:\r
+ case PciBarTypeMem32:\r
//\r
// Mem\r
//\r
- AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- //\r
- // prefechable\r
- //\r
- AddressSpace->SpecificFlag = 0x6;\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
//\r
// 32 bit\r
//\r
- AddressSpace->AddrSpaceGranularity = 32;\r
+ Descriptor->AddrSpaceGranularity = 32;\r
break;\r
\r
- case PciBarTypeMem64:\r
+ case PciBarTypePMem64:\r
//\r
- // Mem\r
+ // prefechable\r
//\r
- AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
//\r
- // 64 bit\r
+ // Fall through\r
//\r
- AddressSpace->AddrSpaceGranularity = 64;\r
- break;\r
-\r
- case PciBarTypePMem64:\r
+ case PciBarTypeMem64:\r
//\r
// Mem\r
//\r
- AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- //\r
- // prefechable\r
- //\r
- AddressSpace->SpecificFlag = 0x6;\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
//\r
// 64 bit\r
//\r
- AddressSpace->AddrSpaceGranularity = 64;\r
+ Descriptor->AddrSpaceGranularity = 64;\r
break;\r
\r
default:\r
//\r
// put the checksum\r
//\r
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AddressSpace + 1);\r
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);\r
End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
End->Checksum = 0;\r
\r
- *Resources = Configuration;\r
+ //\r
+ // Get the Address Translation Offset\r
+ //\r
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
+ Descriptor->AddrTranslationOffset = GetMmioAddressTranslationOffset (\r
+ PciIoDevice->PciRootBridgeIo,\r
+ Descriptor->AddrRangeMin,\r
+ Descriptor->AddrLen\r
+ );\r
+ if (Descriptor->AddrTranslationOffset == (UINT64) -1) {\r
+ FreePool (Descriptor);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ }\r
}\r
\r
return EFI_SUCCESS;\r
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