MdeModulePkg/SdMmcPciHcDxe: Add SDMMC HC v4 and above Support.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHcDxe.h

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 8c1a58907839b16c2e8fd1036dad84ef270e7d03..1bb701a5031ff318283e2b94ad6e147db19a8605 100644 (file)
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -2,6 +2,7 @@
 \r
   Provides some data structure definitions used by the SD/MMC host controller driver.\r
 \r
+Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.\r
 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
@@ -116,8 +117,7 @@ typedef struct {
   SD_MMC_HC_SLOT                      Slot[SD_MMC_HC_MAX_SLOT];\r
   SD_MMC_HC_SLOT_CAP                  Capability[SD_MMC_HC_MAX_SLOT];\r
   UINT64                              MaxCurrent[SD_MMC_HC_MAX_SLOT];\r
-\r
-  UINT32                              ControllerVersion;\r
+  UINT16                              ControllerVersion[SD_MMC_HC_MAX_SLOT];\r
 \r
   //\r
   // Some controllers may require to override base clock frequency\r
@@ -150,7 +150,8 @@ typedef struct {
   BOOLEAN                             Started;\r
   UINT64                              Timeout;\r
 \r
-  SD_MMC_HC_ADMA_DESC_LINE            *AdmaDesc;\r
+  SD_MMC_HC_ADMA_32_DESC_LINE         *Adma32Desc;\r
+  SD_MMC_HC_ADMA_64_DESC_LINE         *Adma64Desc;\r
   EFI_PHYSICAL_ADDRESS                AdmaDescPhy;\r
   VOID                                *AdmaMap;\r
   UINT32                              AdmaPages;\r