\r
It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.\r
\r
+ Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));\r
DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));\r
DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));\r
- DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));\r
+ DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));\r
+ DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));\r
DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));\r
DEBUG ((DEBUG_INFO, " SlotType "));\r
if (Capability->SlotType == 0x00) {\r
return EFI_TIMEOUT;\r
}\r
\r
+/**\r
+ Get the controller version information from the specified slot.\r
+\r
+ @param[in] PciIo The PCI IO protocol instance.\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[out] Version The buffer to store the version information.\r
+\r
+ @retval EFI_SUCCESS The operation executes successfully.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdMmcHcGetControllerVersion (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT8 Slot,\r
+ OUT UINT16 *Version\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ *Version &= 0xFF;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
/**\r
Software reset the specified SD/MMC host controller and enable all interrupts.\r
\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
+ @param[in] ControllerVer The version of host controller.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
IN UINT64 ClockFreq,\r
- IN UINT32 BaseClkFreq\r
+ IN UINT32 BaseClkFreq,\r
+ IN UINT16 ControllerVer\r
)\r
{\r
EFI_STATUS Status;\r
UINT32 SettingFreq;\r
UINT32 Divisor;\r
UINT32 Remainder;\r
- UINT16 ControllerVer;\r
UINT16 ClockCtrl;\r
\r
//\r
\r
DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r
\r
- Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
//\r
// Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
//\r
- if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&\r
- ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {\r
+ if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&\r
+ (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {\r
ASSERT (Divisor <= 0x3FF);\r
ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
- } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
+ } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||\r
+ (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {\r
//\r
// Only the most significant bit can be used as divisor.\r
//\r
return Status;\r
}\r
\r
+/**\r
+ Configure V4 controller enhancements at initialization.\r
+\r
+ @param[in] PciIo The PCI IO protocol instance.\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[in] Capability The capability of the slot.\r
+ @param[in] ControllerVer The version of host controller.\r
+\r
+ @retval EFI_SUCCESS The clock is supplied successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+SdMmcHcInitV4Enhancements (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT8 Slot,\r
+ IN SD_MMC_HC_SLOT_CAP Capability,\r
+ IN UINT16 ControllerVer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT16 HostCtrl2;\r
+\r
+ //\r
+ // Check if controller version V4 or higher\r
+ //\r
+ if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r
+ HostCtrl2 = SD_MMC_HC_V4_EN;\r
+ //\r
+ // Check if V4 64bit support is available\r
+ //\r
+ if (Capability.SysBus64V4 != 0) {\r
+ HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;\r
+ DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));\r
+ }\r
+ //\r
+ // Check if controller version V4.10 or higher\r
+ //\r
+ if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {\r
+ HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;\r
+ DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));\r
+ }\r
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
/**\r
Supply SD/MMC card with lowest clock frequency at initialization.\r
\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
+ @param[in] ControllerVer The version of host controller.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
SdMmcHcInitClockFreq (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
- IN UINT32 BaseClkFreq\r
+ IN UINT32 BaseClkFreq,\r
+ IN UINT16 ControllerVer\r
)\r
{\r
EFI_STATUS Status;\r
// Supply 400KHz clock frequency at initialization phase.\r
//\r
InitFreq = 400;\r
- Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);\r
+ Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);\r
return Status;\r
}\r
\r
PciIo = Private->PciIo;\r
Capability = Private->Capability[Slot];\r
\r
- Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);\r
+ Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
/**\r
Build ADMA descriptor table for transfer.\r
\r
- Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.\r
+ Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.\r
\r
@param[in] Trb The pointer to the SD_MMC_HC_TRB instance.\r
+ @param[in] ControllerVer The version of host controller.\r
\r
@retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r
@retval Others The ADMA descriptor table isn't created successfully.\r
**/\r
EFI_STATUS\r
BuildAdmaDescTable (\r
- IN SD_MMC_HC_TRB *Trb\r
+ IN SD_MMC_HC_TRB *Trb,\r
+ IN UINT16 ControllerVer\r
)\r
{\r
EFI_PHYSICAL_ADDRESS Data;\r
UINT64 Entries;\r
UINT32 Index;\r
UINT64 Remaining;\r
- UINT32 Address;\r
+ UINT64 Address;\r
UINTN TableSize;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
EFI_STATUS Status;\r
UINTN Bytes;\r
+ BOOLEAN AddressingMode64;\r
+ BOOLEAN DataLength26;\r
+ UINT32 AdmaMaxDataPerLine;\r
+ UINT32 DescSize;\r
+ VOID *AdmaDesc;\r
+\r
+ AddressingMode64 = FALSE;\r
+ DataLength26 = FALSE;\r
+ AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;\r
+ DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);\r
+ AdmaDesc = NULL;\r
\r
Data = Trb->DataPhy;\r
DataLen = Trb->DataLen;\r
PciIo = Trb->Private->PciIo;\r
+\r
//\r
- // Only support 32bit ADMA Descriptor Table\r
+ // Detect whether 64bit addressing is supported.\r
//\r
- if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {\r
+ if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {\r
+ Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r
+ SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);\r
+ if (!EFI_ERROR (Status)) {\r
+ AddressingMode64 = TRUE;\r
+ DescSize = sizeof (SD_MMC_HC_ADMA_64_DESC_LINE);\r
+ }\r
+ }\r
+ //\r
+ // Check for valid ranges in 32bit ADMA Descriptor Table\r
+ //\r
+ if (!AddressingMode64 &&\r
+ ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {\r
return EFI_INVALID_PARAMETER;\r
}\r
//\r
- // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
- // for 32-bit address descriptor table.\r
+ // Check address field alignment\r
//\r
- if ((Data & (BIT0 | BIT1)) != 0) {\r
- DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r
+ if (AddressingMode64) {\r
+ //\r
+ // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)\r
+ //\r
+ if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {\r
+ DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));\r
+ }\r
+ } else {\r
+ //\r
+ // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
+ //\r
+ if ((Data & (BIT0 | BIT1)) != 0) {\r
+ DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r
+ }\r
+ }\r
+ //\r
+ // Detect whether 26bit data length is supported.\r
+ //\r
+ Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r
+ SD_MMC_HC_26_DATA_LEN_ADMA_EN, SD_MMC_HC_26_DATA_LEN_ADMA_EN);\r
+ if (!EFI_ERROR (Status)) {\r
+ DataLength26 = TRUE;\r
+ AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;\r
}\r
\r
- Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);\r
- TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));\r
+ Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);\r
+ TableSize = (UINTN)MultU64x32 (Entries, DescSize);\r
Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);\r
Status = PciIo->AllocateBuffer (\r
PciIo,\r
AllocateAnyPages,\r
EfiBootServicesData,\r
EFI_SIZE_TO_PAGES (TableSize),\r
- (VOID **)&Trb->AdmaDesc,\r
+ (VOID **)&AdmaDesc,\r
0\r
);\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
- ZeroMem (Trb->AdmaDesc, TableSize);\r
+ ZeroMem (AdmaDesc, TableSize);\r
Bytes = TableSize;\r
Status = PciIo->Map (\r
PciIo,\r
EfiPciIoOperationBusMasterCommonBuffer,\r
- Trb->AdmaDesc,\r
+ AdmaDesc,\r
&Bytes,\r
&Trb->AdmaDescPhy,\r
&Trb->AdmaMap\r
PciIo->FreeBuffer (\r
PciIo,\r
EFI_SIZE_TO_PAGES (TableSize),\r
- Trb->AdmaDesc\r
+ AdmaDesc\r
);\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r
+ if ((!AddressingMode64) &&\r
+ (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {\r
//\r
// The ADMA doesn't support 64bit addressing.\r
//\r
PciIo->FreeBuffer (\r
PciIo,\r
EFI_SIZE_TO_PAGES (TableSize),\r
- Trb->AdmaDesc\r
+ AdmaDesc\r
);\r
return EFI_DEVICE_ERROR;\r
}\r
\r
Remaining = DataLen;\r
- Address = (UINT32)Data;\r
+ Address = Data;\r
+ if (!AddressingMode64) {\r
+ Trb->Adma32Desc = AdmaDesc;\r
+ Trb->Adma64Desc = NULL;\r
+ } else {\r
+ Trb->Adma64Desc = AdmaDesc;\r
+ Trb->Adma32Desc = NULL;\r
+ }\r
for (Index = 0; Index < Entries; Index++) {\r
- if (Remaining <= ADMA_MAX_DATA_PER_LINE) {\r
- Trb->AdmaDesc[Index].Valid = 1;\r
- Trb->AdmaDesc[Index].Act = 2;\r
- Trb->AdmaDesc[Index].Length = (UINT16)Remaining;\r
- Trb->AdmaDesc[Index].Address = Address;\r
- break;\r
+ if (!AddressingMode64) {\r
+ if (Remaining <= AdmaMaxDataPerLine) {\r
+ Trb->Adma32Desc[Index].Valid = 1;\r
+ Trb->Adma32Desc[Index].Act = 2;\r
+ if (DataLength26) {\r
+ Trb->Adma32Desc[Index].UpperLength = (UINT16)(Remaining >> 16);\r
+ }\r
+ Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r
+ Trb->Adma32Desc[Index].Address = (UINT32)Address;\r
+ break;\r
+ } else {\r
+ Trb->Adma32Desc[Index].Valid = 1;\r
+ Trb->Adma32Desc[Index].Act = 2;\r
+ if (DataLength26) {\r
+ Trb->Adma32Desc[Index].UpperLength = 0;\r
+ }\r
+ Trb->Adma32Desc[Index].LowerLength = 0;\r
+ Trb->Adma32Desc[Index].Address = (UINT32)Address;\r
+ }\r
} else {\r
- Trb->AdmaDesc[Index].Valid = 1;\r
- Trb->AdmaDesc[Index].Act = 2;\r
- Trb->AdmaDesc[Index].Length = 0;\r
- Trb->AdmaDesc[Index].Address = Address;\r
+ if (Remaining <= AdmaMaxDataPerLine) {\r
+ Trb->Adma64Desc[Index].Valid = 1;\r
+ Trb->Adma64Desc[Index].Act = 2;\r
+ if (DataLength26) {\r
+ Trb->Adma64Desc[Index].UpperLength = (UINT16)(Remaining >> 16);\r
+ }\r
+ Trb->Adma64Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);\r
+ Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;\r
+ Trb->Adma64Desc[Index].UpperAddress = (UINT32)(Address >> 32);\r
+ break;\r
+ } else {\r
+ Trb->Adma64Desc[Index].Valid = 1;\r
+ Trb->Adma64Desc[Index].Act = 2;\r
+ if (DataLength26) {\r
+ Trb->Adma64Desc[Index].UpperLength = 0;\r
+ }\r
+ Trb->Adma64Desc[Index].LowerLength = 0;\r
+ Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;\r
+ Trb->Adma64Desc[Index].UpperAddress = (UINT32)(Address >> 32);\r
+ }\r
}\r
\r
- Remaining -= ADMA_MAX_DATA_PER_LINE;\r
- Address += ADMA_MAX_DATA_PER_LINE;\r
+ Remaining -= AdmaMaxDataPerLine;\r
+ Address += AdmaMaxDataPerLine;\r
}\r
\r
//\r
// Set the last descriptor line as end of descriptor table\r
//\r
- Trb->AdmaDesc[Index].End = 1;\r
+ AddressingMode64 ? (Trb->Adma64Desc[Index].End = 1) : (Trb->Adma32Desc[Index].End = 1);\r
return EFI_SUCCESS;\r
}\r
\r
Trb->Mode = SdMmcNoData;\r
} else if (Private->Capability[Slot].Adma2 != 0) {\r
Trb->Mode = SdMmcAdmaMode;\r
- Status = BuildAdmaDescTable (Trb);\r
+ Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);\r
if (EFI_ERROR (Status)) {\r
PciIo->Unmap (PciIo, Trb->DataMap);\r
goto Error;\r
Trb->AdmaMap\r
);\r
}\r
- if (Trb->AdmaDesc != NULL) {\r
+ if (Trb->Adma32Desc != NULL) {\r
+ PciIo->FreeBuffer (\r
+ PciIo,\r
+ Trb->AdmaPages,\r
+ Trb->Adma32Desc\r
+ );\r
+ }\r
+ if (Trb->Adma64Desc != NULL) {\r
PciIo->FreeBuffer (\r
PciIo,\r
Trb->AdmaPages,\r
- Trb->AdmaDesc\r
+ Trb->Adma64Desc\r
);\r
}\r
if (Trb->DataMap != NULL) {\r
UINT16 Cmd;\r
UINT16 IntStatus;\r
UINT32 Argument;\r
- UINT16 BlkCount;\r
+ UINT32 BlkCount;\r
UINT16 BlkSize;\r
UINT16 TransMode;\r
UINT8 HostCtrl1;\r
- UINT32 SdmaAddr;\r
+ UINT64 SdmaAddr;\r
UINT64 AdmaAddr;\r
+ BOOLEAN AddressingMode64;\r
+\r
+ AddressingMode64 = FALSE;\r
\r
Packet = Trb->Packet;\r
PciIo = Trb->Private->PciIo;\r
\r
SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);\r
\r
+ if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
+ Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),\r
+ SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);\r
+ if (!EFI_ERROR (Status)) {\r
+ AddressingMode64 = TRUE;\r
+ }\r
+ }\r
+\r
if (Trb->Mode == SdMmcSdmaMode) {\r
- if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {\r
+ if ((!AddressingMode64) &&\r
+ ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;\r
- Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);\r
+ SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;\r
+\r
+ if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
+ Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);\r
+ } else {\r
+ Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);\r
+ }\r
+\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
//\r
// Calcuate Block Count.\r
//\r
- BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);\r
+ BlkCount = (Trb->DataLen / Trb->BlockSize);\r
+ }\r
+ if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {\r
+ Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);\r
+ } else {\r
+ Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);\r
}\r
- Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;\r
UINT16 IntStatus;\r
UINT32 Response[4];\r
- UINT32 SdmaAddr;\r
+ UINT64 SdmaAddr;\r
UINT8 Index;\r
UINT8 SwReset;\r
UINT32 PioLength;\r
//\r
// Update SDMA Address register.\r
//\r
- SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r
- Status = SdMmcHcRwMmio (\r
+ SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);\r
+\r
+ if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {\r
+ Status = SdMmcHcRwMmio (\r
+ Private->PciIo,\r
+ Trb->Slot,\r
+ SD_MMC_HC_ADMA_SYS_ADDR,\r
+ FALSE,\r
+ sizeof (UINT64),\r
+ &SdmaAddr\r
+ );\r
+ } else {\r
+ Status = SdMmcHcRwMmio (\r
Private->PciIo,\r
Trb->Slot,\r
SD_MMC_HC_SDMA_ADDR,\r
sizeof (UINT32),\r
&SdmaAddr\r
);\r
+ }\r
+\r
if (EFI_ERROR (Status)) {\r
goto Done;\r
}\r
- Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;\r
+ Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;\r
}\r
\r
if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&\r
\r
Provides some data structure definitions used by the SD/MMC host controller driver.\r
\r
+Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
//\r
// The maximum data length of each descriptor line\r
//\r
-#define ADMA_MAX_DATA_PER_LINE 0x10000\r
+#define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB\r
+#define ADMA_MAX_DATA_PER_LINE_26B SIZE_64MB\r
\r
+//\r
+// ADMA descriptor for 32b addressing.\r
+//\r
typedef struct {\r
UINT32 Valid:1;\r
UINT32 End:1;\r
UINT32 Int:1;\r
UINT32 Reserved:1;\r
UINT32 Act:2;\r
- UINT32 Reserved1:10;\r
- UINT32 Length:16;\r
+ UINT32 UpperLength:10;\r
+ UINT32 LowerLength:16;\r
UINT32 Address;\r
-} SD_MMC_HC_ADMA_DESC_LINE;\r
+} SD_MMC_HC_ADMA_32_DESC_LINE;\r
+\r
+//\r
+// ADMA descriptor for 64b addressing.\r
+//\r
+typedef struct {\r
+ UINT32 Valid:1;\r
+ UINT32 End:1;\r
+ UINT32 Int:1;\r
+ UINT32 Reserved:1;\r
+ UINT32 Act:2;\r
+ UINT32 UpperLength:10;\r
+ UINT32 LowerLength:16;\r
+ UINT32 LowerAddress;\r
+ UINT32 UpperAddress;\r
+ UINT32 Reserved1;\r
+} SD_MMC_HC_ADMA_64_DESC_LINE;\r
\r
#define SD_MMC_SDMA_BOUNDARY 512 * 1024\r
#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
UINT32 Voltage33:1; // bit 24\r
UINT32 Voltage30:1; // bit 25\r
UINT32 Voltage18:1; // bit 26\r
- UINT32 Reserved3:1; // bit 27\r
- UINT32 SysBus64:1; // bit 28\r
+ UINT32 SysBus64V4:1; // bit 27\r
+ UINT32 SysBus64V3:1; // bit 28\r
UINT32 AsyncInt:1; // bit 29\r
UINT32 SlotType:2; // bit 30:31\r
UINT32 Sdr50:1; // bit 32\r
UINT32 Sdr104:1; // bit 33\r
UINT32 Ddr50:1; // bit 34\r
- UINT32 Reserved4:1; // bit 35\r
+ UINT32 Reserved3:1; // bit 35\r
UINT32 DriverTypeA:1; // bit 36\r
UINT32 DriverTypeC:1; // bit 37\r
UINT32 DriverTypeD:1; // bit 38\r
UINT32 DriverType4:1; // bit 39\r
UINT32 TimerCount:4; // bit 40:43\r
- UINT32 Reserved5:1; // bit 44\r
+ UINT32 Reserved4:1; // bit 44\r
UINT32 TuningSDR50:1; // bit 45\r
UINT32 RetuningMod:2; // bit 46:47\r
UINT32 ClkMultiplier:8; // bit 48:55\r
- UINT32 Reserved6:7; // bit 56:62\r
+ UINT32 Reserved5:7; // bit 56:62\r
UINT32 Hs400:1; // bit 63\r
} SD_MMC_HC_SLOT_CAP;\r
\r
//\r
// SD Host controller version\r
//\r
-#define SD_MMC_HC_CTRL_VER_100 0x00\r
-#define SD_MMC_HC_CTRL_VER_200 0x01\r
-#define SD_MMC_HC_CTRL_VER_300 0x02\r
-#define SD_MMC_HC_CTRL_VER_400 0x03\r
-#define SD_MMC_HC_CTRL_VER_410 0x04\r
-#define SD_MMC_HC_CTRL_VER_420 0x05\r
+#define SD_MMC_HC_CTRL_VER_100 0x00\r
+#define SD_MMC_HC_CTRL_VER_200 0x01\r
+#define SD_MMC_HC_CTRL_VER_300 0x02\r
+#define SD_MMC_HC_CTRL_VER_400 0x03\r
+#define SD_MMC_HC_CTRL_VER_410 0x04\r
+#define SD_MMC_HC_CTRL_VER_420 0x05\r
+\r
+//\r
+// SD Host controller V4 enhancements\r
+//\r
+#define SD_MMC_HC_V4_EN BIT12\r
+#define SD_MMC_HC_64_ADDR_EN BIT13\r
+#define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10\r
\r
/**\r
Dump the content of SD/MMC host controller's Capability Register.\r
IN UINT64 Timeout\r
);\r
\r
+/**\r
+ Get the controller version information from the specified slot.\r
+\r
+ @param[in] PciIo The PCI IO protocol instance.\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[out] Version The buffer to store the version information.\r
+\r
+ @retval EFI_SUCCESS The operation executes successfully.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdMmcHcGetControllerVersion (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT8 Slot,\r
+ OUT UINT16 *Version\r
+ );\r
+\r
/**\r
Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
register.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
+ @param[in] ControllerVer The version of host controller.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
IN UINT64 ClockFreq,\r
- IN UINT32 BaseClkFreq\r
+ IN UINT32 BaseClkFreq,\r
+ IN UINT16 ControllerVer\r
);\r
\r
/**\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] BaseClkFreq The base clock frequency of host controller in MHz.\r
+ @param[in] ControllerVer The version of host controller.\r
\r
@retval EFI_SUCCESS The clock is supplied successfully.\r
@retval Others The clock isn't supplied successfully.\r
SdMmcHcInitClockFreq (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT8 Slot,\r
- IN UINT32 BaseClkFreq\r
+ IN UINT32 BaseClkFreq,\r
+ IN UINT16 ControllerVer\r
);\r
\r
/**\r
projects / mirror_edk2.git / commitdiff