Improve coding style in MdeModulePkg.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / Uhci.h

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
index eb61554e0e86c3612c6893458d809d1423703c20..c2377bf3a7980cbf4d4a2afe1dcc8bccbb1c2f75 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
@@ -2,7 +2,7 @@
 \r
   The definition for UHCI driver model and HC protocol routines.\r
 \r
-Copyright (c) 2004 - 2009, Intel Corporation\r
+Copyright (c) 2004 - 2010, Intel Corporation\r
 All rights reserved. This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -45,38 +45,39 @@ typedef struct _USB_HC_DEV  USB_HC_DEV;
 #include "UhciDebug.h"\r
 #include "ComponentName.h"\r
 \r
-typedef enum {\r
-  UHC_1_MICROSECOND             = 1,\r
-  UHC_1_MILLISECOND             = 1000 * UHC_1_MICROSECOND,\r
-  UHC_1_SECOND                  = 1000 * UHC_1_MILLISECOND,\r
+//\r
+// UHC timeout experience values\r
+//\r
 \r
-  //\r
-  // UHCI register operation timeout, set by experience\r
-  //\r
-  UHC_GENERIC_TIMEOUT           = UHC_1_SECOND,\r
+#define UHC_1_MICROSECOND             1\r
+#define UHC_1_MILLISECOND             (1000 * UHC_1_MICROSECOND)\r
+#define UHC_1_SECOND                  (1000 * UHC_1_MILLISECOND)\r
 \r
-  //\r
-  // Wait for force global resume(FGR) complete, refers to\r
-  // specification[UHCI11-2.1.1]\r
-  //\r
-  UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,\r
+//\r
+// UHCI register operation timeout, set by experience\r
+//\r
+#define UHC_GENERIC_TIMEOUT           UHC_1_SECOND\r
 \r
-  //\r
-  // Wait for roothub port reset and recovery, reset stall\r
-  // is set by experience, and recovery stall refers to\r
-  // specification[UHCI11-2.1.1]\r
-  //\r
-  UHC_ROOT_PORT_RESET_STALL     = 50 * UHC_1_MILLISECOND,\r
-  UHC_ROOT_PORT_RECOVERY_STALL  = 10 * UHC_1_MILLISECOND,\r
+//\r
+// Wait for force global resume(FGR) complete, refers to\r
+// specification[UHCI11-2.1.1]\r
+//\r
+#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)\r
 \r
-  //\r
-  // Sync and Async transfer polling interval, set by experience,\r
-  // and the unit of Async is 100us.\r
-  //\r
-  UHC_SYNC_POLL_INTERVAL        = 1 * UHC_1_MILLISECOND,\r
-  UHC_ASYNC_POLL_INTERVAL       = 50 * 10000UL\r
-}UHC_TIMEOUT_EXPERIENCE_VALUE;\r
+//\r
+// Wait for roothub port reset and recovery, reset stall\r
+// is set by experience, and recovery stall refers to\r
+// specification[UHCI11-2.1.1]\r
+//\r
+#define UHC_ROOT_PORT_RESET_STALL     (50 * UHC_1_MILLISECOND)\r
+#define UHC_ROOT_PORT_RECOVERY_STALL  (10 * UHC_1_MILLISECOND)\r
 \r
+//\r
+// Sync and Async transfer polling interval, set by experience,\r
+// and the unit of Async is 100us.\r
+//\r
+#define UHC_SYNC_POLL_INTERVAL        (1 * UHC_1_MILLISECOND)\r
+#define UHC_ASYNC_POLL_INTERVAL       (50 * 10000UL)\r
 \r
 //\r
 // UHC raises TPL to TPL_NOTIFY to serialize all its operations\r
@@ -88,7 +89,7 @@ typedef enum {
 \r
 #pragma pack(1)\r
 typedef struct {\r
-  UINT8               PI;\r
+  UINT8               ProgInterface;\r
   UINT8               SubClassCode;\r
   UINT8               BaseCode;\r
 } USB_CLASSC;\r