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This file contains the definition for XHCI host controller schedule routines.\r
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-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
UINT32 TRBPtrHi;\r
\r
- UINT32 Lenth:17;\r
+ UINT32 Length:17;\r
UINT32 TDSize:5;\r
UINT32 IntTarget:10;\r
\r
UINT32 wIndex:16;\r
UINT32 wLength:16;\r
\r
- UINT32 Lenth:17;\r
+ UINT32 Length:17;\r
UINT32 RsvdZ1:5;\r
UINT32 IntTarget:10;\r
\r
\r
UINT32 TRBPtrHi;\r
\r
- UINT32 Lenth:17;\r
+ UINT32 Length:17;\r
UINT32 TDSize:5;\r
UINT32 IntTarget:10;\r
\r
\r
UINT32 TRBPtrHi;\r
\r
- UINT32 Lenth:24;\r
+ UINT32 Length:24;\r
UINT32 Completecode:8;\r
\r
UINT32 CycleBit:1;\r