MdeModulePkg/Xhci: Fill the 'interval' field for ISO endpoint context

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciSched.c

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
index 7f554f5710dfb6df0c34c54c25bb67c688273bc0..3dd2b8909787180ec94bc19af05c382a838d7ca1 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
@@ -2,7 +2,7 @@
 PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid\r
 which is used to enable recovery function from USB Drivers.\r
 \r
-Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
@@ -1195,6 +1195,10 @@ XhcPeiInitializeDeviceSlot (
   // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
   //    Context data structure described above.\r
   //\r
+  // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request\r
+  // to device.\r
+  //\r
+  MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);\r
   ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
   PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r
   CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
@@ -1402,6 +1406,10 @@ XhcPeiInitializeDeviceSlot64 (
   // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
   //    Context data structure described above.\r
   //\r
+  // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request\r
+  // to device.\r
+  //\r
+  MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);\r
   ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
   PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r
   CmdTrbAddr.PtrLo    = XHC_LOW_32BIT (PhyAddr);\r
@@ -1741,6 +1749,20 @@ XhcPeiSetConfigCmd (
             InputContext->EP[Dci-1].CErr   = 0;\r
             InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
           }\r
+          //\r
+          // Get the bInterval from descriptor and init the the interval field of endpoint context.\r
+          // Refer to XHCI 1.1 spec section 6.2.3.6.\r
+          //\r
+          if (DeviceSpeed == EFI_USB_SPEED_FULL) {\r
+            Interval = EpDesc->Interval;\r
+            ASSERT (Interval >= 1 && Interval <= 16);\r
+            InputContext->EP[Dci-1].Interval = Interval + 2;\r
+          } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
+            Interval = EpDesc->Interval;\r
+            ASSERT (Interval >= 1 && Interval <= 16);\r
+            InputContext->EP[Dci-1].Interval = Interval - 1;\r
+          }\r
+\r
           //\r
           // Do not support isochronous transfer now.\r
           //\r
@@ -1944,6 +1966,20 @@ XhcPeiSetConfigCmd64 (
             InputContext->EP[Dci-1].CErr   = 0;\r
             InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
           }\r
+          //\r
+          // Get the bInterval from descriptor and init the the interval field of endpoint context.\r
+          // Refer to XHCI 1.1 spec section 6.2.3.6.\r
+          //\r
+          if (DeviceSpeed == EFI_USB_SPEED_FULL) {\r
+            Interval = EpDesc->Interval;\r
+            ASSERT (Interval >= 1 && Interval <= 16);\r
+            InputContext->EP[Dci-1].Interval = Interval + 2;\r
+          } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
+            Interval = EpDesc->Interval;\r
+            ASSERT (Interval >= 1 && Interval <= 16);\r
+            InputContext->EP[Dci-1].Interval = Interval - 1;\r
+          }\r
+\r
           //\r
           // Do not support isochronous transfer now.\r
           //\r