/** @file\r
Ia32-specific functionality for DxeLoad.\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
IN EFI_PHYSICAL_ADDRESS StackBase,\r
IN UINTN StackSize\r
)\r
-{ \r
+{\r
UINT8 PhysicalAddressBits;\r
EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
UINTN IndexOfPdpEntries;\r
NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));\r
\r
TotalPagesNum = NumberOfPdpEntriesNeeded + 1;\r
- PageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
+ PageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);\r
ASSERT (PageAddress != 0);\r
\r
PageMap = (VOID *) PageAddress;\r
//\r
// Each Directory Pointer entries points to a page of Page Directory entires.\r
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
- // \r
+ //\r
PageDirectoryEntry = (VOID *) PageAddress;\r
PageAddress += SIZE_4KB;\r
\r
);\r
}\r
\r
+ //\r
+ // Protect the page table by marking the memory used for page table to be\r
+ // read-only.\r
+ //\r
+ EnablePageTableProtection ((UINTN)PageMap, FALSE);\r
+\r
return (UINTN) PageMap;\r
}\r
\r
return TRUE;\r
}\r
\r
+ if (PcdGetBool (PcdCpuStackGuard)) {\r
+ return TRUE;\r
+ }\r
+\r
if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable ()) {\r
return TRUE;\r
}\r
//\r
// End of PEI phase signal\r
//\r
+ PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);\r
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
+ PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);\r
ASSERT_EFI_ERROR (Status);\r
\r
AsmWriteCr3 (PageTables);\r
//\r
// End of PEI phase signal\r
//\r
+ PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);\r
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
+ PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);\r
ASSERT_EFI_ERROR (Status);\r
\r
if (BuildPageTablesIa32Pae) {\r