+/**\r
+ Allocates and fills in the Page Directory and Page Table Entries to\r
+ establish a 4G page table.\r
+\r
+ @param[in] StackBase Stack base address.\r
+ @param[in] StackSize Stack size.\r
+\r
+ @return The address of page table.\r
+\r
+**/\r
+UINTN\r
+Create4GPageTablesIa32Pae (\r
+ IN EFI_PHYSICAL_ADDRESS StackBase,\r
+ IN UINTN StackSize\r
+ )\r
+{\r
+ UINT8 PhysicalAddressBits;\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ UINTN IndexOfPdpEntries;\r
+ UINTN IndexOfPageDirectoryEntries;\r
+ UINT32 NumberOfPdpEntriesNeeded;\r
+ PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
+ PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
+ PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
+ UINTN TotalPagesNum;\r
+ UINTN PageAddress;\r
+ UINT64 AddressEncMask;\r
+\r
+ //\r
+ // Make sure AddressEncMask is contained to smallest supported address field\r
+ //\r
+ AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
+\r
+ PhysicalAddressBits = 32;\r
+\r
+ //\r
+ // Calculate the table entries needed.\r
+ //\r
+ NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));\r
+\r
+ TotalPagesNum = NumberOfPdpEntriesNeeded + 1;\r
+ PageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);\r
+ ASSERT (PageAddress != 0);\r
+\r
+ PageMap = (VOID *) PageAddress;\r
+ PageAddress += SIZE_4KB;\r
+\r
+ PageDirectoryPointerEntry = PageMap;\r
+ PhysicalAddress = 0;\r
+\r
+ for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
+ //\r
+ // Each Directory Pointer entries points to a page of Page Directory entires.\r
+ // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
+ //\r
+ PageDirectoryEntry = (VOID *) PageAddress;\r
+ PageAddress += SIZE_4KB;\r
+\r
+ //\r
+ // Fill in a Page Directory Pointer Entries\r
+ //\r
+ PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask;\r
+ PageDirectoryPointerEntry->Bits.Present = 1;\r
+\r
+ for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) {\r
+ if ((IsNullDetectionEnabled () && PhysicalAddress == 0)\r
+ || ((PhysicalAddress < StackBase + StackSize)\r
+ && ((PhysicalAddress + SIZE_2MB) > StackBase))) {\r
+ //\r
+ // Need to split this 2M page that covers stack range.\r
+ //\r
+ Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);\r
+ } else {\r
+ //\r
+ // Fill in the Page Directory entries\r
+ //\r
+ PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress | AddressEncMask;\r
+ PageDirectoryEntry->Bits.ReadWrite = 1;\r
+ PageDirectoryEntry->Bits.Present = 1;\r
+ PageDirectoryEntry->Bits.MustBe1 = 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
+ ZeroMem (\r
+ PageDirectoryPointerEntry,\r
+ sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
+ );\r
+ }\r
+\r
+ //\r
+ // Protect the page table by marking the memory used for page table to be\r
+ // read-only.\r
+ //\r
+ EnablePageTableProtection ((UINTN)PageMap, FALSE);\r
+\r
+ return (UINTN) PageMap;\r
+}\r
+\r
+/**\r
+ The function will check if IA32 PAE is supported.\r
+\r
+ @retval TRUE IA32 PAE is supported.\r
+ @retval FALSE IA32 PAE is not supported.\r
+\r
+**/\r
+BOOLEAN\r
+IsIa32PaeSupport (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ BOOLEAN Ia32PaeSupport;\r
+\r
+ Ia32PaeSupport = FALSE;\r
+ AsmCpuid (0x0, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= 0x1) {\r
+ AsmCpuid (0x1, NULL, NULL, NULL, &RegEdx);\r
+ if ((RegEdx & BIT6) != 0) {\r
+ Ia32PaeSupport = TRUE;\r
+ }\r
+ }\r
+\r
+ return Ia32PaeSupport;\r
+}\r
+\r
+/**\r
+ The function will check if Execute Disable Bit is available.\r
+\r
+ @retval TRUE Execute Disable Bit is available.\r
+ @retval FALSE Execute Disable Bit is not available.\r
+\r
+**/\r
+BOOLEAN\r
+IsExecuteDisableBitAvailable (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ BOOLEAN Available;\r
+\r
+ Available = FALSE;\r
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= 0x80000001) {\r
+ AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
+ if ((RegEdx & BIT20) != 0) {\r
+ //\r
+ // Bit 20: Execute Disable Bit available.\r
+ //\r
+ Available = TRUE;\r
+ }\r
+ }\r
+\r
+ return Available;\r
+}\r
+\r
+/**\r
+ The function will check if page table should be setup or not.\r
+\r
+ @retval TRUE Page table should be created.\r
+ @retval FALSE Page table should not be created.\r
+\r
+**/\r
+BOOLEAN\r
+ToBuildPageTable (\r
+ VOID\r
+ )\r
+{\r
+ if (!IsIa32PaeSupport ()) {\r
+ return FALSE;\r
+ }\r
+\r
+ if (IsNullDetectionEnabled ()) {\r
+ return TRUE;\r
+ }\r
+\r
+ if (PcdGet8 (PcdHeapGuardPropertyMask) != 0) {\r
+ return TRUE;\r
+ }\r
+\r
+ if (PcdGetBool (PcdCpuStackGuard)) {\r
+ return TRUE;\r
+ }\r
+\r
+ if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable ()) {\r
+ return TRUE;\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Transfers control to DxeCore.\r
+\r
+ This function performs a CPU architecture specific operations to execute\r
+ the entry point of DxeCore with the parameters of HobList.\r
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.\r
+\r
+ @param DxeCoreEntryPoint The entry point of DxeCore.\r
+ @param HobList The start of HobList passed to DxeCore.\r
+\r
+**/\r