MdeModulePkg/Core/DxeIplPeim: Add support for PCD PcdPteMemoryEncryptionAddressOrMask

[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.h

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
index 87a27b08243e96430455f1376c09f0a916cc7a5b..7c9bb49e3e2cffe60797403bb0bdc6131c7074a1 100644 (file)
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
@@ -7,7 +7,9 @@
     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
 \r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -23,6 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #define SYS_CODE64_SEL 0x38\r
 \r
+\r
 #pragma pack(1)\r
 \r
 typedef union {\r
@@ -73,6 +76,28 @@ typedef union {
   UINT64    Uint64;\r
 } PAGE_MAP_AND_DIRECTORY_POINTER;\r
 \r
+//\r
+// Page Table Entry 4KB\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
+    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
+    UINT64  PAT:1;                    //\r
+    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+    UINT64  Available:3;              // Available for use by system software\r
+    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
+    UINT64  AvabilableHigh:11;        // Available for use by system software\r
+    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
+  } Bits;\r
+  UINT64    Uint64;\r
+} PAGE_TABLE_4K_ENTRY;\r
+\r
 //\r
 // Page Table Entry 2MB\r
 //\r
@@ -123,22 +148,51 @@ typedef union {
 \r
 #pragma pack()\r
 \r
+#define IA32_PG_P                   BIT0\r
+#define IA32_PG_RW                  BIT1\r
+\r
+#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
+\r
+/**\r
+  Enable Execute Disable Bit.\r
+\r
+**/\r
+VOID\r
+EnableExecuteDisableBit (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Split 2M page to 4K.\r
+\r
+  @param[in]      PhysicalAddress       Start physical address the 2M page covered.\r
+  @param[in, out] PageEntry2M           Pointer to 2M page entry.\r
+  @param[in]      StackBase             Stack base address.\r
+  @param[in]      StackSize             Stack size.\r
+\r
+**/\r
+VOID\r
+Split2MPageTo4K (\r
+  IN EFI_PHYSICAL_ADDRESS               PhysicalAddress,\r
+  IN OUT UINT64                         *PageEntry2M,\r
+  IN EFI_PHYSICAL_ADDRESS               StackBase,\r
+  IN UINTN                              StackSize\r
+  );\r
 \r
 /**\r
   Allocates and fills in the Page Directory and Page Table Entries to\r
   establish a 1:1 Virtual to Physical mapping.\r
 \r
-  @param  NumberOfProcessorPhysicalAddressBits  Number of processor address bits \r
-                                                to use. Limits the number of page \r
-                                                table entries  to the physical \r
-                                                address space. \r
+  @param[in] StackBase  Stack base address.\r
+  @param[in] StackSize  Stack size.\r
 \r
   @return The address of 4 level page map.\r
 \r
 **/\r
 UINTN\r
 CreateIdentityMappingPageTables (\r
-  VOID\r
+  IN EFI_PHYSICAL_ADDRESS   StackBase,\r
+  IN UINTN                  StackSize\r
   );\r
 \r
 \r