/** @file \r
- ACPI 2.0 definitions from the ACPI Specification, revision 2.0\r
+ ACPI 2.0 definitions from the ACPI Specification, revision 2.0\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation\r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
#ifndef _ACPI_2_0_H_\r
#define _ACPI_2_0_H_\r
\r
-#include <IndustryStandard/Acpi1_0.h>\r
+#include <IndustryStandard/Acpi10.h>\r
+\r
+//\r
+// Define for Desriptor\r
+//\r
+#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02\r
+\r
+#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
+///\r
+/// Generic Register Descriptor\r
+///\r
+typedef PACKED struct {\r
+ ACPI_LARGE_RESOURCE_HEADER Header;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AddressSize;\r
+ UINT64 RegisterAddress;\r
+} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR;\r
+\r
+#pragma pack()\r
\r
//\r
// Ensure proper structure formats\r
///\r
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03\r
\r
-///\r
-/// Fixed ACPI Description Table Boot Architecture Flags\r
-/// All other bits are reserved and must be set to 0.\r
-///\r
-#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)\r
-#define EFI_ACPI_2_0_8042 (1 << 1)\r
+//\r
+// Fixed ACPI Description Table Preferred Power Management Profile\r
+//\r
+#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0\r
+#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1\r
+#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2\r
+#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3\r
+#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4\r
+#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5\r
+#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6\r
+\r
+//\r
+// Fixed ACPI Description Table Boot Architecture Flags\r
+// All other bits are reserved and must be set to 0.\r
+//\r
+#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_2_0_8042 BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_2_0_WBINVD (1 << 0)\r
-#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)\r
-#define EFI_ACPI_2_0_PROC_C1 (1 << 2)\r
-#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)\r
-#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)\r
-#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)\r
-#define EFI_ACPI_2_0_FIX_RTC (1 << 6)\r
-#define EFI_ACPI_2_0_RTC_S4 (1 << 7)\r
-#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)\r
-#define EFI_ACPI_2_0_DCK_CAP (1 << 9)\r
-#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)\r
-#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)\r
-#define EFI_ACPI_2_0_HEADLESS (1 << 12)\r
-#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)\r
+#define EFI_ACPI_2_0_WBINVD BIT0\r
+#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_2_0_PROC_C1 BIT2\r
+#define EFI_ACPI_2_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_2_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_2_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_2_0_FIX_RTC BIT6\r
+#define EFI_ACPI_2_0_RTC_S4 BIT7\r
+#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_2_0_DCK_CAP BIT9\r
+#define EFI_ACPI_2_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_2_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_2_0_HEADLESS BIT12\r
+#define EFI_ACPI_2_0_CPU_SW_SLP BIT13\r
\r
///\r
/// Firmware ACPI Control Structure\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_2_0_S4BIOS_F BIT0\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)\r
+#define EFI_ACPI_2_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
/// "RSD PTR " Root System Description Pointer\r
///\r
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352\r
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\r
\r
///\r
/// "SPIC" Multiple SAPIC Description Table\r
/// BUGBUG: Don't know where this came from except SR870BN4 uses it.\r
/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053\r
///\r
-#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041\r
+#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\r
\r
///\r
/// "BOOT" MS Simple Boot Spec\r
///\r
-#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42\r
+#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\r
\r
///\r
/// "DBGP" MS Bebug Port Spec\r
///\r
-#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244\r
+#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\r
\r
///\r
/// "DSDT" Differentiated System Description Table\r
///\r
-#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344\r
+#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\r
\r
///\r
/// "ECDT" Embedded Controller Boot Resources Table\r
///\r
-#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345\r
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\r
\r
///\r
/// "ETDT" Event Timer Description Table\r
///\r
-#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445\r
+#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\r
\r
///\r
/// "FACS" Firmware ACPI Control Structure\r
///\r
-#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146\r
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\r
\r
///\r
/// "FACP" Fixed ACPI Description Table\r
///\r
-#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146\r
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\r
\r
///\r
/// "APIC" Multiple APIC Description Table\r
///\r
-#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041\r
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\r
\r
///\r
/// "PSDT" Persistent System Description Table\r
///\r
-#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350\r
+#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\r
\r
///\r
/// "RSDT" Root System Description Table\r
///\r
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352\r
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\r
\r
///\r
/// "SBST" Smart Battery Specification Table\r
///\r
-#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253\r
+#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\r
\r
///\r
/// "SLIT" System Locality Information Table\r
///\r
-#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53\r
+#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\r
\r
///\r
/// "SPCR" Serial Port Concole Redirection Table\r
///\r
-#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053\r
+#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\r
\r
///\r
/// "SRAT" Static Resource Affinity Table\r
///\r
-#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253\r
+#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\r
\r
///\r
/// "SSDT" Secondary System Description Table\r
///\r
-#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353\r
+#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\r
\r
///\r
/// "SPMI" Server Platform Management Interface Table\r
///\r
-#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE 0x494D5053\r
+#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\r
\r
///\r
/// "XSDT" Extended System Description Table\r
///\r
-#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358\r
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\r
\r
///\r
-/// "MCFG" Static Resource Affinity Table\r
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table\r
///\r
-#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D\r
+#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\r
\r
#pragma pack()\r
\r
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