PCI Local Bus Specification, 2.2\r
PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
PC Card Standard, 8.0\r
+ PCI Power Management Interface Specifiction, Revision 1.2\r
\r
- \r
-\r
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
- Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r
\r
struct {\r
UINT16 Version : 3;\r
UINT16 PmeClock : 1;\r
- UINT16 : 1;\r
+ UINT16 Reserved : 1;\r
UINT16 DeviceSpecificInitialization : 1;\r
UINT16 AuxCurrent : 3;\r
UINT16 D1Support : 1;\r
typedef union {\r
struct {\r
UINT16 PowerState : 2;\r
- UINT16 : 6;\r
+ UINT16 Reserved : 6;\r
UINT16 PmeEnable : 1;\r
UINT16 DataSelect : 4;\r
UINT16 DataScale : 2;\r