/** @file\r
Provides string functions, linked list functions, math functions, synchronization\r
- functions, and CPU architecture specific functions.\r
+ functions, and CPU architecture-specific functions.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
+Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef __BASE_LIB__\r
#define __BASE_LIB__\r
\r
-///\r
-/// Definitions for SPIN_LOCK\r
-///\r
-typedef volatile UINTN SPIN_LOCK;\r
-\r
//\r
-// Definitions for architecture specific types\r
+// Definitions for architecture-specific types\r
//\r
#if defined (MDE_CPU_IA32)\r
///\r
-/// IA32 context buffer used by SetJump() and LongJump()\r
+/// IA-32 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT32 Ebx;\r
#if defined (MDE_CPU_IPF)\r
\r
///\r
-/// IPF context buffer used by SetJump() and LongJump()\r
+/// Itanium architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 F2[2];\r
\r
#if defined (MDE_CPU_X64)\r
///\r
-/// x64 context buffer used by SetJump() and LongJump()\r
+/// x64 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 Rbx;\r
If Length > 0 and Destination is NULL, then ASSERT().\r
If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().\r
If Length > 0 and Source is NULL, then ASSERT().\r
- If Length > 0 and Source is not aligned on a 16-bit bounadry, then ASSERT().\r
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
- PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated Unicode string.\r
@param Source Pointer to a Null-terminated Unicode string.\r
subtracted from the first mismatched Unicode character in FirstString.\r
\r
If Length > 0 and FirstString is NULL, then ASSERT().\r
- If Length > 0 and FirstString is not aligned on a 16-bit bounadary, then ASSERT().\r
+ If Length > 0 and FirstString is not aligned on a 16-bit boundary, then ASSERT().\r
If Length > 0 and SecondString is NULL, then ASSERT().\r
- If Length > 0 and SecondString is not aligned on a 16-bit bounadary, then ASSERT().\r
- If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more\r
- than PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
- If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more\r
- than PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
+ If Length > 0 and SecondString is not aligned on a 16-bit boundary, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than\r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
\r
@param FirstString Pointer to a Null-terminated Unicode string.\r
@param SecondString Pointer to a Null-terminated Unicode string.\r
results are undefined.\r
\r
If Destination is NULL, then ASSERT().\r
- If Destination is not aligned on a 16-bit bounadary, then ASSERT().\r
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().\r
If Source is NULL, then ASSERT().\r
- If Source is not aligned on a 16-bit bounadary, then ASSERT().\r
+ If Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Destination contains more\r
than PcdMaximumUnicodeStringLength Unicode characters not including the\r
If Length > 0 and Source is NULL, then ASSERT().\r
If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Destination contains more\r
- than PcdMaximumUnicodeStringLength Unicode characters not including the\r
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the\r
Null-terminator, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
- PcdMaximumUnicodeStringLength Unicode characters not including the\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
Null-terminator, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and concatenating Destination\r
- and Source results in a Unicode string with more than\r
- PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
+ and Source results in a Unicode string with more than PcdMaximumUnicodeStringLength\r
+ Unicode characters, not including the Null-terminator, then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated Unicode string.\r
@param Source Pointer to a Null-terminated Unicode string.\r
If Destination is NULL, then ASSERT().\r
If Source is NULL, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated ASCII string.\r
\r
If Length > 0 and FirstString is NULL, then ASSERT().\r
If Length > 0 and SecondString is NULL, then ASSERT().\r
- If PcdMaximumAsciiStringLength is not zero and FirstString contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
- If PcdMaximumAsciiStringLength is not zero and SecondString contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ If PcdMaximumAsciiStringLength is not zero, and SecondString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
\r
@param FirstString Pointer to a Null-terminated ASCII string.\r
If Length > 0 and Destination is NULL, then ASSERT().\r
If Length > 0 and Source is NULL, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than\r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and Destination contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and concatenating Destination and\r
Source results in a ASCII string with more than PcdMaximumAsciiStringLength\r
- ASCII characters not including the Null-terminator, then ASSERT().\r
+ ASCII characters, not including the Null-terminator, then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated ASCII string.\r
@param Source Pointer to a Null-terminated ASCII string.\r
instead if calling the InitializeListHead() function to perform the\r
equivalent operation.\r
\r
- @param ListHead The head note of a list to initiailize.\r
+ @param ListHead The head note of a list to initialize.\r
\r
**/\r
#define INITIALIZE_LIST_HEAD_VARIABLE(ListHead) {&(ListHead), &(ListHead)}\r
@param Operand The 32-bit operand to rotate right.\r
@param Count The number of bits to rotate right.\r
\r
- @return Operand >>> Count\r
+ @return Operand >> Count\r
\r
**/\r
UINT32\r
from little endian to big endian or vice versa. The byte swapped value is\r
returned.\r
\r
- @param Value Operand A 16-bit unsigned value.\r
+ @param Value A 16-bit unsigned value.\r
\r
- @return The byte swapped Operand.\r
+ @return The byte swapped Value.\r
\r
**/\r
UINT16\r
from little endian to big endian or vice versa. The byte swapped value is\r
returned.\r
\r
- @param Value Operand A 32-bit unsigned value.\r
+ @param Value A 32-bit unsigned value.\r
\r
- @return The byte swapped Operand.\r
+ @return The byte swapped Value.\r
\r
**/\r
UINT32\r
from little endian to big endian or vice versa. The byte swapped value is\r
returned.\r
\r
- @param Value Operand A 64-bit unsigned value.\r
+ @param Value A 64-bit unsigned value.\r
\r
- @return The byte swapped Operand.\r
+ @return The byte swapped Value.\r
\r
**/\r
UINT64\r
unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
bit unsigned result is returned.\r
\r
- If the result overflows, then ASSERT().\r
-\r
@param Multiplicand A 64-bit unsigned value.\r
@param Multiplier A 64-bit unsigned value.\r
\r
IN UINT64 OrData\r
);\r
\r
-\r
-//\r
-// Base Library Synchronization Functions\r
-//\r
-\r
-/**\r
- Retrieves the architecture specific spin lock alignment requirements for\r
- optimal spin lock performance.\r
-\r
- This function retrieves the spin lock alignment requirements for optimal\r
- performance on a given CPU architecture. The spin lock alignment must be a\r
- power of two and is returned by this function. If there are no alignment\r
- requirements, then 1 must be returned. The spin lock synchronization\r
- functions must function correctly if the spin lock size and alignment values\r
- returned by this function are not used at all. These values are hints to the\r
- consumers of the spin lock synchronization functions to obtain optimal spin\r
- lock performance.\r
-\r
- @return The architecture specific spin lock alignment.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-GetSpinLockProperties (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Initializes a spin lock to the released state and returns the spin lock.\r
-\r
- This function initializes the spin lock specified by SpinLock to the released\r
- state, and returns SpinLock. Optimal performance can be achieved by calling\r
- GetSpinLockProperties() to determine the size and alignment requirements for\r
- SpinLock.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to initialize to the released\r
- state.\r
-\r
- @return SpinLock in release state.\r
-\r
-**/\r
-SPIN_LOCK *\r
-EFIAPI\r
-InitializeSpinLock (\r
- OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Waits until a spin lock can be placed in the acquired state.\r
-\r
- This function checks the state of the spin lock specified by SpinLock. If\r
- SpinLock is in the released state, then this function places SpinLock in the\r
- acquired state and returns SpinLock. Otherwise, this function waits\r
- indefinitely for the spin lock to be released, and then places it in the\r
- acquired state and returns SpinLock. All state transitions of SpinLock must\r
- be performed using MP safe mechanisms.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
- If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().\r
- If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in\r
- PcdSpinLockTimeout microseconds, then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to place in the acquired state.\r
-\r
- @return SpinLock acquired lock.\r
-\r
-**/\r
-SPIN_LOCK *\r
-EFIAPI\r
-AcquireSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Attempts to place a spin lock in the acquired state.\r
-\r
- This function checks the state of the spin lock specified by SpinLock. If\r
- SpinLock is in the released state, then this function places SpinLock in the\r
- acquired state and returns TRUE. Otherwise, FALSE is returned. All state\r
- transitions of SpinLock must be performed using MP safe mechanisms.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
- If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to place in the acquired state.\r
-\r
- @retval TRUE SpinLock was placed in the acquired state.\r
- @retval FALSE SpinLock could not be acquired.\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-AcquireSpinLockOrFail (\r
- IN OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Releases a spin lock.\r
-\r
- This function places the spin lock specified by SpinLock in the release state\r
- and returns SpinLock.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
- If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to release.\r
-\r
- @return SpinLock released lock.\r
-\r
-**/\r
-SPIN_LOCK *\r
-EFIAPI\r
-ReleaseSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic increment of an 32-bit unsigned integer.\r
-\r
- Performs an atomic increment of the 32-bit unsigned integer specified by\r
- Value and returns the incremented value. The increment operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 32-bit value to increment.\r
-\r
- @return The incremented value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InterlockedIncrement (\r
- IN UINT32 *Value\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic decrement of an 32-bit unsigned integer.\r
-\r
- Performs an atomic decrement of the 32-bit unsigned integer specified by\r
- Value and returns the decremented value. The decrement operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 32-bit value to decrement.\r
-\r
- @return The decremented value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InterlockedDecrement (\r
- IN UINT32 *Value\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
-\r
- Performs an atomic compare exchange operation on the 32-bit unsigned integer\r
- specified by Value. If Value is equal to CompareValue, then Value is set to\r
- ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,\r
- then Value is returned. The compare exchange operation must be performed using\r
- MP safe mechanisms.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 32-bit value for the compare exchange\r
- operation.\r
- @param CompareValue 32-bit value used in compare operation.\r
- @param ExchangeValue 32-bit value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InterlockedCompareExchange32 (\r
- IN OUT UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
-\r
- Performs an atomic compare exchange operation on the 64-bit unsigned integer specified\r
- by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and\r
- CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.\r
- The compare exchange operation must be performed using MP safe mechanisms.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 64-bit value for the compare exchange\r
- operation.\r
- @param CompareValue 64-bit value used in compare operation.\r
- @param ExchangeValue 64-bit value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-InterlockedCompareExchange64 (\r
- IN OUT UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a pointer value.\r
-\r
- Performs an atomic compare exchange operation on the pointer value specified\r
- by Value. If Value is equal to CompareValue, then Value is set to\r
- ExchangeValue and CompareValue is returned. If Value is not equal to\r
- CompareValue, then Value is returned. The compare exchange operation must be\r
- performed using MP safe mechanisms.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the pointer value for the compare exchange\r
- operation.\r
- @param CompareValue Pointer value used in compare operation.\r
- @param ExchangeValue Pointer value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-**/\r
-VOID *\r
-EFIAPI\r
-InterlockedCompareExchangePointer (\r
- IN OUT VOID **Value,\r
- IN VOID *CompareValue,\r
- IN VOID *ExchangeValue\r
- );\r
-\r
-\r
//\r
// Base Library Checksum Functions\r
//\r
calls to LongJump() cause a non-zero value to be returned by SetJump().\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
\r
NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.\r
The same structure must never be used for more than one CPU architecture context.\r
the state of JumpBuffer.\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
If Value is 0, then ASSERT().\r
\r
@param JumpBuffer A pointer to CPU context buffer.\r
by Context1 and Context2. Context1 and Context2 are optional and may\r
be NULL. The function EntryPoint must never return. This function\r
supports a variable number of arguments following the NewStack parameter.\r
- These additional arguments are ignored on IA-32, x64, and EBC.\r
- IPF CPUs expect one additional parameter of type VOID * that specifies\r
+ These additional arguments are ignored on IA-32, x64, and EBC architectures.\r
+ Itanium processors expect one additional parameter of type VOID * that specifies\r
the new backing store pointer.\r
\r
If EntryPoint is NULL, then ASSERT().\r
function.\r
@param NewStack A pointer to the new stack to use for the EntryPoint\r
function.\r
- @param ... This variable argument list is ignored for IA32, x64, and EBC. \r
- For IPF, this variable argument list is expected to contain \r
+ @param ... This variable argument list is ignored for IA-32, x64, and EBC architectures. \r
+ For Itanium processors, this variable argument list is expected to contain \r
a single parameter of type VOID * that specifies the new backing \r
store pointer.\r
\r
CpuDeadLoop (\r
VOID\r
);\r
+ \r
#if defined (MDE_CPU_IPF)\r
\r
/**\r
line containing Address + Length - 1 is flushed. This function may choose to flush \r
the entire cache if that is more efficient than flushing the specified range. If \r
Length is 0, the no cache lines are flushed. Address is returned. \r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
Executes a FC instruction\r
Executes a FC instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
Executes a FC.I instruction.\r
Executes a FC.I instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
No parameter checking is performed on Index. If the Index value is beyond the\r
implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
must either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults. This function is only available on IPF.\r
+ catch the faults. This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Processor Identifier Register index to read.\r
\r
\r
/**\r
Reads the current value of 64-bit Processor Status Register (PSR).\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of PSR.\r
\r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults. This function is only available on IPF.\r
+ fault handlers to catch the faults. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PSR.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #0 (KR0).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of KR0. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR0.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #1 (KR1).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR1. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR1.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #2 (KR2).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR2. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR2.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #3 (KR3).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR3. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR3.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #4 (KR4).\r
- This function is only available on IPF.\r
\r
+ Reads and returns the current value of KR4. \r
+ This function is only available on Itanium processors.\r
+ \r
@return The current value of KR4.\r
\r
**/\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #5 (KR5).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR5. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR5.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #6 (KR6).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR6. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR6.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #7 (KR7).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR7. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR7.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #0 (KR0).\r
- This function is only available on IPF.\r
+ \r
+ Writes the current value of KR0. The 64-bit value written to \r
+ the KR0 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR0.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #1 (KR1).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR1. The 64-bit value written to \r
+ the KR1 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR1.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #2 (KR2).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR2. The 64-bit value written to \r
+ the KR2 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR2.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #3 (KR3).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR3. The 64-bit value written to \r
+ the KR3 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR3.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #4 (KR4).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR4. The 64-bit value written to \r
+ the KR4 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR4.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #5 (KR5).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR5. The 64-bit value written to \r
+ the KR5 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR5.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #6 (KR6).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR6. The 64-bit value written to \r
+ the KR6 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR6.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #7 (KR7).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR7. The 64-bit value written to \r
+ the KR7 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR7.\r
\r
\r
/**\r
Reads the current value of Interval Timer Counter Register (ITC).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of ITC.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITC.\r
\r
\r
/**\r
Reads the current value of Interval Timer Vector Register (ITV).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of ITV. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITV.\r
\r
\r
/**\r
Reads the current value of Interval Timer Match Register (ITM).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of ITM.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITM.\r
**/\r
\r
/**\r
Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
- This function is only available on IPF.\r
+ \r
+ Writes the current value of ITC. The 64-bit value written to the ITC is returned. \r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITC.\r
\r
\r
/**\r
Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
- This function is only available on IPF.\r
+ \r
+ Writes the current value of ITM. The 64-bit value written to the ITM is returned. \r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITM.\r
\r
\r
/**\r
Writes the current value of 64-bit Interval Timer Vector Register (ITV).\r
+ \r
+ Writes the current value of ITV. The 64-bit value written to the ITV is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITV.\r
\r
\r
/**\r
Reads the current value of Default Control Register (DCR).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
\r
@return The current value of DCR.\r
\r
\r
/**\r
Reads the current value of Interruption Vector Address Register (IVA).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
\r
@return The current value of IVA.\r
**/\r
\r
/**\r
Reads the current value of Page Table Address Register (PTA).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
\r
@return The current value of PTA.\r
\r
\r
/**\r
Writes the current value of 64-bit Default Control Register (DCR).\r
+ \r
+ Writes the current value of DCR. The 64-bit value written to the DCR is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to DCR.\r
\r
\r
/**\r
Writes the current value of 64-bit Interruption Vector Address Register (IVA).\r
+ \r
+ Writes the current value of IVA. The 64-bit value written to the IVA is returned. \r
The size of vector table is 32 K bytes and is 32 K bytes aligned\r
the low 15 bits of Value is ignored when written.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to IVA.\r
\r
\r
/**\r
Writes the current value of 64-bit Page Table Address Register (PTA).\r
+ \r
+ Writes the current value of PTA. The 64-bit value written to the PTA is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PTA.\r
\r
\r
/**\r
Reads the current value of Local Interrupt ID Register (LID).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of LID. This function is only available on Itanium processors.\r
\r
@return The current value of LID.\r
\r
\r
/**\r
Reads the current value of External Interrupt Vector Register (IVR).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IVR. This function is only available on Itanium processors. \r
\r
@return The current value of IVR.\r
\r
\r
/**\r
Reads the current value of Task Priority Register (TPR).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of TPR. This function is only available on Itanium processors. \r
\r
@return The current value of TPR.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #0 (IRR0).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR0. This function is only available on Itanium processors. \r
\r
@return The current value of IRR0.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #1 (IRR1).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR1. This function is only available on Itanium processors. \r
\r
@return The current value of IRR1.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #2 (IRR2).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
\r
@return The current value of IRR2.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #3 (IRR3).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR3. This function is only available on Itanium processors. \r
\r
@return The current value of IRR3.\r
\r
\r
/**\r
Reads the current value of Performance Monitor Vector Register (PMV).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of PMV. This function is only available on Itanium processors. \r
\r
@return The current value of PMV.\r
\r
\r
/**\r
Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
\r
@return The current value of CMCV.\r
\r
\r
/**\r
Reads the current value of Local Redirection Register #0 (LRR0).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of LRR0. This function is only available on Itanium processors. \r
\r
@return The current value of LRR0.\r
\r
\r
/**\r
Reads the current value of Local Redirection Register #1 (LRR1).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
\r
@return The current value of LRR1.\r
\r
\r
/**\r
Writes the current value of 64-bit Page Local Interrupt ID Register (LID).\r
+ \r
+ Writes the current value of LID. The 64-bit value written to the LID is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LID.\r
\r
\r
/**\r
Writes the current value of 64-bit Task Priority Register (TPR).\r
+ \r
+ Writes the current value of TPR. The 64-bit value written to the TPR is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to TPR.\r
\r
\r
/**\r
Performs a write operation on End OF External Interrupt Register (EOI).\r
- Writes a value of 0 to the EOI Register. This function is only available on IPF.\r
+ \r
+ Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
\r
**/\r
VOID\r
\r
/**\r
Writes the current value of 64-bit Performance Monitor Vector Register (PMV).\r
+ \r
+ Writes the current value of PMV. The 64-bit value written to the PMV is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PMV.\r
\r
\r
/**\r
Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).\r
+ \r
+ Writes the current value of CMCV. The 64-bit value written to the CMCV is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to CMCV.\r
\r
\r
/**\r
Writes the current value of 64-bit Local Redirection Register #0 (LRR0).\r
+ \r
+ Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR0.\r
\r
\r
/**\r
Writes the current value of 64-bit Local Redirection Register #1 (LRR1).\r
+ \r
+ Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR1.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to read.\r
\r
the implemented DBR register range, a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Index is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to read.\r
\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMC register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to read.\r
\r
- @return The current value of Performance Monitor Configuration Register\r
- specified by Index.\r
+ @return The current value of Performance Monitor Configuration Register\r
+ specified by Index.\r
\r
**/\r
UINT64\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMD register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to read.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to write.\r
@param Value The 64-bit value to write to IBR.\r
DBR register range, a Reserved Register/Field fault may occur. The caller must\r
either guarantee that Index is valid, or the caller must set up fault handlers to\r
catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to write.\r
@param Value The 64-bit value to write to DBR.\r
counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
dependent. No parameter checking is performed on Index. If the Index value is\r
beyond the implemented PMC register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to write.\r
@param Value The 64-bit value to write to PMC.\r
performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set\r
is implementation dependent. No parameter checking is performed on Index. If the\r
Index value is beyond the implemented PMD register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to write.\r
@param Value The 64-bit value to write to PMD.\r
Reads the current value of 64-bit Global Pointer (GP).\r
\r
Reads and returns the current value of GP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of GP.\r
\r
\r
Writes the current value of GP. The 64-bit value written to the GP is returned.\r
No parameter checking is performed on Value.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to GP.\r
\r
Reads the current value of 64-bit Stack Pointer (SP).\r
\r
Reads and returns the current value of SP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of SP.\r
\r
\r
Reads and returns the control register specified by Index. The valid Index valued are defined\r
above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
\r
@param Index The index of the control register to read.\r
\r
\r
Reads and returns the application register specified by Index. The valid Index valued are defined\r
above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
\r
@param Index The index of the application register to read.\r
\r
);\r
\r
\r
+/**\r
+ Reads the current value of a Machine Specific Register (MSR).\r
+\r
+ Reads and returns the current value of the Machine Specific Register specified by Index. No\r
+ parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
+ register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
+ Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
+ only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Machine Specific Register index to read.\r
+\r
+ @return The current value of the Machine Specific Register specified by Index. \r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMsr (\r
+ IN UINT8 Index \r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of a Machine Specific Register (MSR).\r
+\r
+ Writes Value to the Machine Specific Register specified by Index. Value is returned. No\r
+ parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
+ register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
+ Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
+ only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Machine Specific Register index to write.\r
+ @param Value The 64-bit value to write to the Machine Specific Register.\r
+\r
+ @return The 64-bit value to write to the Machine Specific Register. \r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteMsr (\r
+ IN UINT8 Index, \r
+ IN UINT64 Value \r
+ );\r
+\r
+\r
/**\r
Determines if the CPU is currently executing in virtual, physical, or mixed mode.\r
\r
If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
and -1 is returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@retval 1 The CPU is in virtual mode.\r
@retval 0 The CPU is in physical mode.\r
argument return value may be returned or undefined result may occur during the\r
execution of the procedure. If the PalEntryPoint does not point to a valid\r
PAL entry point then the system behavior is undefined. This function is only\r
- available on IPF.\r
+ available on Itanium processors.\r
\r
@param PalEntryPoint The PAL procedure calls entry point.\r
@param Index The PAL procedure Index number.\r
IN UINT64 Arg3,\r
IN UINT64 Arg4\r
);\r
+#endif\r
\r
-\r
-#elif defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
/// IA32 and x64 Specific Functions\r
/// Byte packed structure for 16-bit Real Mode EFLAGS\r
///\r
typedef union {\r
struct {\r
- UINT32 CF:1; /// Carry Flag\r
- UINT32 Reserved_0:1; /// Reserved\r
- UINT32 PF:1; /// Parity Flag\r
- UINT32 Reserved_1:1; /// Reserved\r
- UINT32 AF:1; /// Auxiliary Carry Flag\r
- UINT32 Reserved_2:1; /// Reserved\r
- UINT32 ZF:1; /// Zero Flag\r
- UINT32 SF:1; /// Sign Flag\r
- UINT32 TF:1; /// Trap Flag\r
- UINT32 IF:1; /// Interrupt Enable Flag\r
- UINT32 DF:1; /// Direction Flag\r
- UINT32 OF:1; /// Overflow Flag\r
- UINT32 IOPL:2; /// I/O Privilege Level\r
- UINT32 NT:1; /// Nested Task\r
- UINT32 Reserved_3:1; /// Reserved\r
+ UINT32 CF:1; ///< Carry Flag\r
+ UINT32 Reserved_0:1; ///< Reserved\r
+ UINT32 PF:1; ///< Parity Flag\r
+ UINT32 Reserved_1:1; ///< Reserved\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag\r
+ UINT32 Reserved_2:1; ///< Reserved\r
+ UINT32 ZF:1; ///< Zero Flag\r
+ UINT32 SF:1; ///< Sign Flag\r
+ UINT32 TF:1; ///< Trap Flag\r
+ UINT32 IF:1; ///< Interrupt Enable Flag\r
+ UINT32 DF:1; ///< Direction Flag\r
+ UINT32 OF:1; ///< Overflow Flag\r
+ UINT32 IOPL:2; ///< I/O Privilege Level\r
+ UINT32 NT:1; ///< Nested Task\r
+ UINT32 Reserved_3:1; ///< Reserved\r
} Bits;\r
UINT16 Uint16;\r
} IA32_FLAGS16;\r
///\r
typedef union {\r
struct {\r
- UINT32 CF:1; /// Carry Flag\r
- UINT32 Reserved_0:1; /// Reserved\r
- UINT32 PF:1; /// Parity Flag\r
- UINT32 Reserved_1:1; /// Reserved\r
- UINT32 AF:1; /// Auxiliary Carry Flag\r
- UINT32 Reserved_2:1; /// Reserved\r
- UINT32 ZF:1; /// Zero Flag\r
- UINT32 SF:1; /// Sign Flag\r
- UINT32 TF:1; /// Trap Flag\r
- UINT32 IF:1; /// Interrupt Enable Flag\r
- UINT32 DF:1; /// Direction Flag\r
- UINT32 OF:1; /// Overflow Flag\r
- UINT32 IOPL:2; /// I/O Privilege Level\r
- UINT32 NT:1; /// Nested Task\r
- UINT32 Reserved_3:1; /// Reserved\r
- UINT32 RF:1; /// Resume Flag\r
- UINT32 VM:1; /// Virtual 8086 Mode\r
- UINT32 AC:1; /// Alignment Check\r
- UINT32 VIF:1; /// Virtual Interrupt Flag\r
- UINT32 VIP:1; /// Virtual Interrupt Pending\r
- UINT32 ID:1; /// ID Flag\r
- UINT32 Reserved_4:10; /// Reserved\r
+ UINT32 CF:1; ///< Carry Flag\r
+ UINT32 Reserved_0:1; ///< Reserved\r
+ UINT32 PF:1; ///< Parity Flag\r
+ UINT32 Reserved_1:1; ///< Reserved\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag\r
+ UINT32 Reserved_2:1; ///< Reserved\r
+ UINT32 ZF:1; ///< Zero Flag\r
+ UINT32 SF:1; ///< Sign Flag\r
+ UINT32 TF:1; ///< Trap Flag\r
+ UINT32 IF:1; ///< Interrupt Enable Flag\r
+ UINT32 DF:1; ///< Direction Flag\r
+ UINT32 OF:1; ///< Overflow Flag\r
+ UINT32 IOPL:2; ///< I/O Privilege Level\r
+ UINT32 NT:1; ///< Nested Task\r
+ UINT32 Reserved_3:1; ///< Reserved\r
+ UINT32 RF:1; ///< Resume Flag\r
+ UINT32 VM:1; ///< Virtual 8086 Mode\r
+ UINT32 AC:1; ///< Alignment Check\r
+ UINT32 VIF:1; ///< Virtual Interrupt Flag\r
+ UINT32 VIP:1; ///< Virtual Interrupt Pending\r
+ UINT32 ID:1; ///< ID Flag\r
+ UINT32 Reserved_4:10; ///< Reserved\r
} Bits;\r
UINTN UintN;\r
} IA32_EFLAGS32;\r
///\r
typedef union {\r
struct {\r
- UINT32 PE:1; /// Protection Enable\r
- UINT32 MP:1; /// Monitor Coprocessor\r
- UINT32 EM:1; /// Emulation\r
- UINT32 TS:1; /// Task Switched\r
- UINT32 ET:1; /// Extension Type\r
- UINT32 NE:1; /// Numeric Error\r
- UINT32 Reserved_0:10; /// Reserved\r
- UINT32 WP:1; /// Write Protect\r
- UINT32 Reserved_1:1; /// Reserved\r
- UINT32 AM:1; /// Alignment Mask\r
- UINT32 Reserved_2:10; /// Reserved\r
- UINT32 NW:1; /// Mot Write-through\r
- UINT32 CD:1; /// Cache Disable\r
- UINT32 PG:1; /// Paging\r
+ UINT32 PE:1; ///< Protection Enable\r
+ UINT32 MP:1; ///< Monitor Coprocessor\r
+ UINT32 EM:1; ///< Emulation\r
+ UINT32 TS:1; ///< Task Switched\r
+ UINT32 ET:1; ///< Extension Type\r
+ UINT32 NE:1; ///< Numeric Error\r
+ UINT32 Reserved_0:10; ///< Reserved\r
+ UINT32 WP:1; ///< Write Protect\r
+ UINT32 Reserved_1:1; ///< Reserved\r
+ UINT32 AM:1; ///< Alignment Mask\r
+ UINT32 Reserved_2:10; ///< Reserved\r
+ UINT32 NW:1; ///< Mot Write-through\r
+ UINT32 CD:1; ///< Cache Disable\r
+ UINT32 PG:1; ///< Paging\r
} Bits;\r
UINTN UintN;\r
} IA32_CR0;\r
///\r
typedef union {\r
struct {\r
- UINT32 VME:1; /// Virtual-8086 Mode Extensions\r
- UINT32 PVI:1; /// Protected-Mode Virtual Interrupts\r
- UINT32 TSD:1; /// Time Stamp Disable\r
- UINT32 DE:1; /// Debugging Extensions\r
- UINT32 PSE:1; /// Page Size Extensions\r
- UINT32 PAE:1; /// Physical Address Extension\r
- UINT32 MCE:1; /// Machine Check Enable\r
- UINT32 PGE:1; /// Page Global Enable\r
- UINT32 PCE:1; /// Performance Monitoring Counter\r
- /// Enable\r
- UINT32 OSFXSR:1; /// Operating System Support for\r
- /// FXSAVE and FXRSTOR instructions\r
- UINT32 OSXMMEXCPT:1; /// Operating System Support for\r
- /// Unmasked SIMD Floating Point\r
- /// Exceptions\r
- UINT32 Reserved_0:2; /// Reserved\r
- UINT32 VMXE:1; /// VMX Enable\r
- UINT32 Reserved_1:18; /// Reseved\r
+ UINT32 VME:1; ///< Virtual-8086 Mode Extensions\r
+ UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts\r
+ UINT32 TSD:1; ///< Time Stamp Disable\r
+ UINT32 DE:1; ///< Debugging Extensions\r
+ UINT32 PSE:1; ///< Page Size Extensions\r
+ UINT32 PAE:1; ///< Physical Address Extension\r
+ UINT32 MCE:1; ///< Machine Check Enable\r
+ UINT32 PGE:1; ///< Page Global Enable\r
+ UINT32 PCE:1; ///< Performance Monitoring Counter\r
+ ///< Enable\r
+ UINT32 OSFXSR:1; ///< Operating System Support for\r
+ ///< FXSAVE and FXRSTOR instructions\r
+ UINT32 OSXMMEXCPT:1; ///< Operating System Support for\r
+ ///< Unmasked SIMD Floating Point\r
+ ///< Exceptions\r
+ UINT32 Reserved_0:2; ///< Reserved\r
+ UINT32 VMXE:1; ///< VMX Enable\r
+ UINT32 Reserved_1:18; ///< Reserved\r
} Bits;\r
UINTN UintN;\r
} IA32_CR4;\r
#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E\r
#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F\r
\r
+\r
+#if defined (MDE_CPU_IA32)\r
///\r
-/// Byte packed structure for an Interrupt Gate Descriptor\r
+/// Byte packed structure for an IA-32 Interrupt Gate Descriptor\r
///\r
-#if defined (MDE_CPU_IA32)\r
-\r
typedef union {\r
struct {\r
- UINT32 OffsetLow:16; // Offset bits 15..0\r
- UINT32 Selector:16; // Selector\r
- UINT32 Reserved_0:8; // Reserved\r
- UINT32 GateType:8; // Gate Type. See #defines above\r
- UINT32 OffsetHigh:16; // Offset bits 31..16\r
+ UINT32 OffsetLow:16; ///< Offset bits 15..0\r
+ UINT32 Selector:16; ///< Selector\r
+ UINT32 Reserved_0:8; ///< Reserved\r
+ UINT32 GateType:8; ///< Gate Type. See #defines above\r
+ UINT32 OffsetHigh:16; ///< Offset bits 31..16\r
} Bits;\r
UINT64 Uint64;\r
} IA32_IDT_GATE_DESCRIPTOR;\r
#endif\r
\r
#if defined (MDE_CPU_X64)\r
-\r
+///\r
+/// Byte packed structure for an x64 Interrupt Gate Descriptor\r
+///\r
typedef union {\r
struct {\r
- UINT32 OffsetLow:16; // Offset bits 15..0\r
- UINT32 Selector:16; // Selector\r
- UINT32 Reserved_0:8; // Reserved\r
- UINT32 GateType:8; // Gate Type. See #defines above\r
- UINT32 OffsetHigh:16; // Offset bits 31..16\r
- UINT32 OffsetUpper:32; // Offset bits 63..32\r
- UINT32 Reserved_1:32; // Reserved\r
+ UINT32 OffsetLow:16; ///< Offset bits 15..0\r
+ UINT32 Selector:16; ///< Selector\r
+ UINT32 Reserved_0:8; ///< Reserved\r
+ UINT32 GateType:8; ///< Gate Type. See #defines above\r
+ UINT32 OffsetHigh:16; ///< Offset bits 31..16\r
+ UINT32 OffsetUpper:32; ///< Offset bits 63..32\r
+ UINT32 Reserved_1:32; ///< Reserved\r
} Bits;\r
- UINT64 Uint64;\r
- UINT64 Uint64_1;\r
+ struct {\r
+ UINT64 Uint64;\r
+ UINT64 Uint64_1;\r
+ } Uint128; \r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
#endif\r
@param Edx Pointer to the 32-bit EDX value returned by the CPUID\r
instruction. This is an optional parameter that may be NULL.\r
\r
- @return Index\r
+ @return Index.\r
\r
**/\r
UINT32\r
instruction. This is an optional parameter that may be\r
NULL.\r
\r
- @return Index\r
+ @return Index.\r
\r
**/\r
UINT32\r
/**\r
Writes a bit field to an MSR.\r
\r
- Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r
+ Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r
field is specified by the StartBit and the EndBit. All other bits in the\r
destination MSR are preserved. The lower 32-bits of the MSR written is\r
returned. The caller must either guarantee that Index and the data written \r
in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r
then the actual minimum stack size is ExtraStackSize plus the maximum number\r
of bytes that need to be passed to the 16-bit real mode code.\r
-\r
+ \r
If RealModeBufferSize is NULL, then ASSERT().\r
If ExtraStackSize is NULL, then ASSERT().\r
\r
Prepares all structures a code required to use AsmThunk16().\r
\r
Prepares all structures and code required to use AsmThunk16().\r
+ \r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
\r
If ThunkContext is NULL, then ASSERT().\r
\r
If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in \r
ThunkAttributes, then ASSERT().\r
\r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
+\r
@param ThunkContext A pointer to the context structure that describes the\r
16-bit real mode code to call.\r
\r
real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\r
once and AsmThunk16() can be called for each 16-bit real mode thunk.\r
\r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
+\r
See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\r
\r
@param ThunkContext A pointer to the context structure that describes the\r
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