+ @retval TRUE CPU interrupts were enabled on entry to this call.\r
+ @retval FALSE CPU interrupts were disabled on entry to this call.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SaveAndDisableInterrupts (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Enables CPU interrupts for the smallest window required to capture any\r
+ pending interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableDisableInterrupts (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Retrieves the current CPU interrupt state.\r
+\r
+ Returns TRUE is interrupts are currently enabled. Otherwise\r
+ returns FALSE.\r
+\r
+ @retval TRUE CPU interrupts are enabled.\r
+ @retval FALSE CPU interrupts are disabled.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+GetInterruptState (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Set the current CPU interrupt state.\r
+\r
+ Sets the current CPU interrupt state to the state specified by\r
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If\r
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is\r
+ returned.\r
+\r
+ @param InterruptState TRUE if interrupts should enabled. FALSE if\r
+ interrupts should be disabled.\r
+\r
+ @return InterruptState\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SetInterruptState (\r
+ IN BOOLEAN InterruptState\r
+ );\r
+\r
+\r
+/**\r
+ Requests CPU to pause for a short period of time.\r
+\r
+ Requests CPU to pause for a short period of time. Typically used in MP\r
+ systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the\r
+ new stack specified by NewStack and passing in the parameters specified\r
+ by Context1 and Context2. Context1 and Context2 are optional and may\r
+ be NULL. The function EntryPoint must never return. This function\r
+ supports a variable number of arguments following the NewStack parameter.\r
+ These additional arguments are ignored on IA-32, x64, and EBC architectures.\r
+ Itanium processors expect one additional parameter of type VOID * that specifies\r
+ the new backing store pointer.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param ... This variable argument list is ignored for IA-32, x64, and EBC architectures. \r
+ For Itanium processors, this variable argument list is expected to contain \r
+ a single parameter of type VOID * that specifies the new backing \r
+ store pointer.\r
+\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SwitchStack (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack,\r
+ ...\r
+ );\r
+\r
+\r
+/**\r
+ Generates a breakpoint on the CPU.\r
+\r
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+ that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Executes an infinite loop.\r
+\r
+ Forces the CPU to execute an infinite loop. A debugger may be used to skip\r
+ past the loop and the code that follows the loop must execute properly. This\r
+ implies that the infinite loop must not cause the code that follow it to be\r
+ optimized away.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuDeadLoop (\r
+ VOID\r
+ );\r
+ \r
+#if defined (MDE_CPU_IPF)\r
+\r
+/**\r
+ Flush a range of cache lines in the cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Flushes the cache lines specified by Address and Length. If Address is not aligned \r
+ on a cache line boundary, then entire cache line containing Address is flushed. \r
+ If Address + Length is not aligned on a cache line boundary, then the entire cache \r
+ line containing Address + Length - 1 is flushed. This function may choose to flush \r
+ the entire cache if that is more efficient than flushing the specified range. If \r
+ Length is 0, the no cache lines are flushed. Address is returned. \r
+ This function is only available on Itanium processors.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction lines to invalidate. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing mode,\r
+ then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+AsmFlushCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r
+\r
+/**\r
+ Executes a FC instruction\r
+ Executes a FC instruction on the cache line specified by Address.\r
+ The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
+\r
+ @param Address The Address of cache line to be flushed.\r
+\r
+ @return The address of FC instruction executed.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmFc (\r
+ IN UINT64 Address\r
+ );\r
+\r
+\r
+/**\r
+ Executes a FC.I instruction.\r
+ Executes a FC.I instruction on the cache line specified by Address.\r
+ The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
+\r
+ @param Address The Address of cache line to be flushed.\r
+\r
+ @return The address of FC.I instruction executed.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmFci (\r
+ IN UINT64 Address\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of a Processor Identifier Register (CPUID).\r
+ \r
+ Reads and returns the current value of Processor Identifier Register specified by Index. \r
+ The Index of largest implemented CPUID (One less than the number of implemented CPUID\r
+ registers) is determined by CPUID [3] bits {7:0}.\r
+ No parameter checking is performed on Index. If the Index value is beyond the\r
+ implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
+ must either guarantee that Index is valid, or the caller must set up fault handlers to\r
+ catch the faults. This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Processor Identifier Register index to read.\r
+\r
+ @return The current value of Processor Identifier Register specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadCpuid (\r
+ IN UINT8 Index\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Processor Status Register (PSR).\r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of PSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPsr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Processor Status Register (PSR).\r
+\r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to PSR.\r
+\r
+ @return The 64-bit value written to the PSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWritePsr (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #0 (KR0).\r
+ \r
+ Reads and returns the current value of KR0. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr0 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #1 (KR1).\r
+\r
+ Reads and returns the current value of KR1. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr1 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #2 (KR2).\r
+\r
+ Reads and returns the current value of KR2. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr2 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #3 (KR3).\r
+\r
+ Reads and returns the current value of KR3. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr3 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #4 (KR4).\r
+\r
+ Reads and returns the current value of KR4. \r
+ This function is only available on Itanium processors.\r
+ \r
+ @return The current value of KR4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr4 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #5 (KR5).\r
+\r
+ Reads and returns the current value of KR5. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr5 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #6 (KR6).\r
+\r
+ Reads and returns the current value of KR6. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr6 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit Kernel Register #7 (KR7).\r
+\r
+ Reads and returns the current value of KR7. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of KR7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadKr7 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #0 (KR0).\r
+ \r
+ Writes the current value of KR0. The 64-bit value written to \r
+ the KR0 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR0.\r
+\r
+ @return The 64-bit value written to the KR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr0 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #1 (KR1).\r
+\r
+ Writes the current value of KR1. The 64-bit value written to \r
+ the KR1 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR1.\r
+\r
+ @return The 64-bit value written to the KR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr1 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #2 (KR2).\r
+\r
+ Writes the current value of KR2. The 64-bit value written to \r
+ the KR2 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR2.\r
+\r
+ @return The 64-bit value written to the KR2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr2 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #3 (KR3).\r
+\r
+ Writes the current value of KR3. The 64-bit value written to \r
+ the KR3 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR3.\r
+\r
+ @return The 64-bit value written to the KR3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr3 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #4 (KR4).\r
+\r
+ Writes the current value of KR4. The 64-bit value written to \r
+ the KR4 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR4.\r
+\r
+ @return The 64-bit value written to the KR4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr4 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #5 (KR5).\r
+\r
+ Writes the current value of KR5. The 64-bit value written to \r
+ the KR5 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR5.\r
+\r
+ @return The 64-bit value written to the KR5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr5 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #6 (KR6).\r
+\r
+ Writes the current value of KR6. The 64-bit value written to \r
+ the KR6 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR6.\r
+\r
+ @return The 64-bit value written to the KR6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr6 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Write the current value of 64-bit Kernel Register #7 (KR7).\r
+\r
+ Writes the current value of KR7. The 64-bit value written to \r
+ the KR7 is returned. This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to KR7.\r
+\r
+ @return The 64-bit value written to the KR7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteKr7 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interval Timer Counter Register (ITC).\r
+ \r
+ Reads and returns the current value of ITC.\r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of ITC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadItc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interval Timer Vector Register (ITV).\r
+ \r
+ Reads and returns the current value of ITV. \r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of ITV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadItv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interval Timer Match Register (ITM).\r
+ \r
+ Reads and returns the current value of ITM.\r
+ This function is only available on Itanium processors.\r
+\r
+ @return The current value of ITM.\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadItm (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
+ \r
+ Writes the current value of ITC. The 64-bit value written to the ITC is returned. \r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to ITC.\r
+\r
+ @return The 64-bit value written to the ITC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteItc (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
+ \r
+ Writes the current value of ITM. The 64-bit value written to the ITM is returned. \r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to ITM.\r
+\r
+ @return The 64-bit value written to the ITM.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteItm (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Interval Timer Vector Register (ITV).\r
+ \r
+ Writes the current value of ITV. The 64-bit value written to the ITV is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to ITV.\r
+\r
+ @return The 64-bit value written to the ITV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteItv (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Default Control Register (DCR).\r
+ \r
+ Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
+\r
+ @return The current value of DCR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadDcr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Interruption Vector Address Register (IVA).\r
+ \r
+ Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
+\r
+ @return The current value of IVA.\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIva (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Page Table Address Register (PTA).\r
+ \r
+ Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
+\r
+ @return The current value of PTA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPta (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Default Control Register (DCR).\r
+ \r
+ Writes the current value of DCR. The 64-bit value written to the DCR is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to DCR.\r
+\r
+ @return The 64-bit value written to the DCR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteDcr (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Interruption Vector Address Register (IVA).\r
+ \r
+ Writes the current value of IVA. The 64-bit value written to the IVA is returned. \r
+ The size of vector table is 32 K bytes and is 32 K bytes aligned\r
+ the low 15 bits of Value is ignored when written.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to IVA.\r
+\r
+ @return The 64-bit value written to the IVA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteIva (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Page Table Address Register (PTA).\r
+ \r
+ Writes the current value of PTA. The 64-bit value written to the PTA is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to PTA.\r
+\r
+ @return The 64-bit value written to the PTA.\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWritePta (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Local Interrupt ID Register (LID).\r
+ \r
+ Reads and returns the current value of LID. This function is only available on Itanium processors.\r
+\r
+ @return The current value of LID.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadLid (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of External Interrupt Vector Register (IVR).\r
+ \r
+ Reads and returns the current value of IVR. This function is only available on Itanium processors. \r
+\r
+ @return The current value of IVR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIvr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Task Priority Register (TPR).\r
+ \r
+ Reads and returns the current value of TPR. This function is only available on Itanium processors. \r
+\r
+ @return The current value of TPR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadTpr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of External Interrupt Request Register #0 (IRR0).\r
+ \r
+ Reads and returns the current value of IRR0. This function is only available on Itanium processors. \r
+\r
+ @return The current value of IRR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIrr0 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of External Interrupt Request Register #1 (IRR1).\r
+ \r
+ Reads and returns the current value of IRR1. This function is only available on Itanium processors. \r
+\r
+ @return The current value of IRR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIrr1 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of External Interrupt Request Register #2 (IRR2).\r
+ \r
+ Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
+\r
+ @return The current value of IRR2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIrr2 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of External Interrupt Request Register #3 (IRR3).\r
+ \r
+ Reads and returns the current value of IRR3. This function is only available on Itanium processors. \r
+\r
+ @return The current value of IRR3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIrr3 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Performance Monitor Vector Register (PMV).\r
+ \r
+ Reads and returns the current value of PMV. This function is only available on Itanium processors. \r
+\r
+ @return The current value of PMV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPmv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
+ \r
+ Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
+\r
+ @return The current value of CMCV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadCmcv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Local Redirection Register #0 (LRR0).\r
+ \r
+ Reads and returns the current value of LRR0. This function is only available on Itanium processors. \r
+\r
+ @return The current value of LRR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadLrr0 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Local Redirection Register #1 (LRR1).\r
+ \r
+ Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
+\r
+ @return The current value of LRR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadLrr1 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Page Local Interrupt ID Register (LID).\r
+ \r
+ Writes the current value of LID. The 64-bit value written to the LID is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to LID.\r
+\r
+ @return The 64-bit value written to the LID.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteLid (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Task Priority Register (TPR).\r
+ \r
+ Writes the current value of TPR. The 64-bit value written to the TPR is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding to\r
+ reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to TPR.\r
+\r
+ @return The 64-bit value written to the TPR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteTpr (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Performs a write operation on End OF External Interrupt Register (EOI).\r
+ \r
+ Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteEoi (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Performance Monitor Vector Register (PMV).\r
+ \r
+ Writes the current value of PMV. The 64-bit value written to the PMV is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding\r
+ to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to PMV.\r
+\r
+ @return The 64-bit value written to the PMV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWritePmv (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).\r
+ \r
+ Writes the current value of CMCV. The 64-bit value written to the CMCV is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding\r
+ to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to CMCV.\r
+\r
+ @return The 64-bit value written to the CMCV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteCmcv (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Local Redirection Register #0 (LRR0).\r
+ \r
+ Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding\r
+ to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to LRR0.\r
+\r
+ @return The 64-bit value written to the LRR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteLrr0 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Local Redirection Register #1 (LRR1).\r
+ \r
+ Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned. \r
+ No parameter checking is performed on Value. All bits of Value corresponding\r
+ to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Value is valid, or the caller must\r
+ set up fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Value The 64-bit value to write to LRR1.\r
+\r
+ @return The 64-bit value written to the LRR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteLrr1 (\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Instruction Breakpoint Register (IBR).\r
+ \r
+ The Instruction Breakpoint Registers are used in pairs. The even numbered\r
+ registers contain breakpoint addresses, and the odd numbered registers contain\r
+ breakpoint mask conditions. At least 4 instruction registers pairs are implemented\r
+ on all processor models. Implemented registers are contiguous starting with\r
+ register 0. No parameter checking is performed on Index, and if the Index value\r
+ is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
+ occur. The caller must either guarantee that Index is valid, or the caller must\r
+ set up fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Instruction Breakpoint Register index to read.\r
+\r
+ @return The current value of Instruction Breakpoint Register specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadIbr (\r
+ IN UINT8 Index\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Data Breakpoint Register (DBR).\r
+\r
+ The Data Breakpoint Registers are used in pairs. The even numbered registers\r
+ contain breakpoint addresses, and odd numbered registers contain breakpoint\r
+ mask conditions. At least 4 data registers pairs are implemented on all processor\r
+ models. Implemented registers are contiguous starting with register 0.\r
+ No parameter checking is performed on Index. If the Index value is beyond\r
+ the implemented DBR register range, a Reserved Register/Field fault may occur.\r
+ The caller must either guarantee that Index is valid, or the caller must set up\r
+ fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Data Breakpoint Register index to read.\r
+\r
+ @return The current value of Data Breakpoint Register specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadDbr (\r
+ IN UINT8 Index\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Performance Monitor Configuration Register (PMC).\r
+\r
+ All processor implementations provide at least 4 performance counters\r
+ (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter overflow\r
+ status registers (PMC [0]... PMC [3]). Processor implementations may provide\r
+ additional implementation-dependent PMC and PMD to increase the number of\r
+ 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
+ register set is implementation dependent. No parameter checking is performed\r
+ on Index. If the Index value is beyond the implemented PMC register range,\r
+ zero value will be returned.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Performance Monitor Configuration Register index to read.\r
+\r
+ @return The current value of Performance Monitor Configuration Register\r
+ specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPmc (\r
+ IN UINT8 Index\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of Performance Monitor Data Register (PMD).\r
+\r
+ All processor implementations provide at least 4 performance counters\r
+ (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter\r
+ overflow status registers (PMC [0]... PMC [3]). Processor implementations may\r
+ provide additional implementation-dependent PMC and PMD to increase the number\r
+ of 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
+ register set is implementation dependent. No parameter checking is performed\r
+ on Index. If the Index value is beyond the implemented PMD register range,\r
+ zero value will be returned.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Performance Monitor Data Register index to read.\r
+\r
+ @return The current value of Performance Monitor Data Register specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPmd (\r
+ IN UINT8 Index\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Instruction Breakpoint Register (IBR).\r
+\r
+ Writes current value of Instruction Breakpoint Register specified by Index.\r
+ The Instruction Breakpoint Registers are used in pairs. The even numbered\r
+ registers contain breakpoint addresses, and odd numbered registers contain\r
+ breakpoint mask conditions. At least 4 instruction registers pairs are implemented\r
+ on all processor models. Implemented registers are contiguous starting with\r
+ register 0. No parameter checking is performed on Index. If the Index value\r
+ is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
+ occur. The caller must either guarantee that Index is valid, or the caller must\r
+ set up fault handlers to catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Instruction Breakpoint Register index to write.\r
+ @param Value The 64-bit value to write to IBR.\r
+\r
+ @return The 64-bit value written to the IBR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteIbr (\r
+ IN UINT8 Index,\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Data Breakpoint Register (DBR).\r
+\r
+ Writes current value of Data Breakpoint Register specified by Index.\r
+ The Data Breakpoint Registers are used in pairs. The even numbered registers\r
+ contain breakpoint addresses, and odd numbered registers contain breakpoint\r
+ mask conditions. At least 4 data registers pairs are implemented on all processor\r
+ models. Implemented registers are contiguous starting with register 0. No parameter\r
+ checking is performed on Index. If the Index value is beyond the implemented\r
+ DBR register range, a Reserved Register/Field fault may occur. The caller must\r
+ either guarantee that Index is valid, or the caller must set up fault handlers to\r
+ catch the faults.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Data Breakpoint Register index to write.\r
+ @param Value The 64-bit value to write to DBR.\r
+\r
+ @return The 64-bit value written to the DBR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteDbr (\r
+ IN UINT8 Index,\r
+ IN UINT64 Value\r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit Performance Monitor Configuration Register (PMC).\r
+\r
+ Writes current value of Performance Monitor Configuration Register specified by Index.\r
+ All processor implementations provide at least 4 performance counters\r
+ (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter overflow status\r
+ registers (PMC [0]... PMC [3]). Processor implementations may provide additional\r
+ implementation-dependent PMC and PMD to increase the number of 'generic' performance\r
+ counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
+ dependent. No parameter checking is performed on Index. If the Index value is\r
+ beyond the implemented PMC register range, the write is ignored.\r
+ This function is only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Performance Monitor Configuration Register index to write.\r
+ @param Value The 64-bit value to write to PMC.\r