/** @file\r
Provides string functions, linked list functions, math functions, synchronization\r
- functions, and CPU architecture specific functions.\r
+ functions, and CPU architecture-specific functions.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
+Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#ifndef __BASE_LIB__\r
#define __BASE_LIB__\r
\r
-///\r
-/// Definitions for SPIN_LOCK\r
-///\r
-typedef volatile UINTN SPIN_LOCK;\r
-\r
//\r
-// Definitions for architecture specific types\r
+// Definitions for architecture-specific types\r
//\r
#if defined (MDE_CPU_IA32)\r
///\r
-/// IA32 context buffer used by SetJump() and LongJump()\r
+/// IA-32 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT32 Ebx;\r
\r
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
\r
-#elif defined (MDE_CPU_IPF)\r
+#endif // defined (MDE_CPU_IA32)\r
+\r
+#if defined (MDE_CPU_IPF)\r
\r
///\r
-/// IPF context buffer used by SetJump() and LongJump()\r
+/// Itanium architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 F2[2];\r
\r
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 0x10\r
\r
-#elif defined (MDE_CPU_X64)\r
+#endif // defined (MDE_CPU_IPF)\r
+\r
+#if defined (MDE_CPU_X64)\r
///\r
-/// X64 context buffer used by SetJump() and LongJump()\r
+/// x64 architecture context buffer used by SetJump() and LongJump()\r
///\r
typedef struct {\r
UINT64 Rbx;\r
\r
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
\r
-#elif defined (MDE_CPU_EBC)\r
+#endif // defined (MDE_CPU_X64)\r
+\r
+#if defined (MDE_CPU_EBC)\r
///\r
/// EBC context buffer used by SetJump() and LongJump()\r
///\r
\r
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
\r
-#else\r
-#error Unknown Processor Type\r
-#endif\r
+#endif // defined (MDE_CPU_EBC)\r
\r
//\r
// String Services\r
@param Destination Pointer to a Null-terminated Unicode string.\r
@param Source Pointer to a Null-terminated Unicode string.\r
\r
- @return Destiantion\r
+ @return Destination.\r
\r
**/\r
CHAR16 *\r
If Length > 0 and Destination is NULL, then ASSERT().\r
If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().\r
If Length > 0 and Source is NULL, then ASSERT().\r
- If Length > 0 and Source is not aligned on a 16-bit bounadry, then ASSERT().\r
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
- PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated Unicode string.\r
@param Source Pointer to a Null-terminated Unicode string.\r
@param Length Maximum number of Unicode characters to copy.\r
\r
- @return Destination\r
+ @return Destination.\r
\r
**/\r
CHAR16 *\r
subtracted from the first mismatched Unicode character in FirstString.\r
\r
If Length > 0 and FirstString is NULL, then ASSERT().\r
- If Length > 0 and FirstString is not aligned on a 16-bit bounadary, then ASSERT().\r
+ If Length > 0 and FirstString is not aligned on a 16-bit boundary, then ASSERT().\r
If Length > 0 and SecondString is NULL, then ASSERT().\r
- If Length > 0 and SecondString is not aligned on a 16-bit bounadary, then ASSERT().\r
- If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more\r
- than PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
- If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more\r
- than PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
+ If Length > 0 and SecondString is not aligned on a 16-bit boundary, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than\r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
\r
@param FirstString Pointer to a Null-terminated Unicode string.\r
@param SecondString Pointer to a Null-terminated Unicode string.\r
results are undefined.\r
\r
If Destination is NULL, then ASSERT().\r
- If Destination is not aligned on a 16-bit bounadary, then ASSERT().\r
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().\r
If Source is NULL, then ASSERT().\r
- If Source is not aligned on a 16-bit bounadary, then ASSERT().\r
+ If Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Destination contains more\r
than PcdMaximumUnicodeStringLength Unicode characters not including the\r
@param Destination Pointer to a Null-terminated Unicode string.\r
@param Source Pointer to a Null-terminated Unicode string.\r
\r
- @return Destination\r
+ @return Destination.\r
\r
**/\r
CHAR16 *\r
If Length > 0 and Source is NULL, then ASSERT().\r
If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Destination contains more\r
- than PcdMaximumUnicodeStringLength Unicode characters not including the\r
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the\r
Null-terminator, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
- PcdMaximumUnicodeStringLength Unicode characters not including the\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
Null-terminator, then ASSERT().\r
If PcdMaximumUnicodeStringLength is not zero, and concatenating Destination\r
- and Source results in a Unicode string with more than\r
- PcdMaximumUnicodeStringLength Unicode characters not including the\r
- Null-terminator, then ASSERT().\r
+ and Source results in a Unicode string with more than PcdMaximumUnicodeStringLength\r
+ Unicode characters, not including the Null-terminator, then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated Unicode string.\r
@param Source Pointer to a Null-terminated Unicode string.\r
@param Length Maximum number of Unicode characters to concatenate from\r
Source.\r
\r
- @return Destination\r
+ @return Destination.\r
\r
**/\r
CHAR16 *\r
);\r
\r
/**\r
- Returns the first occurance of a Null-terminated Unicode sub-string\r
+ Returns the first occurrence of a Null-terminated Unicode sub-string\r
in a Null-terminated Unicode string.\r
\r
This function scans the contents of the Null-terminated Unicode string\r
IN CONST CHAR16 *String\r
);\r
\r
-/**\r
- Convert a nibble in the low 4 bits of a byte to a Unicode hexadecimal character.\r
-\r
- This function converts a nibble in the low 4 bits of a byte to a Unicode hexadecimal \r
- character For example, the nibble 0x01 and 0x0A will converted to L'1' and L'A' \r
- respectively.\r
-\r
- The upper nibble in the input byte will be masked off.\r
-\r
- @param Nibble The nibble which is in the low 4 bits of the input byte.\r
-\r
- @retval CHAR16 The Unicode hexadecimal character.\r
- \r
-**/\r
-CHAR16\r
-EFIAPI\r
-NibbleToHexChar (\r
- IN UINT8 Nibble\r
- );\r
-\r
-/** \r
- Convert binary buffer to a Unicode String in a specified sequence. \r
-\r
- This function converts bytes in the memory block pointed by Buffer to a Unicode String Str. \r
- Each byte will be represented by two Unicode characters. For example, byte 0xA1 will \r
- be converted into two Unicode character L'A' and L'1'. In the output String, the Unicode Character \r
- for the Most Significant Nibble will be put before the Unicode Character for the Least Significant\r
- Nibble. The output string for the buffer containing a single byte 0xA1 will be L"A1". \r
- For a buffer with multiple bytes, the Unicode character produced by the first byte will be put into the \r
- the last character in the output string. The one next to first byte will be put into the\r
- character before the last character. This rules applies to the rest of the bytes. The Unicode\r
- character by the last byte will be put into the first character in the output string. For example,\r
- the input buffer for a 64-bits unsigned integrer 0x12345678abcdef1234 will be converted to\r
- a Unicode string equal to L"12345678abcdef1234".\r
-\r
- @param String On input, String is pointed to the buffer allocated for the convertion.\r
- @param StringLen The Length of String buffer to hold the output String. The length must include the tailing '\0' character.\r
- The StringLen required to convert a N bytes Buffer will be a least equal to or greater \r
- than 2*N + 1.\r
- @param Buffer The pointer to a input buffer.\r
- @param BufferSizeInBytes Lenth in bytes of the input buffer.\r
- \r
-\r
- @retval EFI_SUCCESS The convertion is successfull. All bytes in Buffer has been convert to the corresponding\r
- Unicode character and placed into the right place in String.\r
- @retval EFI_BUFFER_TOO_SMALL StringSizeInBytes is smaller than 2 * N + 1the number of bytes required to\r
- complete the convertion. \r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-BufToHexString (\r
- IN OUT CHAR16 *String,\r
- IN OUT UINTN *StringLen,\r
- IN CONST UINT8 *Buffer,\r
- IN UINTN BufferSizeInBytes\r
- );\r
-\r
-\r
-/**\r
- Convert a Unicode string consisting of hexadecimal characters to a output byte buffer.\r
-\r
- This function converts a Unicode string consisting of characters in the range of Hexadecimal\r
- character (L'0' to L'9', L'A' to L'F' and L'a' to L'f') to a output byte buffer. The function will stop\r
- at the first non-hexadecimal character or the NULL character. The convertion process can be\r
- simply viewed as the reverse operations defined by BufToHexString. Two Unicode characters will be \r
- converted into one byte. The first Unicode character represents the Most Significant Nibble and the\r
- second Unicode character represents the Least Significant Nibble in the output byte. \r
- The first pair of Unicode characters represents the last byte in the output buffer. The second pair of Unicode \r
- characters represent the the byte preceding the last byte. This rule applies to the rest pairs of bytes. \r
- The last pair represent the first byte in the output buffer. \r
-\r
- For example, a Unciode String L"12345678" will be converted into a buffer wil the following bytes \r
- (first byte is the byte in the lowest memory address): "0x78, 0x56, 0x34, 0x12".\r
-\r
- If String has N valid hexadecimal characters for conversion, the caller must make sure Buffer is at least \r
- N/2 (if N is even) or (N+1)/2 (if N if odd) bytes. \r
-\r
- @param Buffer The output buffer allocated by the caller.\r
- @param BufferSizeInBytes On input, the size in bytes of Buffer. On output, it is updated to \r
- contain the size of the Buffer which is actually used for the converstion.\r
- For Unicode string with 2*N hexadecimal characters (not including the \r
- tailing NULL character), N bytes of Buffer will be used for the output.\r
- @param String The input hexadecimal string.\r
- @param ConvertedStrLen The number of hexadecimal characters used to produce content in output\r
- buffer Buffer.\r
-\r
- @retval RETURN_BUFFER_TOO_SMALL The input BufferSizeInBytes is too small to hold the output. BufferSizeInBytes\r
- will be updated to the size required for the converstion.\r
- @retval RETURN_SUCCESS The convertion is successful or the first Unicode character from String\r
- is hexadecimal. If ConvertedStrLen is not NULL, it is updated\r
- to the number of hexadecimal character used for the converstion.\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-HexStringToBuf (\r
- OUT UINT8 *Buffer, \r
- IN OUT UINTN *BufferSizeInBytes,\r
- IN CONST CHAR16 *String,\r
- OUT UINTN *ConvertedStrLen OPTIONAL\r
- );\r
-\r
-\r
-/**\r
- Test if a Unicode character is a hexadecimal digit. If true, the input\r
- Unicode character is converted to a byte. \r
-\r
- This function tests if a Unicode character is a hexadecimal digit. If true, the input\r
- Unicode character is converted to a byte. For example, Unicode character\r
- L'A' will be converted to 0x0A. \r
-\r
- If Digit is NULL, then ASSERT.\r
-\r
- @param Digit The output hexadecimal digit.\r
-\r
- @param Char The input Unicode character.\r
-\r
- @retval TRUE Char is in the range of Hexadecimal number. Digit is updated\r
- to the byte value of the number.\r
- @retval FALSE Char is not in the range of Hexadecimal number. Digit is keep\r
- intact.\r
- \r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-IsHexDigit (\r
- OUT UINT8 *Digit,\r
- IN CHAR16 Char\r
- );\r
-\r
/**\r
Convert a Null-terminated Unicode string to a Null-terminated\r
ASCII string and returns the ASCII string.\r
@param Source Pointer to a Null-terminated Unicode string.\r
@param Destination Pointer to a Null-terminated ASCII string.\r
\r
- @return Destination\r
+ @return Destination.\r
\r
**/\r
CHAR8 *\r
If Destination is NULL, then ASSERT().\r
If Source is NULL, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated ASCII string.\r
\r
If Length > 0 and FirstString is NULL, then ASSERT().\r
If Length > 0 and SecondString is NULL, then ASSERT().\r
- If PcdMaximumAsciiStringLength is not zero and FirstString contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
- If PcdMaximumAsciiStringLength is not zero and SecondString contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ If PcdMaximumAsciiStringLength is not zero, and SecondString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
\r
@param FirstString Pointer to a Null-terminated ASCII string.\r
If Length > 0 and Destination is NULL, then ASSERT().\r
If Length > 0 and Source is NULL, then ASSERT().\r
If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than\r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and Destination contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
- PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
then ASSERT().\r
If PcdMaximumAsciiStringLength is not zero, and concatenating Destination and\r
Source results in a ASCII string with more than PcdMaximumAsciiStringLength\r
- ASCII characters not including the Null-terminator, then ASSERT().\r
+ ASCII characters, not including the Null-terminator, then ASSERT().\r
\r
@param Destination Pointer to a Null-terminated ASCII string.\r
@param Source Pointer to a Null-terminated ASCII string.\r
\r
\r
/**\r
- Returns the first occurance of a Null-terminated ASCII sub-string\r
+ Returns the first occurrence of a Null-terminated ASCII sub-string\r
in a Null-terminated ASCII string.\r
\r
This function scans the contents of the ASCII string specified by String\r
\r
@retval NULL If the SearchString does not appear in String.\r
@retval others If there is a match return the first occurrence of SearchingString.\r
- If the lenth of SearchString is zero,return String.\r
+ If the length of SearchString is zero,return String.\r
\r
**/\r
CHAR8 *\r
@param Source Pointer to a Null-terminated ASCII string.\r
@param Destination Pointer to a Null-terminated Unicode string.\r
\r
- @return Destination\r
+ @return Destination.\r
\r
**/\r
CHAR16 *\r
\r
@param Value The 8-bit value to convert to BCD. Range 0..99.\r
\r
- @return The BCD value\r
+ @return The BCD value.\r
\r
**/\r
UINT8\r
instead if calling the InitializeListHead() function to perform the\r
equivalent operation.\r
\r
- @param ListHead The head note of a list to initiailize.\r
+ @param ListHead The head note of a list to initialize.\r
\r
**/\r
#define INITIALIZE_LIST_HEAD_VARIABLE(ListHead) {&(ListHead), &(ListHead)}\r
@param FirstEntry A pointer to a node in a linked list.\r
@param SecondEntry A pointer to another node in the same linked list.\r
\r
- @return SecondEntry\r
+ @return SecondEntry.\r
\r
**/\r
LIST_ENTRY *\r
linked list containing Entry, including the Entry node, is greater than\r
or equal to PcdMaximumLinkedListLength, then ASSERT().\r
\r
- @param Entry A pointer to a node in a linked list\r
+ @param Entry A pointer to a node in a linked list.\r
\r
- @return Entry\r
+ @return Entry.\r
\r
**/\r
LIST_ENTRY *\r
@param Operand The 64-bit operand to shift left.\r
@param Count The number of bits to shift left.\r
\r
- @return Operand << Count\r
+ @return Operand << Count.\r
\r
**/\r
UINT64\r
@param Operand The 32-bit operand to rotate right.\r
@param Count The number of bits to rotate right.\r
\r
- @return Operand >>> Count\r
+ @return Operand >> Count\r
\r
**/\r
UINT32\r
\r
@param Operand The 32-bit operand to evaluate.\r
\r
- @retval 0-31 The lowest bit set in Operand was found.\r
+ @retval 0..31 The lowest bit set in Operand was found.\r
@retval -1 Operand is zero.\r
\r
**/\r
\r
@param Operand The 64-bit operand to evaluate.\r
\r
- @retval 0-63 The lowest bit set in Operand was found.\r
+ @retval 0..63 The lowest bit set in Operand was found.\r
@retval -1 Operand is zero.\r
\r
\r
\r
@param Operand The 32-bit operand to evaluate.\r
\r
- @retval 0-31 Position of the highest bit set in Operand if found.\r
+ @retval 0..31 Position of the highest bit set in Operand if found.\r
@retval -1 Operand is zero.\r
\r
**/\r
\r
@param Operand The 64-bit operand to evaluate.\r
\r
- @retval 0-63 Position of the highest bit set in Operand if found.\r
+ @retval 0..63 Position of the highest bit set in Operand if found.\r
@retval -1 Operand is zero.\r
\r
**/\r
from little endian to big endian or vice versa. The byte swapped value is\r
returned.\r
\r
- @param Value Operand A 16-bit unsigned value.\r
+ @param Value A 16-bit unsigned value.\r
\r
- @return The byte swapped Operand.\r
+ @return The byte swapped Value.\r
\r
**/\r
UINT16\r
from little endian to big endian or vice versa. The byte swapped value is\r
returned.\r
\r
- @param Value Operand A 32-bit unsigned value.\r
+ @param Value A 32-bit unsigned value.\r
\r
- @return The byte swapped Operand.\r
+ @return The byte swapped Value.\r
\r
**/\r
UINT32\r
from little endian to big endian or vice versa. The byte swapped value is\r
returned.\r
\r
- @param Value Operand A 64-bit unsigned value.\r
+ @param Value A 64-bit unsigned value.\r
\r
- @return The byte swapped Operand.\r
+ @return The byte swapped Value.\r
\r
**/\r
UINT64\r
unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
bit unsigned result is returned.\r
\r
- If the result overflows, then ASSERT().\r
-\r
@param Multiplicand A 64-bit unsigned value.\r
@param Multiplier A 32-bit unsigned value.\r
\r
unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
bit unsigned result is returned.\r
\r
- If the result overflows, then ASSERT().\r
-\r
@param Multiplicand A 64-bit unsigned value.\r
@param Multiplier A 64-bit unsigned value.\r
\r
signed value Multiplier and generates a 64-bit signed result. This 64-bit\r
signed result is returned.\r
\r
- If the result overflows, then ASSERT().\r
-\r
@param Multiplicand A 64-bit signed value.\r
@param Multiplier A 64-bit signed value.\r
\r
NULL, then the 64-bit signed remainder is returned in Remainder. This\r
function returns the 64-bit signed quotient.\r
\r
- It is the caller¡¯s responsibility to not call this function with a Divisor of 0.\r
+ It is the caller's responsibility to not call this function with a Divisor of 0.\r
If Divisor is 0, then the quotient and remainder should be assumed to be \r
the largest negative integer.\r
\r
Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 8-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 8-bit value is returned.\r
\r
If 8-bit operations are not supported, then ASSERT().\r
Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 16-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 16-bit value is returned.\r
\r
If 16-bit operations are not supported, then ASSERT().\r
Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 32-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 32-bit value is returned.\r
\r
If 32-bit operations are not supported, then ASSERT().\r
Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the\r
result.\r
\r
- Performs a bitwise inclusive OR between the bit field specified by StartBit\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
and EndBit in Operand and the value specified by OrData. All other bits in\r
Operand are preserved. The new 64-bit value is returned.\r
\r
bitwise OR, and returns the result.\r
\r
Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
- in Operand and the value specified by AndData, followed by a bitwise\r
- inclusive OR with value specified by OrData. All other bits in Operand are\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
preserved. The new 64-bit value is returned.\r
\r
If 64-bit operations are not supported, then ASSERT().\r
IN UINT64 OrData\r
);\r
\r
-\r
-//\r
-// Base Library Synchronization Functions\r
-//\r
-\r
-/**\r
- Retrieves the architecture specific spin lock alignment requirements for\r
- optimal spin lock performance.\r
-\r
- This function retrieves the spin lock alignment requirements for optimal\r
- performance on a given CPU architecture. The spin lock alignment must be a\r
- power of two and is returned by this function. If there are no alignment\r
- requirements, then 1 must be returned. The spin lock synchronization\r
- functions must function correctly if the spin lock size and alignment values\r
- returned by this function are not used at all. These values are hints to the\r
- consumers of the spin lock synchronization functions to obtain optimal spin\r
- lock performance.\r
-\r
- @return The architecture specific spin lock alignment.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-GetSpinLockProperties (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Initializes a spin lock to the released state and returns the spin lock.\r
-\r
- This function initializes the spin lock specified by SpinLock to the released\r
- state, and returns SpinLock. Optimal performance can be achieved by calling\r
- GetSpinLockProperties() to determine the size and alignment requirements for\r
- SpinLock.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to initialize to the released\r
- state.\r
-\r
- @return SpinLock in release state.\r
-\r
-**/\r
-SPIN_LOCK *\r
-EFIAPI\r
-InitializeSpinLock (\r
- OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Waits until a spin lock can be placed in the acquired state.\r
-\r
- This function checks the state of the spin lock specified by SpinLock. If\r
- SpinLock is in the released state, then this function places SpinLock in the\r
- acquired state and returns SpinLock. Otherwise, this function waits\r
- indefinitely for the spin lock to be released, and then places it in the\r
- acquired state and returns SpinLock. All state transitions of SpinLock must\r
- be performed using MP safe mechanisms.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
- If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().\r
- If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in\r
- PcdSpinLockTimeout microseconds, then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to place in the acquired state.\r
-\r
- @return SpinLock accquired lock.\r
-\r
-**/\r
-SPIN_LOCK *\r
-EFIAPI\r
-AcquireSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Attempts to place a spin lock in the acquired state.\r
-\r
- This function checks the state of the spin lock specified by SpinLock. If\r
- SpinLock is in the released state, then this function places SpinLock in the\r
- acquired state and returns TRUE. Otherwise, FALSE is returned. All state\r
- transitions of SpinLock must be performed using MP safe mechanisms.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
- If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to place in the acquired state.\r
-\r
- @retval TRUE SpinLock was placed in the acquired state.\r
- @retval FALSE SpinLock could not be acquired.\r
-\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-AcquireSpinLockOrFail (\r
- IN OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Releases a spin lock.\r
-\r
- This function places the spin lock specified by SpinLock in the release state\r
- and returns SpinLock.\r
-\r
- If SpinLock is NULL, then ASSERT().\r
- If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().\r
-\r
- @param SpinLock A pointer to the spin lock to release.\r
-\r
- @return SpinLock released lock.\r
-\r
-**/\r
-SPIN_LOCK *\r
-EFIAPI\r
-ReleaseSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic increment of an 32-bit unsigned integer.\r
-\r
- Performs an atomic increment of the 32-bit unsigned integer specified by\r
- Value and returns the incremented value. The increment operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 32-bit value to increment.\r
-\r
- @return The incremented value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InterlockedIncrement (\r
- IN UINT32 *Value\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic decrement of an 32-bit unsigned integer.\r
-\r
- Performs an atomic decrement of the 32-bit unsigned integer specified by\r
- Value and returns the decremented value. The decrement operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 32-bit value to decrement.\r
-\r
- @return The decremented value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InterlockedDecrement (\r
- IN UINT32 *Value\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
-\r
- Performs an atomic compare exchange operation on the 32-bit unsigned integer\r
- specified by Value. If Value is equal to CompareValue, then Value is set to\r
- ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,\r
- then Value is returned. The compare exchange operation must be performed using\r
- MP safe mechanisms.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 32-bit value for the compare exchange\r
- operation.\r
- @param CompareValue 32-bit value used in compare operation.\r
- @param ExchangeValue 32-bit value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InterlockedCompareExchange32 (\r
- IN OUT UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
-\r
- Performs an atomic compare exchange operation on the 64-bit unsigned integer specified\r
- by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and\r
- CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.\r
- The compare exchange operation must be performed using MP safe mechanisms.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the 64-bit value for the compare exchange\r
- operation.\r
- @param CompareValue 64-bit value used in compare operation.\r
- @param ExchangeValue 64-bit value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-InterlockedCompareExchange64 (\r
- IN OUT UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
- );\r
-\r
-\r
-/**\r
- Performs an atomic compare exchange operation on a pointer value.\r
-\r
- Performs an atomic compare exchange operation on the pointer value specified\r
- by Value. If Value is equal to CompareValue, then Value is set to\r
- ExchangeValue and CompareValue is returned. If Value is not equal to\r
- CompareValue, then Value is returned. The compare exchange operation must be\r
- performed using MP safe mechanisms.\r
-\r
- If Value is NULL, then ASSERT().\r
-\r
- @param Value A pointer to the pointer value for the compare exchange\r
- operation.\r
- @param CompareValue Pointer value used in compare operation.\r
- @param ExchangeValue Pointer value used in exchange operation.\r
-\r
- @return The original *Value before exchange.\r
-**/\r
-VOID *\r
-EFIAPI\r
-InterlockedCompareExchangePointer (\r
- IN OUT VOID **Value,\r
- IN VOID *CompareValue,\r
- IN VOID *ExchangeValue\r
- );\r
-\r
-\r
//\r
// Base Library Checksum Functions\r
//\r
);\r
\r
\r
-///\r
-/// Base Library CPU Functions\r
-///\r
+//\r
+// Base Library CPU Functions\r
+//\r
+\r
+/**\r
+ Function entry point used when a stack switch is requested with SwitchStack()\r
+\r
+ @param Context1 Context1 parameter passed into SwitchStack().\r
+ @param Context2 Context2 parameter passed into SwitchStack().\r
+\r
+**/\r
typedef\r
VOID\r
(EFIAPI *SWITCH_STACK_ENTRY_POINT)(\r
calls to LongJump() cause a non-zero value to be returned by SetJump().\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
\r
NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.\r
The same structure must never be used for more than one CPU architecture context.\r
the state of JumpBuffer.\r
\r
If JumpBuffer is NULL, then ASSERT().\r
- For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
If Value is 0, then ASSERT().\r
\r
@param JumpBuffer A pointer to CPU context buffer.\r
by Context1 and Context2. Context1 and Context2 are optional and may\r
be NULL. The function EntryPoint must never return. This function\r
supports a variable number of arguments following the NewStack parameter.\r
- These additional arguments are ignored on IA-32, x64, and EBC.\r
- IPF CPUs expect one additional parameter of type VOID * that specifies\r
+ These additional arguments are ignored on IA-32, x64, and EBC architectures.\r
+ Itanium processors expect one additional parameter of type VOID * that specifies\r
the new backing store pointer.\r
\r
If EntryPoint is NULL, then ASSERT().\r
function.\r
@param NewStack A pointer to the new stack to use for the EntryPoint\r
function.\r
- @param ... This variable argument list is ignored for IA32, x64, and EBC. \r
- For IPF, this variable argument list is expected to contain \r
+ @param ... This variable argument list is ignored for IA-32, x64, and EBC architectures. \r
+ For Itanium processors, this variable argument list is expected to contain \r
a single parameter of type VOID * that specifies the new backing \r
store pointer.\r
\r
CpuDeadLoop (\r
VOID\r
);\r
-\r
+ \r
#if defined (MDE_CPU_IPF)\r
\r
/**\r
Flush a range of cache lines in the cache coherency domain of the calling\r
CPU.\r
\r
- Invalidates the cache lines specified by Address and Length. If Address is\r
- not aligned on a cache line boundary, then entire cache line containing\r
- Address is invalidated. If Address + Length is not aligned on a cache line\r
- boundary, then the entire instruction cache line containing Address + Length\r
- -1 is invalidated. This function may choose to invalidate the entire\r
- instruction cache if that is more efficient than invalidating the specified\r
- range. If Length is 0, the no instruction cache lines are invalidated.\r
- Address is returned.\r
+ Flushes the cache lines specified by Address and Length. If Address is not aligned \r
+ on a cache line boundary, then entire cache line containing Address is flushed. \r
+ If Address + Length is not aligned on a cache line boundary, then the entire cache \r
+ line containing Address + Length - 1 is flushed. This function may choose to flush \r
+ the entire cache if that is more efficient than flushing the specified range. If \r
+ Length is 0, the no cache lines are flushed. Address is returned. \r
+ This function is only available on Itanium processors.\r
\r
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
\r
\r
@param Length The number of bytes to invalidate from the instruction cache.\r
\r
- @return Address\r
+ @return Address.\r
\r
**/\r
VOID *\r
EFIAPI\r
-IpfFlushCacheRange (\r
+AsmFlushCacheRange (\r
IN VOID *Address,\r
IN UINTN Length\r
);\r
Executes a FC instruction\r
Executes a FC instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
Executes a FC.I instruction.\r
Executes a FC.I instruction on the cache line specified by Address.\r
The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on IPF.\r
+ An implementation may flush a larger region. This function is only available on Itanium processors.\r
\r
@param Address The Address of cache line to be flushed.\r
\r
No parameter checking is performed on Index. If the Index value is beyond the\r
implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
must either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults. This function is only available on IPF.\r
+ catch the faults. This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Processor Identifier Register index to read.\r
\r
\r
/**\r
Reads the current value of 64-bit Processor Status Register (PSR).\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of PSR.\r
\r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults. This function is only available on IPF.\r
+ fault handlers to catch the faults. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PSR.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #0 (KR0).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of KR0. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR0.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #1 (KR1).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR1. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR1.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #2 (KR2).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR2. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR2.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #3 (KR3).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR3. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR3.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #4 (KR4).\r
- This function is only available on IPF.\r
\r
+ Reads and returns the current value of KR4. \r
+ This function is only available on Itanium processors.\r
+ \r
@return The current value of KR4.\r
\r
**/\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #5 (KR5).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR5. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR5.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #6 (KR6).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR6. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR6.\r
\r
\r
/**\r
Reads the current value of 64-bit Kernel Register #7 (KR7).\r
- This function is only available on IPF.\r
+\r
+ Reads and returns the current value of KR7. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of KR7.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #0 (KR0).\r
- This function is only available on IPF.\r
+ \r
+ Writes the current value of KR0. The 64-bit value written to \r
+ the KR0 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR0.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #1 (KR1).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR1. The 64-bit value written to \r
+ the KR1 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR1.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #2 (KR2).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR2. The 64-bit value written to \r
+ the KR2 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR2.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #3 (KR3).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR3. The 64-bit value written to \r
+ the KR3 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR3.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #4 (KR4).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR4. The 64-bit value written to \r
+ the KR4 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR4.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #5 (KR5).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR5. The 64-bit value written to \r
+ the KR5 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR5.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #6 (KR6).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR6. The 64-bit value written to \r
+ the KR6 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR6.\r
\r
\r
/**\r
Write the current value of 64-bit Kernel Register #7 (KR7).\r
- This function is only available on IPF.\r
+\r
+ Writes the current value of KR7. The 64-bit value written to \r
+ the KR7 is returned. This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to KR7.\r
\r
\r
/**\r
Reads the current value of Interval Timer Counter Register (ITC).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of ITC.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITC.\r
\r
\r
/**\r
Reads the current value of Interval Timer Vector Register (ITV).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of ITV. \r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITV.\r
\r
\r
/**\r
Reads the current value of Interval Timer Match Register (ITM).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of ITM.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of ITM.\r
**/\r
\r
/**\r
Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
- This function is only available on IPF.\r
+ \r
+ Writes the current value of ITC. The 64-bit value written to the ITC is returned. \r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITC.\r
\r
\r
/**\r
Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
- This function is only available on IPF.\r
+ \r
+ Writes the current value of ITM. The 64-bit value written to the ITM is returned. \r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITM.\r
\r
\r
/**\r
Writes the current value of 64-bit Interval Timer Vector Register (ITV).\r
+ \r
+ Writes the current value of ITV. The 64-bit value written to the ITV is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to ITV.\r
\r
\r
/**\r
Reads the current value of Default Control Register (DCR).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
\r
@return The current value of DCR.\r
\r
\r
/**\r
Reads the current value of Interruption Vector Address Register (IVA).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
\r
@return The current value of IVA.\r
**/\r
\r
/**\r
Reads the current value of Page Table Address Register (PTA).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
\r
@return The current value of PTA.\r
\r
\r
/**\r
Writes the current value of 64-bit Default Control Register (DCR).\r
+ \r
+ Writes the current value of DCR. The 64-bit value written to the DCR is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to DCR.\r
\r
\r
/**\r
Writes the current value of 64-bit Interruption Vector Address Register (IVA).\r
+ \r
+ Writes the current value of IVA. The 64-bit value written to the IVA is returned. \r
The size of vector table is 32 K bytes and is 32 K bytes aligned\r
the low 15 bits of Value is ignored when written.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to IVA.\r
\r
\r
/**\r
Writes the current value of 64-bit Page Table Address Register (PTA).\r
+ \r
+ Writes the current value of PTA. The 64-bit value written to the PTA is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PTA.\r
\r
\r
/**\r
Reads the current value of Local Interrupt ID Register (LID).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of LID. This function is only available on Itanium processors.\r
\r
@return The current value of LID.\r
\r
\r
/**\r
Reads the current value of External Interrupt Vector Register (IVR).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IVR. This function is only available on Itanium processors. \r
\r
@return The current value of IVR.\r
\r
\r
/**\r
Reads the current value of Task Priority Register (TPR).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of TPR. This function is only available on Itanium processors. \r
\r
@return The current value of TPR.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #0 (IRR0).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR0. This function is only available on Itanium processors. \r
\r
@return The current value of IRR0.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #1 (IRR1).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR1. This function is only available on Itanium processors. \r
\r
@return The current value of IRR1.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #2 (IRR2).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
\r
@return The current value of IRR2.\r
\r
\r
/**\r
Reads the current value of External Interrupt Request Register #3 (IRR3).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of IRR3. This function is only available on Itanium processors. \r
\r
@return The current value of IRR3.\r
\r
\r
/**\r
Reads the current value of Performance Monitor Vector Register (PMV).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of PMV. This function is only available on Itanium processors. \r
\r
@return The current value of PMV.\r
\r
\r
/**\r
Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
\r
@return The current value of CMCV.\r
\r
\r
/**\r
Reads the current value of Local Redirection Register #0 (LRR0).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of LRR0. This function is only available on Itanium processors. \r
\r
@return The current value of LRR0.\r
\r
\r
/**\r
Reads the current value of Local Redirection Register #1 (LRR1).\r
- This function is only available on IPF.\r
+ \r
+ Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
\r
@return The current value of LRR1.\r
\r
\r
/**\r
Writes the current value of 64-bit Page Local Interrupt ID Register (LID).\r
+ \r
+ Writes the current value of LID. The 64-bit value written to the LID is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LID.\r
\r
\r
/**\r
Writes the current value of 64-bit Task Priority Register (TPR).\r
+ \r
+ Writes the current value of TPR. The 64-bit value written to the TPR is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding to\r
reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to TPR.\r
\r
\r
/**\r
Performs a write operation on End OF External Interrupt Register (EOI).\r
- Writes a value of 0 to the EOI Register. This function is only available on IPF.\r
+ \r
+ Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
\r
**/\r
VOID\r
\r
/**\r
Writes the current value of 64-bit Performance Monitor Vector Register (PMV).\r
+ \r
+ Writes the current value of PMV. The 64-bit value written to the PMV is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to PMV.\r
\r
\r
/**\r
Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).\r
+ \r
+ Writes the current value of CMCV. The 64-bit value written to the CMCV is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to CMCV.\r
\r
\r
/**\r
Writes the current value of 64-bit Local Redirection Register #0 (LRR0).\r
+ \r
+ Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR0.\r
\r
\r
/**\r
Writes the current value of 64-bit Local Redirection Register #1 (LRR1).\r
+ \r
+ Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned. \r
No parameter checking is performed on Value. All bits of Value corresponding\r
to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Value is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to LRR1.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to read.\r
\r
the implemented DBR register range, a Reserved Register/Field fault may occur.\r
The caller must either guarantee that Index is valid, or the caller must set up\r
fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to read.\r
\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMC register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to read.\r
\r
- @return The current value of Performance Monitor Configuration Register\r
- specified by Index.\r
+ @return The current value of Performance Monitor Configuration Register\r
+ specified by Index.\r
\r
**/\r
UINT64\r
register set is implementation dependent. No parameter checking is performed\r
on Index. If the Index value is beyond the implemented PMD register range,\r
zero value will be returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to read.\r
\r
is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
occur. The caller must either guarantee that Index is valid, or the caller must\r
set up fault handlers to catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Instruction Breakpoint Register index to write.\r
@param Value The 64-bit value to write to IBR.\r
DBR register range, a Reserved Register/Field fault may occur. The caller must\r
either guarantee that Index is valid, or the caller must set up fault handlers to\r
catch the faults.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Data Breakpoint Register index to write.\r
@param Value The 64-bit value to write to DBR.\r
counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
dependent. No parameter checking is performed on Index. If the Index value is\r
beyond the implemented PMC register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Configuration Register index to write.\r
@param Value The 64-bit value to write to PMC.\r
performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set\r
is implementation dependent. No parameter checking is performed on Index. If the\r
Index value is beyond the implemented PMD register range, the write is ignored.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Index The 8-bit Performance Monitor Data Register index to write.\r
@param Value The 64-bit value to write to PMD.\r
Reads the current value of 64-bit Global Pointer (GP).\r
\r
Reads and returns the current value of GP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of GP.\r
\r
\r
Writes the current value of GP. The 64-bit value written to the GP is returned.\r
No parameter checking is performed on Value.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@param Value The 64-bit value to write to GP.\r
\r
Reads the current value of 64-bit Stack Pointer (SP).\r
\r
Reads and returns the current value of SP.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@return The current value of SP.\r
\r
);\r
\r
\r
+///\r
+/// Valid Index value for AsmReadControlRegister()\r
+///\r
+#define IPF_CONTROL_REGISTER_DCR 0\r
+#define IPF_CONTROL_REGISTER_ITM 1\r
+#define IPF_CONTROL_REGISTER_IVA 2\r
+#define IPF_CONTROL_REGISTER_PTA 8\r
+#define IPF_CONTROL_REGISTER_IPSR 16\r
+#define IPF_CONTROL_REGISTER_ISR 17\r
+#define IPF_CONTROL_REGISTER_IIP 19\r
+#define IPF_CONTROL_REGISTER_IFA 20\r
+#define IPF_CONTROL_REGISTER_ITIR 21\r
+#define IPF_CONTROL_REGISTER_IIPA 22\r
+#define IPF_CONTROL_REGISTER_IFS 23\r
+#define IPF_CONTROL_REGISTER_IIM 24\r
+#define IPF_CONTROL_REGISTER_IHA 25\r
+#define IPF_CONTROL_REGISTER_LID 64\r
+#define IPF_CONTROL_REGISTER_IVR 65\r
+#define IPF_CONTROL_REGISTER_TPR 66\r
+#define IPF_CONTROL_REGISTER_EOI 67\r
+#define IPF_CONTROL_REGISTER_IRR0 68\r
+#define IPF_CONTROL_REGISTER_IRR1 69\r
+#define IPF_CONTROL_REGISTER_IRR2 70\r
+#define IPF_CONTROL_REGISTER_IRR3 71\r
+#define IPF_CONTROL_REGISTER_ITV 72\r
+#define IPF_CONTROL_REGISTER_PMV 73\r
+#define IPF_CONTROL_REGISTER_CMCV 74\r
+#define IPF_CONTROL_REGISTER_LRR0 80\r
+#define IPF_CONTROL_REGISTER_LRR1 81\r
+\r
+/**\r
+ Reads a 64-bit control register.\r
+\r
+ Reads and returns the control register specified by Index. The valid Index valued are defined\r
+ above in "Related Definitions".\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
+\r
+ @param Index The index of the control register to read.\r
+\r
+ @return The control register specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegister (\r
+ IN UINT64 Index\r
+ );\r
+\r
+\r
+///\r
+/// Valid Index value for AsmReadApplicationRegister()\r
+///\r
+#define IPF_APPLICATION_REGISTER_K0 0\r
+#define IPF_APPLICATION_REGISTER_K1 1\r
+#define IPF_APPLICATION_REGISTER_K2 2\r
+#define IPF_APPLICATION_REGISTER_K3 3\r
+#define IPF_APPLICATION_REGISTER_K4 4\r
+#define IPF_APPLICATION_REGISTER_K5 5\r
+#define IPF_APPLICATION_REGISTER_K6 6\r
+#define IPF_APPLICATION_REGISTER_K7 7\r
+#define IPF_APPLICATION_REGISTER_RSC 16\r
+#define IPF_APPLICATION_REGISTER_BSP 17\r
+#define IPF_APPLICATION_REGISTER_BSPSTORE 18\r
+#define IPF_APPLICATION_REGISTER_RNAT 19\r
+#define IPF_APPLICATION_REGISTER_FCR 21\r
+#define IPF_APPLICATION_REGISTER_EFLAG 24\r
+#define IPF_APPLICATION_REGISTER_CSD 25\r
+#define IPF_APPLICATION_REGISTER_SSD 26\r
+#define IPF_APPLICATION_REGISTER_CFLG 27\r
+#define IPF_APPLICATION_REGISTER_FSR 28\r
+#define IPF_APPLICATION_REGISTER_FIR 29\r
+#define IPF_APPLICATION_REGISTER_FDR 30\r
+#define IPF_APPLICATION_REGISTER_CCV 32\r
+#define IPF_APPLICATION_REGISTER_UNAT 36\r
+#define IPF_APPLICATION_REGISTER_FPSR 40\r
+#define IPF_APPLICATION_REGISTER_ITC 44\r
+#define IPF_APPLICATION_REGISTER_PFS 64\r
+#define IPF_APPLICATION_REGISTER_LC 65\r
+#define IPF_APPLICATION_REGISTER_EC 66\r
+\r
+/**\r
+ Reads a 64-bit application register.\r
+\r
+ Reads and returns the application register specified by Index. The valid Index valued are defined\r
+ above in "Related Definitions".\r
+ If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on Itanium processors.\r
+\r
+ @param Index The index of the application register to read.\r
+\r
+ @return The application register specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegister (\r
+ IN UINT64 Index\r
+ );\r
+\r
+\r
+/**\r
+ Reads the current value of a Machine Specific Register (MSR).\r
+\r
+ Reads and returns the current value of the Machine Specific Register specified by Index. No\r
+ parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
+ register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
+ Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
+ only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Machine Specific Register index to read.\r
+\r
+ @return The current value of the Machine Specific Register specified by Index. \r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMsr (\r
+ IN UINT8 Index \r
+ );\r
+\r
+\r
+/**\r
+ Writes the current value of a Machine Specific Register (MSR).\r
+\r
+ Writes Value to the Machine Specific Register specified by Index. Value is returned. No\r
+ parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
+ register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
+ Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
+ only available on Itanium processors.\r
+\r
+ @param Index The 8-bit Machine Specific Register index to write.\r
+ @param Value The 64-bit value to write to the Machine Specific Register.\r
+\r
+ @return The 64-bit value to write to the Machine Specific Register. \r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteMsr (\r
+ IN UINT8 Index, \r
+ IN UINT64 Value \r
+ );\r
+\r
+\r
/**\r
Determines if the CPU is currently executing in virtual, physical, or mixed mode.\r
\r
If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
and -1 is returned.\r
- This function is only available on IPF.\r
+ This function is only available on Itanium processors.\r
\r
@retval 1 The CPU is in virtual mode.\r
@retval 0 The CPU is in physical mode.\r
argument return value may be returned or undefined result may occur during the\r
execution of the procedure. If the PalEntryPoint does not point to a valid\r
PAL entry point then the system behavior is undefined. This function is only\r
- available on IPF.\r
+ available on Itanium processors.\r
\r
@param PalEntryPoint The PAL procedure calls entry point.\r
@param Index The PAL procedure Index number.\r
IN UINT64 Arg3,\r
IN UINT64 Arg4\r
);\r
+#endif\r
\r
-\r
-/**\r
- Transfers control to a function starting with a new stack.\r
-\r
- Transfers control to the function specified by EntryPoint using the new stack\r
- specified by NewStack and passing in the parameters specified by Context1 and\r
- Context2. Context1 and Context2 are optional and may be NULL. The function\r
- EntryPoint must never return.\r
-\r
- If EntryPoint is NULL, then ASSERT().\r
- If NewStack is NULL, then ASSERT().\r
-\r
- @param EntryPoint A pointer to function to call with the new stack.\r
- @param Context1 A pointer to the context to pass into the EntryPoint\r
- function.\r
- @param Context2 A pointer to the context to pass into the EntryPoint\r
- function.\r
- @param NewStack A pointer to the new stack to use for the EntryPoint\r
- function.\r
- @param NewBsp A pointer to the new memory location for RSE backing\r
- store.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmSwitchStackAndBackingStore (\r
- IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
- IN VOID *Context1, OPTIONAL\r
- IN VOID *Context2, OPTIONAL\r
- IN VOID *NewStack,\r
- IN VOID *NewBsp\r
- );\r
-\r
-/**\r
- @todo This call should be removed after the PalCall\r
- Instance issue has been fixed.\r
-\r
- Performs a PAL call using static calling convention.\r
-\r
- An internal function to perform a PAL call using static calling convention.\r
-\r
- @param PalEntryPoint The entry point address of PAL. The address in ar.kr5\r
- would be used if this parameter were NULL on input.\r
- @param Arg1 The first argument of a PAL call.\r
- @param Arg2 The second argument of a PAL call.\r
- @param Arg3 The third argument of a PAL call.\r
- @param Arg4 The fourth argument of a PAL call.\r
-\r
- @return The values returned in r8, r9, r10 and r11.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-PalCallStatic (\r
- IN CONST VOID *PalEntryPoint,\r
- IN UINT64 Arg1,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
-\r
-\r
-\r
-#elif defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
-/// IA32 and X64 Specific Functions\r
+/// IA32 and x64 Specific Functions\r
/// Byte packed structure for 16-bit Real Mode EFLAGS\r
///\r
typedef union {\r
struct {\r
- UINT32 CF:1; /// Carry Flag\r
- UINT32 Reserved_0:1; /// Reserved\r
- UINT32 PF:1; /// Parity Flag\r
- UINT32 Reserved_1:1; /// Reserved\r
- UINT32 AF:1; /// Auxiliary Carry Flag\r
- UINT32 Reserved_2:1; /// Reserved\r
- UINT32 ZF:1; /// Zero Flag\r
- UINT32 SF:1; /// Sign Flag\r
- UINT32 TF:1; /// Trap Flag\r
- UINT32 IF:1; /// Interrupt Enable Flag\r
- UINT32 DF:1; /// Direction Flag\r
- UINT32 OF:1; /// Overflow Flag\r
- UINT32 IOPL:2; /// I/O Privilege Level\r
- UINT32 NT:1; /// Nested Task\r
- UINT32 Reserved_3:1; /// Reserved\r
+ UINT32 CF:1; ///< Carry Flag\r
+ UINT32 Reserved_0:1; ///< Reserved\r
+ UINT32 PF:1; ///< Parity Flag\r
+ UINT32 Reserved_1:1; ///< Reserved\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag\r
+ UINT32 Reserved_2:1; ///< Reserved\r
+ UINT32 ZF:1; ///< Zero Flag\r
+ UINT32 SF:1; ///< Sign Flag\r
+ UINT32 TF:1; ///< Trap Flag\r
+ UINT32 IF:1; ///< Interrupt Enable Flag\r
+ UINT32 DF:1; ///< Direction Flag\r
+ UINT32 OF:1; ///< Overflow Flag\r
+ UINT32 IOPL:2; ///< I/O Privilege Level\r
+ UINT32 NT:1; ///< Nested Task\r
+ UINT32 Reserved_3:1; ///< Reserved\r
} Bits;\r
UINT16 Uint16;\r
} IA32_FLAGS16;\r
///\r
/// Byte packed structure for EFLAGS/RFLAGS\r
/// 32-bits on IA-32\r
-/// 64-bits on X64. The upper 32-bits on X64 are reserved\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved\r
///\r
typedef union {\r
struct {\r
- UINT32 CF:1; /// Carry Flag\r
- UINT32 Reserved_0:1; /// Reserved\r
- UINT32 PF:1; /// Parity Flag\r
- UINT32 Reserved_1:1; /// Reserved\r
- UINT32 AF:1; /// Auxiliary Carry Flag\r
- UINT32 Reserved_2:1; /// Reserved\r
- UINT32 ZF:1; /// Zero Flag\r
- UINT32 SF:1; /// Sign Flag\r
- UINT32 TF:1; /// Trap Flag\r
- UINT32 IF:1; /// Interrupt Enable Flag\r
- UINT32 DF:1; /// Direction Flag\r
- UINT32 OF:1; /// Overflow Flag\r
- UINT32 IOPL:2; /// I/O Privilege Level\r
- UINT32 NT:1; /// Nested Task\r
- UINT32 Reserved_3:1; /// Reserved\r
- UINT32 RF:1; /// Resume Flag\r
- UINT32 VM:1; /// Virtual 8086 Mode\r
- UINT32 AC:1; /// Alignment Check\r
- UINT32 VIF:1; /// Virtual Interrupt Flag\r
- UINT32 VIP:1; /// Virtual Interrupt Pending\r
- UINT32 ID:1; /// ID Flag\r
- UINT32 Reserved_4:10; /// Reserved\r
+ UINT32 CF:1; ///< Carry Flag\r
+ UINT32 Reserved_0:1; ///< Reserved\r
+ UINT32 PF:1; ///< Parity Flag\r
+ UINT32 Reserved_1:1; ///< Reserved\r
+ UINT32 AF:1; ///< Auxiliary Carry Flag\r
+ UINT32 Reserved_2:1; ///< Reserved\r
+ UINT32 ZF:1; ///< Zero Flag\r
+ UINT32 SF:1; ///< Sign Flag\r
+ UINT32 TF:1; ///< Trap Flag\r
+ UINT32 IF:1; ///< Interrupt Enable Flag\r
+ UINT32 DF:1; ///< Direction Flag\r
+ UINT32 OF:1; ///< Overflow Flag\r
+ UINT32 IOPL:2; ///< I/O Privilege Level\r
+ UINT32 NT:1; ///< Nested Task\r
+ UINT32 Reserved_3:1; ///< Reserved\r
+ UINT32 RF:1; ///< Resume Flag\r
+ UINT32 VM:1; ///< Virtual 8086 Mode\r
+ UINT32 AC:1; ///< Alignment Check\r
+ UINT32 VIF:1; ///< Virtual Interrupt Flag\r
+ UINT32 VIP:1; ///< Virtual Interrupt Pending\r
+ UINT32 ID:1; ///< ID Flag\r
+ UINT32 Reserved_4:10; ///< Reserved\r
} Bits;\r
UINTN UintN;\r
} IA32_EFLAGS32;\r
///\r
/// Byte packed structure for Control Register 0 (CR0)\r
/// 32-bits on IA-32\r
-/// 64-bits on X64. The upper 32-bits on X64 are reserved\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved\r
///\r
typedef union {\r
struct {\r
- UINT32 PE:1; /// Protection Enable\r
- UINT32 MP:1; /// Monitor Coprocessor\r
- UINT32 EM:1; /// Emulation\r
- UINT32 TS:1; /// Task Switched\r
- UINT32 ET:1; /// Extension Type\r
- UINT32 NE:1; /// Numeric Error\r
- UINT32 Reserved_0:10; /// Reserved\r
- UINT32 WP:1; /// Write Protect\r
- UINT32 Reserved_1:1; /// Reserved\r
- UINT32 AM:1; /// Alignment Mask\r
- UINT32 Reserved_2:10; /// Reserved\r
- UINT32 NW:1; /// Mot Write-through\r
- UINT32 CD:1; /// Cache Disable\r
- UINT32 PG:1; /// Paging\r
+ UINT32 PE:1; ///< Protection Enable\r
+ UINT32 MP:1; ///< Monitor Coprocessor\r
+ UINT32 EM:1; ///< Emulation\r
+ UINT32 TS:1; ///< Task Switched\r
+ UINT32 ET:1; ///< Extension Type\r
+ UINT32 NE:1; ///< Numeric Error\r
+ UINT32 Reserved_0:10; ///< Reserved\r
+ UINT32 WP:1; ///< Write Protect\r
+ UINT32 Reserved_1:1; ///< Reserved\r
+ UINT32 AM:1; ///< Alignment Mask\r
+ UINT32 Reserved_2:10; ///< Reserved\r
+ UINT32 NW:1; ///< Mot Write-through\r
+ UINT32 CD:1; ///< Cache Disable\r
+ UINT32 PG:1; ///< Paging\r
} Bits;\r
UINTN UintN;\r
} IA32_CR0;\r
///\r
/// Byte packed structure for Control Register 4 (CR4)\r
/// 32-bits on IA-32\r
-/// 64-bits on X64. The upper 32-bits on X64 are reserved\r
+/// 64-bits on x64. The upper 32-bits on x64 are reserved\r
///\r
typedef union {\r
struct {\r
- UINT32 VME:1; /// Virtual-8086 Mode Extensions\r
- UINT32 PVI:1; /// Protected-Mode Virtual Interrupts\r
- UINT32 TSD:1; /// Time Stamp Disable\r
- UINT32 DE:1; /// Debugging Extensions\r
- UINT32 PSE:1; /// Page Size Extensions\r
- UINT32 PAE:1; /// Physical Address Extension\r
- UINT32 MCE:1; /// Machine Check Enable\r
- UINT32 PGE:1; /// Page Global Enable\r
- UINT32 PCE:1; /// Performance Monitoring Counter\r
- /// Enable\r
- UINT32 OSFXSR:1; /// Operating System Support for\r
- /// FXSAVE and FXRSTOR instructions\r
- UINT32 OSXMMEXCPT:1; /// Operating System Support for\r
- /// Unmasked SIMD Floating Point\r
- /// Exceptions\r
- UINT32 Reserved_0:2; /// Reserved\r
- UINT32 VMXE:1; /// VMX Enable\r
- UINT32 Reserved_1:18; /// Reseved\r
+ UINT32 VME:1; ///< Virtual-8086 Mode Extensions\r
+ UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts\r
+ UINT32 TSD:1; ///< Time Stamp Disable\r
+ UINT32 DE:1; ///< Debugging Extensions\r
+ UINT32 PSE:1; ///< Page Size Extensions\r
+ UINT32 PAE:1; ///< Physical Address Extension\r
+ UINT32 MCE:1; ///< Machine Check Enable\r
+ UINT32 PGE:1; ///< Page Global Enable\r
+ UINT32 PCE:1; ///< Performance Monitoring Counter\r
+ ///< Enable\r
+ UINT32 OSFXSR:1; ///< Operating System Support for\r
+ ///< FXSAVE and FXRSTOR instructions\r
+ UINT32 OSXMMEXCPT:1; ///< Operating System Support for\r
+ ///< Unmasked SIMD Floating Point\r
+ ///< Exceptions\r
+ UINT32 Reserved_0:2; ///< Reserved\r
+ UINT32 VMXE:1; ///< VMX Enable\r
+ UINT32 Reserved_1:18; ///< Reserved\r
} Bits;\r
UINTN UintN;\r
} IA32_CR4;\r
\r
///\r
/// Byte packed structure for an IDTR, GDTR, LDTR descriptor\r
-/// @todo How to make this structure byte-packed in a compiler independent way?\r
///\r
#pragma pack (1)\r
typedef struct {\r
#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E\r
#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F\r
\r
+\r
+#if defined (MDE_CPU_IA32)\r
///\r
-/// Byte packed structure for an Interrupt Gate Descriptor\r
+/// Byte packed structure for an IA-32 Interrupt Gate Descriptor\r
///\r
-#if defined (MDE_CPU_IA32)\r
-\r
typedef union {\r
struct {\r
- UINT32 OffsetLow:16; // Offset bits 15..0\r
- UINT32 Selector:16; // Selector\r
- UINT32 Reserved_0:8; // Reserved\r
- UINT32 GateType:8; // Gate Type. See #defines above\r
- UINT32 OffsetHigh:16; // Offset bits 31..16\r
+ UINT32 OffsetLow:16; ///< Offset bits 15..0\r
+ UINT32 Selector:16; ///< Selector\r
+ UINT32 Reserved_0:8; ///< Reserved\r
+ UINT32 GateType:8; ///< Gate Type. See #defines above\r
+ UINT32 OffsetHigh:16; ///< Offset bits 31..16\r
} Bits;\r
UINT64 Uint64;\r
} IA32_IDT_GATE_DESCRIPTOR;\r
#endif\r
\r
#if defined (MDE_CPU_X64)\r
-\r
+///\r
+/// Byte packed structure for an x64 Interrupt Gate Descriptor\r
+///\r
typedef union {\r
struct {\r
- UINT32 OffsetLow:16; // Offset bits 15..0\r
- UINT32 Selector:16; // Selector\r
- UINT32 Reserved_0:8; // Reserved\r
- UINT32 GateType:8; // Gate Type. See #defines above\r
- UINT32 OffsetHigh:16; // Offset bits 31..16\r
- UINT32 OffsetUpper:32; // Offset bits 63..32\r
- UINT32 Reserved_1:32; // Reserved\r
+ UINT32 OffsetLow:16; ///< Offset bits 15..0\r
+ UINT32 Selector:16; ///< Selector\r
+ UINT32 Reserved_0:8; ///< Reserved\r
+ UINT32 GateType:8; ///< Gate Type. See #defines above\r
+ UINT32 OffsetHigh:16; ///< Offset bits 31..16\r
+ UINT32 OffsetUpper:32; ///< Offset bits 63..32\r
+ UINT32 Reserved_1:32; ///< Reserved\r
} Bits;\r
- UINT64 Uint64;\r
- UINT64 Uint64_1;\r
+ struct {\r
+ UINT64 Uint64;\r
+ UINT64 Uint64_1;\r
+ } Uint128; \r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
#endif\r
If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r
If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r
If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r
- This function is only available on IA-32 and X64.\r
+ This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit value to load into EAX prior to invoking the CPUID\r
instruction.\r
@param Edx Pointer to the 32-bit EDX value returned by the CPUID\r
instruction. This is an optional parameter that may be NULL.\r
\r
- @return Index\r
+ @return Index.\r
\r
**/\r
UINT32\r
instruction. This is an optional parameter that may be\r
NULL.\r
\r
- @return Index\r
+ @return Index.\r
\r
**/\r
UINT32\r
);\r
\r
\r
+/**\r
+ Set CD bit and clear NW bit of CR0 followed by a WBINVD.\r
+\r
+ Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,\r
+ and executing a WBINVD instruction. This function is only available on IA-32 and x64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmDisableCache (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Perform a WBINVD and clear both the CD and NW bits of CR0.\r
+\r
+ Enables the caches by executing a WBINVD instruction and then clear both the CD and NW\r
+ bits of CR0 to 0. This function is only available on IA-32 and x64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmEnableCache (\r
+ VOID\r
+ );\r
+\r
+\r
/**\r
Returns the lower 32-bits of a Machine Specific Register(MSR).\r
\r
No parameter checking is performed on Index, and some Index values may cause\r
CPU exceptions. The caller must either guarantee that Index is valid, or the\r
caller must set up exception handlers to catch the exceptions. This function\r
- is only available on IA-32 and X64.\r
+ is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to read.\r
\r
the MSR is returned. No parameter checking is performed on Index or Value,\r
and some of these may cause CPU exceptions. The caller must either guarantee\r
that Index and Value are valid, or the caller must establish proper exception\r
- handlers. This function is only available on IA-32 and X64.\r
+ handlers. This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param Value The 32-bit value to write to the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise inclusive OR on the lower 32-bits, and\r
+ Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and\r
writes the result back to the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the lower 32-bits of the read result and the value specified by\r
OrData, and writes the result to the 64-bit MSR specified by Index. The lower\r
32-bits of the value written to the MSR is returned. No parameter checking is\r
performed on Index or OrData, and some of these may cause CPU exceptions. The\r
caller must either guarantee that Index and OrData are valid, or the caller\r
must establish proper exception handlers. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param OrData The value to OR with the read value from the MSR.\r
on Index or AndData, and some of these may cause CPU exceptions. The caller\r
must either guarantee that Index and AndData are valid, or the caller must\r
establish proper exception handlers. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive OR\r
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR\r
on the lower 32-bits, and writes the result back to the 64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r
lower 32-bits of the read result and the value specified by AndData\r
- preserving the upper 32-bits, performs a bitwise inclusive OR between the\r
+ preserving the upper 32-bits, performs a bitwise OR between the\r
result of the AND operation and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Address. The lower 32-bits of the value\r
written to the MSR is returned. No parameter checking is performed on Index,\r
AndData, or OrData, and some of these may cause CPU exceptions. The caller\r
must either guarantee that Index, AndData, and OrData are valid, or the\r
caller must establish proper exception handlers. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
specified by the StartBit and the EndBit. The value of the bit field is\r
returned. The caller must either guarantee that Index is valid, or the caller\r
must set up exception handlers to catch the exceptions. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
/**\r
Writes a bit field to an MSR.\r
\r
- Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r
+ Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r
field is specified by the StartBit and the EndBit. All other bits in the\r
destination MSR are preserved. The lower 32-bits of the MSR written is\r
- returned. Extra left bits in Value are stripped. The caller must either\r
- guarantee that Index and the data written is valid, or the caller must set up\r
- exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ returned. The caller must either guarantee that Index and the data written \r
+ is valid, or the caller must set up exception handlers to catch the exceptions. \r
+ This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the\r
result back to the bit field in the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the read result and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Index. The lower 32-bits of the value\r
written to the MSR are returned. Extra left bits in OrData are stripped. The\r
caller must either guarantee that Index and the data written is valid, or\r
the caller must set up exception handlers to catch the exceptions. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
MSR are returned. Extra left bits in AndData are stripped. The caller must\r
either guarantee that Index and the data written is valid, or the caller must\r
set up exception handlers to catch the exceptions. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
AndData, and writes the result to the 64-bit MSR specified by Index. The\r
lower 32-bits of the value written to the MSR are returned. Extra left bits\r
in both AndData and OrData are stripped. The caller must either guarantee\r
that Index and the data written is valid, or the caller must set up exception\r
handlers to catch the exceptions. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
performed on Index, and some Index values may cause CPU exceptions. The\r
caller must either guarantee that Index is valid, or the caller must set up\r
exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to read.\r
\r
performed on Index or Value, and some of these may cause CPU exceptions. The\r
caller must either guarantee that Index and Value are valid, or the caller\r
must establish proper exception handlers. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param Value The 64-bit value to write to the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise inclusive OR, and writes the result\r
+ Reads a 64-bit MSR, performs a bitwise OR, and writes the result\r
back to the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the read result and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Index. The value written to the MSR is\r
returned. No parameter checking is performed on Index or OrData, and some of\r
these may cause CPU exceptions. The caller must either guarantee that Index\r
and OrData are valid, or the caller must establish proper exception handlers.\r
- This function is only available on IA-32 and X64.\r
+ This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param OrData The value to OR with the read value from the MSR.\r
parameter checking is performed on Index or OrData, and some of these may\r
cause CPU exceptions. The caller must either guarantee that Index and OrData\r
are valid, or the caller must establish proper exception handlers. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
\r
\r
/**\r
- Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive\r
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise \r
OR, and writes the result back to the 64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND between read\r
- result and the value specified by AndData, performs a bitwise inclusive OR\r
+ result and the value specified by AndData, performs a bitwise OR\r
between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 64-bit MSR specified by Index. The value written\r
to the MSR is returned. No parameter checking is performed on Index, AndData,\r
or OrData, and some of these may cause CPU exceptions. The caller must either\r
guarantee that Index, AndData, and OrData are valid, or the caller must\r
establish proper exception handlers. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
@param Index The 32-bit MSR index to write.\r
@param AndData The value to AND with the read value from the MSR.\r
StartBit and the EndBit. The value of the bit field is returned. The caller\r
must either guarantee that Index is valid, or the caller must set up\r
exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
\r
Writes Value to a bit field in a 64-bit MSR. The bit field is specified by\r
the StartBit and the EndBit. All other bits in the destination MSR are\r
- preserved. The MSR written is returned. Extra left bits in Value are\r
- stripped. The caller must either guarantee that Index and the data written is\r
- valid, or the caller must set up exception handlers to catch the exceptions.\r
- This function is only available on IA-32 and X64.\r
+ preserved. The MSR written is returned. The caller must either guarantee \r
+ that Index and the data written is valid, or the caller must set up exception \r
+ handlers to catch the exceptions. This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
\r
\r
/**\r
- Reads a bit field in a 64-bit MSR, performs a bitwise inclusive OR, and\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and\r
writes the result back to the bit field in the 64-bit MSR.\r
\r
- Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
between the read result and the value specified by OrData, and writes the\r
result to the 64-bit MSR specified by Index. The value written to the MSR is\r
returned. Extra left bits in OrData are stripped. The caller must either\r
guarantee that Index and the data written is valid, or the caller must set up\r
exception handlers to catch the exceptions. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
Extra left bits in AndData are stripped. The caller must either guarantee\r
that Index and the data written is valid, or the caller must set up exception\r
handlers to catch the exceptions. This function is only available on IA-32\r
- and X64.\r
+ and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
64-bit MSR.\r
\r
Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by\r
- a bitwise inclusive OR between the read result and the value specified by\r
+ a bitwise OR between the read result and the value specified by\r
AndData, and writes the result to the 64-bit MSR specified by Index. The\r
value written to the MSR is returned. Extra left bits in both AndData and\r
OrData are stripped. The caller must either guarantee that Index and the data\r
written is valid, or the caller must set up exception handlers to catch the\r
- exceptions. This function is only available on IA-32 and X64.\r
+ exceptions. This function is only available on IA-32 and x64.\r
\r
If StartBit is greater than 63, then ASSERT().\r
If EndBit is greater than 63, then ASSERT().\r
Reads the current value of the EFLAGS register.\r
\r
Reads and returns the current value of the EFLAGS register. This function is\r
- only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a\r
- 64-bit value on X64.\r
+ only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a\r
+ 64-bit value on x64.\r
\r
- @return EFLAGS on IA-32 or RFLAGS on X64.\r
+ @return EFLAGS on IA-32 or RFLAGS on x64.\r
\r
**/\r
UINTN\r
Reads the current value of the Control Register 0 (CR0).\r
\r
Reads and returns the current value of CR0. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 0 (CR0).\r
\r
Reads the current value of the Control Register 2 (CR2).\r
\r
Reads and returns the current value of CR2. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 2 (CR2).\r
\r
Reads the current value of the Control Register 3 (CR3).\r
\r
Reads and returns the current value of CR3. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 3 (CR3).\r
\r
Reads the current value of the Control Register 4 (CR4).\r
\r
Reads and returns the current value of CR4. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of the Control Register 4 (CR4).\r
\r
Writes a value to Control Register 0 (CR0).\r
\r
Writes and returns a new value to CR0. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr0 The value to write to CR0.\r
\r
Writes a value to Control Register 2 (CR2).\r
\r
Writes and returns a new value to CR2. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr2 The value to write to CR2.\r
\r
Writes a value to Control Register 3 (CR3).\r
\r
Writes and returns a new value to CR3. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr3 The value to write to CR3.\r
\r
Writes a value to Control Register 4 (CR4).\r
\r
Writes and returns a new value to CR4. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Cr4 The value to write to CR4.\r
\r
Reads the current value of Debug Register 0 (DR0).\r
\r
Reads and returns the current value of DR0. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 0 (DR0).\r
\r
Reads the current value of Debug Register 1 (DR1).\r
\r
Reads and returns the current value of DR1. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 1 (DR1).\r
\r
Reads the current value of Debug Register 2 (DR2).\r
\r
Reads and returns the current value of DR2. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 2 (DR2).\r
\r
Reads the current value of Debug Register 3 (DR3).\r
\r
Reads and returns the current value of DR3. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 3 (DR3).\r
\r
Reads the current value of Debug Register 4 (DR4).\r
\r
Reads and returns the current value of DR4. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 4 (DR4).\r
\r
Reads the current value of Debug Register 5 (DR5).\r
\r
Reads and returns the current value of DR5. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 5 (DR5).\r
\r
Reads the current value of Debug Register 6 (DR6).\r
\r
Reads and returns the current value of DR6. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 6 (DR6).\r
\r
Reads the current value of Debug Register 7 (DR7).\r
\r
Reads and returns the current value of DR7. This function is only available\r
- on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
- X64.\r
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ x64.\r
\r
@return The value of Debug Register 7 (DR7).\r
\r
Writes a value to Debug Register 0 (DR0).\r
\r
Writes and returns a new value to DR0. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr0 The value to write to Dr0.\r
\r
Writes a value to Debug Register 1 (DR1).\r
\r
Writes and returns a new value to DR1. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr1 The value to write to Dr1.\r
\r
Writes a value to Debug Register 2 (DR2).\r
\r
Writes and returns a new value to DR2. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr2 The value to write to Dr2.\r
\r
Writes a value to Debug Register 3 (DR3).\r
\r
Writes and returns a new value to DR3. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr3 The value to write to Dr3.\r
\r
Writes a value to Debug Register 4 (DR4).\r
\r
Writes and returns a new value to DR4. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr4 The value to write to Dr4.\r
\r
Writes a value to Debug Register 5 (DR5).\r
\r
Writes and returns a new value to DR5. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr5 The value to write to Dr5.\r
\r
Writes a value to Debug Register 6 (DR6).\r
\r
Writes and returns a new value to DR6. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr6 The value to write to Dr6.\r
\r
Writes a value to Debug Register 7 (DR7).\r
\r
Writes and returns a new value to DR7. This function is only available on\r
- IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
\r
@param Dr7 The value to write to Dr7.\r
\r
Reads the current value of Code Segment Register (CS).\r
\r
Reads and returns the current value of CS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of CS.\r
\r
Reads the current value of Data Segment Register (DS).\r
\r
Reads and returns the current value of DS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of DS.\r
\r
Reads the current value of Extra Segment Register (ES).\r
\r
Reads and returns the current value of ES. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of ES.\r
\r
Reads the current value of FS Data Segment Register (FS).\r
\r
Reads and returns the current value of FS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of FS.\r
\r
Reads the current value of GS Data Segment Register (GS).\r
\r
Reads and returns the current value of GS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of GS.\r
\r
Reads the current value of Stack Segment Register (SS).\r
\r
Reads and returns the current value of SS. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of SS.\r
\r
Reads the current value of Task Register (TR).\r
\r
Reads and returns the current value of TR. This function is only available on\r
- IA-32 and X64.\r
+ IA-32 and x64.\r
\r
@return The current value of TR.\r
\r
Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
\r
Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
If Gdtr is NULL, then ASSERT().\r
\r
Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
\r
Writes and the current GDTR descriptor specified by Gdtr. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
If Gdtr is NULL, then ASSERT().\r
\r
Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
\r
Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
- function is only available on IA-32 and X64.\r
+ function is only available on IA-32 and x64.\r
\r
If Idtr is NULL, then ASSERT().\r
\r
Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
\r
Writes the current IDTR descriptor and returns it in Idtr. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
If Idtr is NULL, then ASSERT().\r
\r
Reads the current Local Descriptor Table Register(LDTR) selector.\r
\r
Reads and returns the current 16-bit LDTR descriptor value. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
@return The current selector of LDT.\r
\r
Writes the current Local Descriptor Table Register (LDTR) selector.\r
\r
Writes and the current LDTR descriptor specified by Ldtr. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
@param Ldtr 16-bit LDTR selector value.\r
\r
\r
Saves the current floating point/SSE/SSE2 state to the buffer specified by\r
Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
- available on IA-32 and X64.\r
+ available on IA-32 and x64.\r
\r
If Buffer is NULL, then ASSERT().\r
If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r
\r
Restores the current floating point/SSE/SSE2 state from the buffer specified\r
by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
- only available on IA-32 and X64.\r
+ only available on IA-32 and x64.\r
\r
If Buffer is NULL, then ASSERT().\r
If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r
Reads the current value of 64-bit MMX Register #0 (MM0).\r
\r
Reads and returns the current value of MM0. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM0.\r
\r
Reads the current value of 64-bit MMX Register #1 (MM1).\r
\r
Reads and returns the current value of MM1. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM1.\r
\r
Reads the current value of 64-bit MMX Register #2 (MM2).\r
\r
Reads and returns the current value of MM2. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM2.\r
\r
Reads the current value of 64-bit MMX Register #3 (MM3).\r
\r
Reads and returns the current value of MM3. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM3.\r
\r
Reads the current value of 64-bit MMX Register #4 (MM4).\r
\r
Reads and returns the current value of MM4. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM4.\r
\r
Reads the current value of 64-bit MMX Register #5 (MM5).\r
\r
Reads and returns the current value of MM5. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM5.\r
\r
Reads the current value of 64-bit MMX Register #6 (MM6).\r
\r
Reads and returns the current value of MM6. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM6.\r
\r
Reads the current value of 64-bit MMX Register #7 (MM7).\r
\r
Reads and returns the current value of MM7. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of MM7.\r
\r
Writes the current value of 64-bit MMX Register #0 (MM0).\r
\r
Writes the current value of MM0. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM0.\r
\r
Writes the current value of 64-bit MMX Register #1 (MM1).\r
\r
Writes the current value of MM1. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM1.\r
\r
Writes the current value of 64-bit MMX Register #2 (MM2).\r
\r
Writes the current value of MM2. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM2.\r
\r
Writes the current value of 64-bit MMX Register #3 (MM3).\r
\r
Writes the current value of MM3. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM3.\r
\r
Writes the current value of 64-bit MMX Register #4 (MM4).\r
\r
Writes the current value of MM4. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM4.\r
\r
Writes the current value of 64-bit MMX Register #5 (MM5).\r
\r
Writes the current value of MM5. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM5.\r
\r
Writes the current value of 64-bit MMX Register #6 (MM6).\r
\r
Writes the current value of MM6. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM6.\r
\r
Writes the current value of 64-bit MMX Register #7 (MM7).\r
\r
Writes the current value of MM7. This function is only available on IA32 and\r
- X64.\r
+ x64.\r
\r
@param Value The 64-bit value to write to MM7.\r
\r
Reads the current value of Time Stamp Counter (TSC).\r
\r
Reads and returns the current value of TSC. This function is only available\r
- on IA-32 and X64.\r
+ on IA-32 and x64.\r
\r
@return The current value of TSC\r
\r
Reads the current value of a Performance Counter (PMC).\r
\r
Reads and returns the current value of performance counter specified by\r
- Index. This function is only available on IA-32 and X64.\r
+ Index. This function is only available on IA-32 and x64.\r
\r
@param Index The 32-bit Performance Counter index to read.\r
\r
Sets up a monitor buffer that is used by AsmMwait().\r
\r
Executes a MONITOR instruction with the register state specified by Eax, Ecx\r
- and Edx. Returns Eax. This function is only available on IA-32 and X64.\r
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.\r
\r
@param Eax The value to load into EAX or RAX before executing the MONITOR\r
instruction.\r
Executes an MWAIT instruction.\r
\r
Executes an MWAIT instruction with the register state specified by Eax and\r
- Ecx. Returns Eax. This function is only available on IA-32 and X64.\r
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.\r
\r
@param Eax The value to load into EAX or RAX before executing the MONITOR\r
instruction.\r
Executes a WBINVD instruction.\r
\r
Executes a WBINVD instruction. This function is only available on IA-32 and\r
- X64.\r
+ x64.\r
\r
**/\r
VOID\r
Executes a INVD instruction.\r
\r
Executes a INVD instruction. This function is only available on IA-32 and\r
- X64.\r
+ x64.\r
\r
**/\r
VOID\r
coherency domain of the CPU.\r
\r
Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
- This function is only available on IA-32 and X64.\r
+ This function is only available on IA-32 and x64.\r
\r
@param LinearAddress The address of the cache line to flush. If the CPU is\r
in a physical addressing mode, then LinearAddress is a\r
\r
Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r
mode. This function assumes the current execution mode is 64-paging mode.\r
- This function is only available on X64. After the 64-bit paging mode is\r
+ This function is only available on x64. After the 64-bit paging mode is\r
disabled, control is transferred to the function specified by EntryPoint\r
using the new stack specified by NewStack and passing in the parameters\r
specified by Context1 and Context2. Context1 and Context2 are optional and\r
in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r
then the actual minimum stack size is ExtraStackSize plus the maximum number\r
of bytes that need to be passed to the 16-bit real mode code.\r
-\r
+ \r
If RealModeBufferSize is NULL, then ASSERT().\r
If ExtraStackSize is NULL, then ASSERT().\r
\r
Prepares all structures a code required to use AsmThunk16().\r
\r
Prepares all structures and code required to use AsmThunk16().\r
+ \r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
\r
If ThunkContext is NULL, then ASSERT().\r
\r
If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in \r
ThunkAttributes, then ASSERT().\r
\r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
+\r
@param ThunkContext A pointer to the context structure that describes the\r
16-bit real mode code to call.\r
\r
real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\r
once and AsmThunk16() can be called for each 16-bit real mode thunk.\r
\r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
+\r
See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\r
\r
@param ThunkContext A pointer to the context structure that describes the\r
projects / mirror_edk2.git / blobdiff