/** @file\r
- Functions accessing PCI configuration registers on any supported PCI segment\r
-\r
- Copyright (c) 2006, Intel Corporation\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r
+ \r
+ The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r
+ registers on PCI root bridges on any supported PCI segment. These library services take a single \r
+ address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r
+ The layout of this address parameter is as follows:\r
+ \r
+ PCI Register: Bits 0..11\r
+ PCI Function Bits 12..14\r
+ PCI Device Bits 15..19\r
+ PCI Bus Bits 20..27\r
+ Reserved Bits 28..31. Must be 0.\r
+ PCI Segment Bits 32..47\r
+ Reserved Bits 48..63. Must be 0.\r
+ \r
+ | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r
+ 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r
+\r
+ These functions perform PCI configuration cycles using the default PCI configuration access \r
+ method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r
+ may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r
+ access method. Modules will typically use the PCI Segment Library for its PCI configuration \r
+ accesses when PCI Segments other than Segment #0 must be accessed. \r
+\r
+Copyright (c) 2006 - 2008, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
Reads and returns the 8-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
EFIAPI\r
PciSegmentRead8 (\r
IN UINT64 Address\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes an 8-bit PCI configuration register.\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
PciSegmentWrite8 (\r
IN UINT64 Address,\r
IN UINT8 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
PciSegmentOr8 (\r
IN UINT64 Address,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
\r
PciSegmentAnd8 (\r
IN UINT64 Address,\r
IN UINT8 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
IN UINT64 Address,\r
IN UINT8 AndData,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field of a PCI configuration register.\r
Reads the bit field in an 8-bit PCI configuration register.\r
The bit field is specified by the StartBit and the EndBit.\r
The value of the bit field is returned.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
IN UINT64 Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a bit field to a PCI configuration register.\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT8 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads the 8-bit PCI configuration register specified by Address,\r
performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
and writes the result to the 8-bit PCI configuration register specified by Address. \r
+ \r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
Extra left bits in OrData are stripped.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT8 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
Extra left bits in AndData are stripped.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
IN UINTN EndBit,\r
IN UINT8 AndData,\r
IN UINT8 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a 16-bit PCI configuration register.\r
\r
Reads and returns the 16-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
EFIAPI\r
PciSegmentRead16 (\r
IN UINT64 Address\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a 16-bit PCI configuration register.\r
\r
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ \r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
PciSegmentWrite16 (\r
IN UINT64 Address,\r
IN UINT16 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param OrData The value to OR with the PCI configuration register.\r
PciSegmentOr16 (\r
IN UINT64 Address,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
-\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ \r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
\r
PciSegmentAnd16 (\r
IN UINT64 Address,\r
IN UINT16 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
IN UINT64 Address,\r
IN UINT16 AndData,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field of a PCI configuration register.\r
Reads the bit field in a 16-bit PCI configuration register.\r
The bit field is specified by the StartBit and the EndBit.\r
The value of the bit field is returned.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINT64 Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a bit field to a PCI configuration register.\r
The bit field is specified by the StartBit and the EndBit.\r
All other bits in the destination PCI configuration register are preserved.\r
The new value of the 16-bit register is returned.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT16 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads the 16-bit PCI configuration register specified by Address,\r
performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address. \r
\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
The ordinal of the least significant bit in a byte is bit 0.\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
Extra left bits in OrData are stripped.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT16 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
Extra left bits in AndData are stripped.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT()..\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINTN EndBit,\r
IN UINT16 AndData,\r
IN UINT16 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a 32-bit PCI configuration register.\r
\r
Reads and returns the 32-bit PCI configuration register specified by Address.\r
This function must guarantee that all PCI read and write operations are serialized.\r
- If any reserved bits in Address are set, then ASSERT().\r
\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
@return The 32-bit PCI configuration register specified by Address.\r
EFIAPI\r
PciSegmentRead32 (\r
IN UINT64 Address\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a 32-bit PCI configuration register.\r
\r
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ \r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
PciSegmentWrite32 (\r
IN UINT64 Address,\r
IN UINT32 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param OrData The value to OR with the PCI configuration register.\r
PciSegmentOr32 (\r
IN UINT64 Address,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
\r
PciSegmentAnd32 (\r
IN UINT64 Address,\r
IN UINT32 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param Andata The value to AND with the PCI configuration register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
@param OrData The value to OR with the PCI configuration register.\r
\r
@return The value written to the PCI configuration register.\r
IN UINT64 Address,\r
IN UINT32 AndData,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field of a PCI configuration register.\r
Reads the bit field in a 32-bit PCI configuration register.\r
The bit field is specified by the StartBit and the EndBit.\r
The value of the bit field is returned.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINT64 Address,\r
IN UINTN StartBit,\r
IN UINTN EndBit\r
- )\r
-;\r
+ );\r
\r
/**\r
Writes a bit field to a PCI configuration register.\r
The bit field is specified by the StartBit and the EndBit.\r
All other bits in the destination PCI configuration register are preserved.\r
The new value of the 32-bit register is returned.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT32 Value\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads the 32-bit PCI configuration register specified by Address,\r
performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
and writes the result to the 32-bit PCI configuration register specified by Address. \r
-\r
+ \r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ \r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
The ordinal of the least significant bit in a byte is bit 0.\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
Extra left bits in OrData are stripped.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINTN StartBit,\r
IN UINTN EndBit,\r
IN UINT32 AndData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
Extra left bits in AndData are stripped.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
IN UINTN EndBit,\r
IN UINT32 AndData,\r
IN UINT32 OrData\r
- )\r
-;\r
+ );\r
\r
/**\r
Reads a range of PCI configuration registers into a caller supplied buffer.\r
and Size into the buffer specified by Buffer.\r
This function only allows the PCI configuration registers from a single PCI function to be read.\r
Size is returned.\r
+ \r
If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r
- If Buffer is NULL, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer receiving the data read.\r
\r
- @return The paramter of Size.\r
+ @return The parameter of Size.\r
\r
**/\r
UINTN\r
IN UINT64 StartAddress,\r
IN UINTN Size,\r
OUT VOID *Buffer\r
- )\r
-;\r
+ );\r
\r
/**\r
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r
and Size from the buffer specified by Buffer.\r
This function only allows the PCI configuration registers from a single PCI function to be written.\r
Size is returned.\r
+ \r
If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer containing the data to write.\r
\r
- @return The paramter of Size.\r
+ @return The parameter of Size.\r
\r
**/\r
UINTN\r
IN UINT64 StartAddress,\r
IN UINTN Size,\r
IN VOID *Buffer\r
- )\r
-;\r
+ );\r
\r
#endif\r
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