/// Processor exception to be hooked.\r
/// All exception types for IA32, X64, Itanium and EBC processors are defined.\r
///\r
-typedef INTN EFI_EXCEPTION_TYPE;\r
+typedef INTN EFI_EXCEPTION_TYPE;\r
\r
///\r
/// IA-32 processor exception types.\r
///\r
-#define EXCEPT_IA32_DIVIDE_ERROR 0\r
-#define EXCEPT_IA32_DEBUG 1\r
-#define EXCEPT_IA32_NMI 2\r
-#define EXCEPT_IA32_BREAKPOINT 3\r
-#define EXCEPT_IA32_OVERFLOW 4\r
-#define EXCEPT_IA32_BOUND 5\r
-#define EXCEPT_IA32_INVALID_OPCODE 6\r
-#define EXCEPT_IA32_DOUBLE_FAULT 8\r
-#define EXCEPT_IA32_INVALID_TSS 10\r
-#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
-#define EXCEPT_IA32_STACK_FAULT 12\r
-#define EXCEPT_IA32_GP_FAULT 13\r
-#define EXCEPT_IA32_PAGE_FAULT 14\r
-#define EXCEPT_IA32_FP_ERROR 16\r
-#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
-#define EXCEPT_IA32_MACHINE_CHECK 18\r
-#define EXCEPT_IA32_SIMD 19\r
+#define EXCEPT_IA32_DIVIDE_ERROR 0\r
+#define EXCEPT_IA32_DEBUG 1\r
+#define EXCEPT_IA32_NMI 2\r
+#define EXCEPT_IA32_BREAKPOINT 3\r
+#define EXCEPT_IA32_OVERFLOW 4\r
+#define EXCEPT_IA32_BOUND 5\r
+#define EXCEPT_IA32_INVALID_OPCODE 6\r
+#define EXCEPT_IA32_DOUBLE_FAULT 8\r
+#define EXCEPT_IA32_INVALID_TSS 10\r
+#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
+#define EXCEPT_IA32_STACK_FAULT 12\r
+#define EXCEPT_IA32_GP_FAULT 13\r
+#define EXCEPT_IA32_PAGE_FAULT 14\r
+#define EXCEPT_IA32_FP_ERROR 16\r
+#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
+#define EXCEPT_IA32_MACHINE_CHECK 18\r
+#define EXCEPT_IA32_SIMD 19\r
\r
///\r
/// FXSAVE_STATE.\r
/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
///\r
typedef struct {\r
- UINT16 Fcw;\r
- UINT16 Fsw;\r
- UINT16 Ftw;\r
- UINT16 Opcode;\r
- UINT32 Eip;\r
- UINT16 Cs;\r
- UINT16 Reserved1;\r
- UINT32 DataOffset;\r
- UINT16 Ds;\r
- UINT8 Reserved2[10];\r
- UINT8 St0Mm0[10], Reserved3[6];\r
- UINT8 St1Mm1[10], Reserved4[6];\r
- UINT8 St2Mm2[10], Reserved5[6];\r
- UINT8 St3Mm3[10], Reserved6[6];\r
- UINT8 St4Mm4[10], Reserved7[6];\r
- UINT8 St5Mm5[10], Reserved8[6];\r
- UINT8 St6Mm6[10], Reserved9[6];\r
- UINT8 St7Mm7[10], Reserved10[6];\r
- UINT8 Xmm0[16];\r
- UINT8 Xmm1[16];\r
- UINT8 Xmm2[16];\r
- UINT8 Xmm3[16];\r
- UINT8 Xmm4[16];\r
- UINT8 Xmm5[16];\r
- UINT8 Xmm6[16];\r
- UINT8 Xmm7[16];\r
- UINT8 Reserved11[14 * 16];\r
+ UINT16 Fcw;\r
+ UINT16 Fsw;\r
+ UINT16 Ftw;\r
+ UINT16 Opcode;\r
+ UINT32 Eip;\r
+ UINT16 Cs;\r
+ UINT16 Reserved1;\r
+ UINT32 DataOffset;\r
+ UINT16 Ds;\r
+ UINT8 Reserved2[10];\r
+ UINT8 St0Mm0[10], Reserved3[6];\r
+ UINT8 St1Mm1[10], Reserved4[6];\r
+ UINT8 St2Mm2[10], Reserved5[6];\r
+ UINT8 St3Mm3[10], Reserved6[6];\r
+ UINT8 St4Mm4[10], Reserved7[6];\r
+ UINT8 St5Mm5[10], Reserved8[6];\r
+ UINT8 St6Mm6[10], Reserved9[6];\r
+ UINT8 St7Mm7[10], Reserved10[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
+ UINT8 Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_IA32;\r
\r
///\r
/// IA-32 processor context definition.\r
///\r
typedef struct {\r
- UINT32 ExceptionData;\r
- EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
- UINT32 Dr0;\r
- UINT32 Dr1;\r
- UINT32 Dr2;\r
- UINT32 Dr3;\r
- UINT32 Dr6;\r
- UINT32 Dr7;\r
- UINT32 Cr0;\r
- UINT32 Cr1; /* Reserved */\r
- UINT32 Cr2;\r
- UINT32 Cr3;\r
- UINT32 Cr4;\r
- UINT32 Eflags;\r
- UINT32 Ldtr;\r
- UINT32 Tr;\r
- UINT32 Gdtr[2];\r
- UINT32 Idtr[2];\r
- UINT32 Eip;\r
- UINT32 Gs;\r
- UINT32 Fs;\r
- UINT32 Es;\r
- UINT32 Ds;\r
- UINT32 Cs;\r
- UINT32 Ss;\r
- UINT32 Edi;\r
- UINT32 Esi;\r
- UINT32 Ebp;\r
- UINT32 Esp;\r
- UINT32 Ebx;\r
- UINT32 Edx;\r
- UINT32 Ecx;\r
- UINT32 Eax;\r
+ UINT32 ExceptionData;\r
+ EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
+ UINT32 Dr0;\r
+ UINT32 Dr1;\r
+ UINT32 Dr2;\r
+ UINT32 Dr3;\r
+ UINT32 Dr6;\r
+ UINT32 Dr7;\r
+ UINT32 Cr0;\r
+ UINT32 Cr1; /* Reserved */\r
+ UINT32 Cr2;\r
+ UINT32 Cr3;\r
+ UINT32 Cr4;\r
+ UINT32 Eflags;\r
+ UINT32 Ldtr;\r
+ UINT32 Tr;\r
+ UINT32 Gdtr[2];\r
+ UINT32 Idtr[2];\r
+ UINT32 Eip;\r
+ UINT32 Gs;\r
+ UINT32 Fs;\r
+ UINT32 Es;\r
+ UINT32 Ds;\r
+ UINT32 Cs;\r
+ UINT32 Ss;\r
+ UINT32 Edi;\r
+ UINT32 Esi;\r
+ UINT32 Ebp;\r
+ UINT32 Esp;\r
+ UINT32 Ebx;\r
+ UINT32 Edx;\r
+ UINT32 Ecx;\r
+ UINT32 Eax;\r
} EFI_SYSTEM_CONTEXT_IA32;\r
\r
///\r
/// x64 processor exception types.\r
///\r
-#define EXCEPT_X64_DIVIDE_ERROR 0\r
-#define EXCEPT_X64_DEBUG 1\r
-#define EXCEPT_X64_NMI 2\r
-#define EXCEPT_X64_BREAKPOINT 3\r
-#define EXCEPT_X64_OVERFLOW 4\r
-#define EXCEPT_X64_BOUND 5\r
-#define EXCEPT_X64_INVALID_OPCODE 6\r
-#define EXCEPT_X64_DOUBLE_FAULT 8\r
-#define EXCEPT_X64_INVALID_TSS 10\r
-#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
-#define EXCEPT_X64_STACK_FAULT 12\r
-#define EXCEPT_X64_GP_FAULT 13\r
-#define EXCEPT_X64_PAGE_FAULT 14\r
-#define EXCEPT_X64_FP_ERROR 16\r
-#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
-#define EXCEPT_X64_MACHINE_CHECK 18\r
-#define EXCEPT_X64_SIMD 19\r
+#define EXCEPT_X64_DIVIDE_ERROR 0\r
+#define EXCEPT_X64_DEBUG 1\r
+#define EXCEPT_X64_NMI 2\r
+#define EXCEPT_X64_BREAKPOINT 3\r
+#define EXCEPT_X64_OVERFLOW 4\r
+#define EXCEPT_X64_BOUND 5\r
+#define EXCEPT_X64_INVALID_OPCODE 6\r
+#define EXCEPT_X64_DOUBLE_FAULT 8\r
+#define EXCEPT_X64_INVALID_TSS 10\r
+#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
+#define EXCEPT_X64_STACK_FAULT 12\r
+#define EXCEPT_X64_GP_FAULT 13\r
+#define EXCEPT_X64_PAGE_FAULT 14\r
+#define EXCEPT_X64_FP_ERROR 16\r
+#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
+#define EXCEPT_X64_MACHINE_CHECK 18\r
+#define EXCEPT_X64_SIMD 19\r
\r
///\r
/// FXSAVE_STATE.\r
/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
///\r
typedef struct {\r
- UINT16 Fcw;\r
- UINT16 Fsw;\r
- UINT16 Ftw;\r
- UINT16 Opcode;\r
- UINT64 Rip;\r
- UINT64 DataOffset;\r
- UINT8 Reserved1[8];\r
- UINT8 St0Mm0[10], Reserved2[6];\r
- UINT8 St1Mm1[10], Reserved3[6];\r
- UINT8 St2Mm2[10], Reserved4[6];\r
- UINT8 St3Mm3[10], Reserved5[6];\r
- UINT8 St4Mm4[10], Reserved6[6];\r
- UINT8 St5Mm5[10], Reserved7[6];\r
- UINT8 St6Mm6[10], Reserved8[6];\r
- UINT8 St7Mm7[10], Reserved9[6];\r
- UINT8 Xmm0[16];\r
- UINT8 Xmm1[16];\r
- UINT8 Xmm2[16];\r
- UINT8 Xmm3[16];\r
- UINT8 Xmm4[16];\r
- UINT8 Xmm5[16];\r
- UINT8 Xmm6[16];\r
- UINT8 Xmm7[16];\r
+ UINT16 Fcw;\r
+ UINT16 Fsw;\r
+ UINT16 Ftw;\r
+ UINT16 Opcode;\r
+ UINT64 Rip;\r
+ UINT64 DataOffset;\r
+ UINT8 Reserved1[8];\r
+ UINT8 St0Mm0[10], Reserved2[6];\r
+ UINT8 St1Mm1[10], Reserved3[6];\r
+ UINT8 St2Mm2[10], Reserved4[6];\r
+ UINT8 St3Mm3[10], Reserved5[6];\r
+ UINT8 St4Mm4[10], Reserved6[6];\r
+ UINT8 St5Mm5[10], Reserved7[6];\r
+ UINT8 St6Mm6[10], Reserved8[6];\r
+ UINT8 St7Mm7[10], Reserved9[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
//\r
// NOTE: UEFI 2.0 spec definition as follows.\r
//\r
- UINT8 Reserved11[14 * 16];\r
+ UINT8 Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_X64;\r
\r
///\r
/// x64 processor context definition.\r
///\r
typedef struct {\r
- UINT64 ExceptionData;\r
- EFI_FX_SAVE_STATE_X64 FxSaveState;\r
- UINT64 Dr0;\r
- UINT64 Dr1;\r
- UINT64 Dr2;\r
- UINT64 Dr3;\r
- UINT64 Dr6;\r
- UINT64 Dr7;\r
- UINT64 Cr0;\r
- UINT64 Cr1; /* Reserved */\r
- UINT64 Cr2;\r
- UINT64 Cr3;\r
- UINT64 Cr4;\r
- UINT64 Cr8;\r
- UINT64 Rflags;\r
- UINT64 Ldtr;\r
- UINT64 Tr;\r
- UINT64 Gdtr[2];\r
- UINT64 Idtr[2];\r
- UINT64 Rip;\r
- UINT64 Gs;\r
- UINT64 Fs;\r
- UINT64 Es;\r
- UINT64 Ds;\r
- UINT64 Cs;\r
- UINT64 Ss;\r
- UINT64 Rdi;\r
- UINT64 Rsi;\r
- UINT64 Rbp;\r
- UINT64 Rsp;\r
- UINT64 Rbx;\r
- UINT64 Rdx;\r
- UINT64 Rcx;\r
- UINT64 Rax;\r
- UINT64 R8;\r
- UINT64 R9;\r
- UINT64 R10;\r
- UINT64 R11;\r
- UINT64 R12;\r
- UINT64 R13;\r
- UINT64 R14;\r
- UINT64 R15;\r
+ UINT64 ExceptionData;\r
+ EFI_FX_SAVE_STATE_X64 FxSaveState;\r
+ UINT64 Dr0;\r
+ UINT64 Dr1;\r
+ UINT64 Dr2;\r
+ UINT64 Dr3;\r
+ UINT64 Dr6;\r
+ UINT64 Dr7;\r
+ UINT64 Cr0;\r
+ UINT64 Cr1; /* Reserved */\r
+ UINT64 Cr2;\r
+ UINT64 Cr3;\r
+ UINT64 Cr4;\r
+ UINT64 Cr8;\r
+ UINT64 Rflags;\r
+ UINT64 Ldtr;\r
+ UINT64 Tr;\r
+ UINT64 Gdtr[2];\r
+ UINT64 Idtr[2];\r
+ UINT64 Rip;\r
+ UINT64 Gs;\r
+ UINT64 Fs;\r
+ UINT64 Es;\r
+ UINT64 Ds;\r
+ UINT64 Cs;\r
+ UINT64 Ss;\r
+ UINT64 Rdi;\r
+ UINT64 Rsi;\r
+ UINT64 Rbp;\r
+ UINT64 Rsp;\r
+ UINT64 Rbx;\r
+ UINT64 Rdx;\r
+ UINT64 Rcx;\r
+ UINT64 Rax;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
} EFI_SYSTEM_CONTEXT_X64;\r
\r
///\r
/// Itanium Processor Family Exception types.\r
///\r
-#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
-#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
-#define EXCEPT_IPF_DATA_TLB 2\r
-#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
-#define EXCEPT_IPF_ALT_DATA_TLB 4\r
-#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
-#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
-#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
-#define EXCEPT_IPF_DIRTY_BIT 8\r
-#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
-#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
-#define EXCEPT_IPF_BREAKPOINT 11\r
-#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
+#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
+#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
+#define EXCEPT_IPF_DATA_TLB 2\r
+#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
+#define EXCEPT_IPF_ALT_DATA_TLB 4\r
+#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
+#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
+#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
+#define EXCEPT_IPF_DIRTY_BIT 8\r
+#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
+#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
+#define EXCEPT_IPF_BREAKPOINT 11\r
+#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
//\r
// 13 - 19 reserved\r
//\r
//\r
// 37 - 44 reserved\r
//\r
-#define EXCEPT_IPF_IA32_EXCEPTION 45\r
-#define EXCEPT_IPF_IA32_INTERCEPT 46\r
-#define EXCEPT_IPF_IA32_INTERRUPT 47\r
+#define EXCEPT_IPF_IA32_EXCEPTION 45\r
+#define EXCEPT_IPF_IA32_INTERCEPT 46\r
+#define EXCEPT_IPF_IA32_INTERRUPT 47\r
\r
///\r
/// IPF processor context definition.\r
// The first reserved field is necessary to preserve alignment for the correct\r
// bits in UNAT and to insure F2 is 16 byte aligned.\r
//\r
- UINT64 Reserved;\r
- UINT64 R1;\r
- UINT64 R2;\r
- UINT64 R3;\r
- UINT64 R4;\r
- UINT64 R5;\r
- UINT64 R6;\r
- UINT64 R7;\r
- UINT64 R8;\r
- UINT64 R9;\r
- UINT64 R10;\r
- UINT64 R11;\r
- UINT64 R12;\r
- UINT64 R13;\r
- UINT64 R14;\r
- UINT64 R15;\r
- UINT64 R16;\r
- UINT64 R17;\r
- UINT64 R18;\r
- UINT64 R19;\r
- UINT64 R20;\r
- UINT64 R21;\r
- UINT64 R22;\r
- UINT64 R23;\r
- UINT64 R24;\r
- UINT64 R25;\r
- UINT64 R26;\r
- UINT64 R27;\r
- UINT64 R28;\r
- UINT64 R29;\r
- UINT64 R30;\r
- UINT64 R31;\r
-\r
- UINT64 F2[2];\r
- UINT64 F3[2];\r
- UINT64 F4[2];\r
- UINT64 F5[2];\r
- UINT64 F6[2];\r
- UINT64 F7[2];\r
- UINT64 F8[2];\r
- UINT64 F9[2];\r
- UINT64 F10[2];\r
- UINT64 F11[2];\r
- UINT64 F12[2];\r
- UINT64 F13[2];\r
- UINT64 F14[2];\r
- UINT64 F15[2];\r
- UINT64 F16[2];\r
- UINT64 F17[2];\r
- UINT64 F18[2];\r
- UINT64 F19[2];\r
- UINT64 F20[2];\r
- UINT64 F21[2];\r
- UINT64 F22[2];\r
- UINT64 F23[2];\r
- UINT64 F24[2];\r
- UINT64 F25[2];\r
- UINT64 F26[2];\r
- UINT64 F27[2];\r
- UINT64 F28[2];\r
- UINT64 F29[2];\r
- UINT64 F30[2];\r
- UINT64 F31[2];\r
-\r
- UINT64 Pr;\r
-\r
- UINT64 B0;\r
- UINT64 B1;\r
- UINT64 B2;\r
- UINT64 B3;\r
- UINT64 B4;\r
- UINT64 B5;\r
- UINT64 B6;\r
- UINT64 B7;\r
+ UINT64 Reserved;\r
+ UINT64 R1;\r
+ UINT64 R2;\r
+ UINT64 R3;\r
+ UINT64 R4;\r
+ UINT64 R5;\r
+ UINT64 R6;\r
+ UINT64 R7;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
+ UINT64 R16;\r
+ UINT64 R17;\r
+ UINT64 R18;\r
+ UINT64 R19;\r
+ UINT64 R20;\r
+ UINT64 R21;\r
+ UINT64 R22;\r
+ UINT64 R23;\r
+ UINT64 R24;\r
+ UINT64 R25;\r
+ UINT64 R26;\r
+ UINT64 R27;\r
+ UINT64 R28;\r
+ UINT64 R29;\r
+ UINT64 R30;\r
+ UINT64 R31;\r
+\r
+ UINT64 F2[2];\r
+ UINT64 F3[2];\r
+ UINT64 F4[2];\r
+ UINT64 F5[2];\r
+ UINT64 F6[2];\r
+ UINT64 F7[2];\r
+ UINT64 F8[2];\r
+ UINT64 F9[2];\r
+ UINT64 F10[2];\r
+ UINT64 F11[2];\r
+ UINT64 F12[2];\r
+ UINT64 F13[2];\r
+ UINT64 F14[2];\r
+ UINT64 F15[2];\r
+ UINT64 F16[2];\r
+ UINT64 F17[2];\r
+ UINT64 F18[2];\r
+ UINT64 F19[2];\r
+ UINT64 F20[2];\r
+ UINT64 F21[2];\r
+ UINT64 F22[2];\r
+ UINT64 F23[2];\r
+ UINT64 F24[2];\r
+ UINT64 F25[2];\r
+ UINT64 F26[2];\r
+ UINT64 F27[2];\r
+ UINT64 F28[2];\r
+ UINT64 F29[2];\r
+ UINT64 F30[2];\r
+ UINT64 F31[2];\r
+\r
+ UINT64 Pr;\r
+\r
+ UINT64 B0;\r
+ UINT64 B1;\r
+ UINT64 B2;\r
+ UINT64 B3;\r
+ UINT64 B4;\r
+ UINT64 B5;\r
+ UINT64 B6;\r
+ UINT64 B7;\r
\r
//\r
// application registers\r
//\r
- UINT64 ArRsc;\r
- UINT64 ArBsp;\r
- UINT64 ArBspstore;\r
- UINT64 ArRnat;\r
+ UINT64 ArRsc;\r
+ UINT64 ArBsp;\r
+ UINT64 ArBspstore;\r
+ UINT64 ArRnat;\r
\r
- UINT64 ArFcr;\r
+ UINT64 ArFcr;\r
\r
- UINT64 ArEflag;\r
- UINT64 ArCsd;\r
- UINT64 ArSsd;\r
- UINT64 ArCflg;\r
- UINT64 ArFsr;\r
- UINT64 ArFir;\r
- UINT64 ArFdr;\r
+ UINT64 ArEflag;\r
+ UINT64 ArCsd;\r
+ UINT64 ArSsd;\r
+ UINT64 ArCflg;\r
+ UINT64 ArFsr;\r
+ UINT64 ArFir;\r
+ UINT64 ArFdr;\r
\r
- UINT64 ArCcv;\r
+ UINT64 ArCcv;\r
\r
- UINT64 ArUnat;\r
+ UINT64 ArUnat;\r
\r
- UINT64 ArFpsr;\r
+ UINT64 ArFpsr;\r
\r
- UINT64 ArPfs;\r
- UINT64 ArLc;\r
- UINT64 ArEc;\r
+ UINT64 ArPfs;\r
+ UINT64 ArLc;\r
+ UINT64 ArEc;\r
\r
//\r
// control registers\r
//\r
- UINT64 CrDcr;\r
- UINT64 CrItm;\r
- UINT64 CrIva;\r
- UINT64 CrPta;\r
- UINT64 CrIpsr;\r
- UINT64 CrIsr;\r
- UINT64 CrIip;\r
- UINT64 CrIfa;\r
- UINT64 CrItir;\r
- UINT64 CrIipa;\r
- UINT64 CrIfs;\r
- UINT64 CrIim;\r
- UINT64 CrIha;\r
+ UINT64 CrDcr;\r
+ UINT64 CrItm;\r
+ UINT64 CrIva;\r
+ UINT64 CrPta;\r
+ UINT64 CrIpsr;\r
+ UINT64 CrIsr;\r
+ UINT64 CrIip;\r
+ UINT64 CrIfa;\r
+ UINT64 CrItir;\r
+ UINT64 CrIipa;\r
+ UINT64 CrIfs;\r
+ UINT64 CrIim;\r
+ UINT64 CrIha;\r
\r
//\r
// debug registers\r
//\r
- UINT64 Dbr0;\r
- UINT64 Dbr1;\r
- UINT64 Dbr2;\r
- UINT64 Dbr3;\r
- UINT64 Dbr4;\r
- UINT64 Dbr5;\r
- UINT64 Dbr6;\r
- UINT64 Dbr7;\r
-\r
- UINT64 Ibr0;\r
- UINT64 Ibr1;\r
- UINT64 Ibr2;\r
- UINT64 Ibr3;\r
- UINT64 Ibr4;\r
- UINT64 Ibr5;\r
- UINT64 Ibr6;\r
- UINT64 Ibr7;\r
+ UINT64 Dbr0;\r
+ UINT64 Dbr1;\r
+ UINT64 Dbr2;\r
+ UINT64 Dbr3;\r
+ UINT64 Dbr4;\r
+ UINT64 Dbr5;\r
+ UINT64 Dbr6;\r
+ UINT64 Dbr7;\r
+\r
+ UINT64 Ibr0;\r
+ UINT64 Ibr1;\r
+ UINT64 Ibr2;\r
+ UINT64 Ibr3;\r
+ UINT64 Ibr4;\r
+ UINT64 Ibr5;\r
+ UINT64 Ibr6;\r
+ UINT64 Ibr7;\r
\r
//\r
// virtual registers - nat bits for R1-R31\r
//\r
- UINT64 IntNat;\r
-\r
+ UINT64 IntNat;\r
} EFI_SYSTEM_CONTEXT_IPF;\r
\r
///\r
/// EBC processor exception types.\r
///\r
-#define EXCEPT_EBC_UNDEFINED 0\r
-#define EXCEPT_EBC_DIVIDE_ERROR 1\r
-#define EXCEPT_EBC_DEBUG 2\r
-#define EXCEPT_EBC_BREAKPOINT 3\r
-#define EXCEPT_EBC_OVERFLOW 4\r
-#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
-#define EXCEPT_EBC_STACK_FAULT 6\r
-#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
-#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
-#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
-#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
+#define EXCEPT_EBC_UNDEFINED 0\r
+#define EXCEPT_EBC_DIVIDE_ERROR 1\r
+#define EXCEPT_EBC_DEBUG 2\r
+#define EXCEPT_EBC_BREAKPOINT 3\r
+#define EXCEPT_EBC_OVERFLOW 4\r
+#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
+#define EXCEPT_EBC_STACK_FAULT 6\r
+#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
+#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
+#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
+#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
///\r
/// For coding convenience, define the maximum valid EBC exception.\r
///\r
-#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
+#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
\r
///\r
/// EBC processor context definition.\r
///\r
typedef struct {\r
- UINT64 R0;\r
- UINT64 R1;\r
- UINT64 R2;\r
- UINT64 R3;\r
- UINT64 R4;\r
- UINT64 R5;\r
- UINT64 R6;\r
- UINT64 R7;\r
- UINT64 Flags;\r
- UINT64 ControlFlags;\r
- UINT64 Ip;\r
+ UINT64 R0;\r
+ UINT64 R1;\r
+ UINT64 R2;\r
+ UINT64 R3;\r
+ UINT64 R4;\r
+ UINT64 R5;\r
+ UINT64 R6;\r
+ UINT64 R7;\r
+ UINT64 Flags;\r
+ UINT64 ControlFlags;\r
+ UINT64 Ip;\r
} EFI_SYSTEM_CONTEXT_EBC;\r
\r
-\r
-\r
///\r
/// ARM processor exception types.\r
///\r
-#define EXCEPT_ARM_RESET 0\r
-#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
-#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
-#define EXCEPT_ARM_PREFETCH_ABORT 3\r
-#define EXCEPT_ARM_DATA_ABORT 4\r
-#define EXCEPT_ARM_RESERVED 5\r
-#define EXCEPT_ARM_IRQ 6\r
-#define EXCEPT_ARM_FIQ 7\r
+#define EXCEPT_ARM_RESET 0\r
+#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
+#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
+#define EXCEPT_ARM_PREFETCH_ABORT 3\r
+#define EXCEPT_ARM_DATA_ABORT 4\r
+#define EXCEPT_ARM_RESERVED 5\r
+#define EXCEPT_ARM_IRQ 6\r
+#define EXCEPT_ARM_FIQ 7\r
\r
///\r
/// For coding convenience, define the maximum valid ARM exception.\r
///\r
-#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
+#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
\r
///\r
/// ARM processor context definition.\r
///\r
typedef struct {\r
- UINT32 R0;\r
- UINT32 R1;\r
- UINT32 R2;\r
- UINT32 R3;\r
- UINT32 R4;\r
- UINT32 R5;\r
- UINT32 R6;\r
- UINT32 R7;\r
- UINT32 R8;\r
- UINT32 R9;\r
- UINT32 R10;\r
- UINT32 R11;\r
- UINT32 R12;\r
- UINT32 SP;\r
- UINT32 LR;\r
- UINT32 PC;\r
- UINT32 CPSR;\r
- UINT32 DFSR;\r
- UINT32 DFAR;\r
- UINT32 IFSR;\r
- UINT32 IFAR;\r
+ UINT32 R0;\r
+ UINT32 R1;\r
+ UINT32 R2;\r
+ UINT32 R3;\r
+ UINT32 R4;\r
+ UINT32 R5;\r
+ UINT32 R6;\r
+ UINT32 R7;\r
+ UINT32 R8;\r
+ UINT32 R9;\r
+ UINT32 R10;\r
+ UINT32 R11;\r
+ UINT32 R12;\r
+ UINT32 SP;\r
+ UINT32 LR;\r
+ UINT32 PC;\r
+ UINT32 CPSR;\r
+ UINT32 DFSR;\r
+ UINT32 DFAR;\r
+ UINT32 IFSR;\r
+ UINT32 IFAR;\r
} EFI_SYSTEM_CONTEXT_ARM;\r
\r
-\r
///\r
/// AARCH64 processor exception types.\r
///\r
-#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
-#define EXCEPT_AARCH64_IRQ 1\r
-#define EXCEPT_AARCH64_FIQ 2\r
-#define EXCEPT_AARCH64_SERROR 3\r
+#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
+#define EXCEPT_AARCH64_IRQ 1\r
+#define EXCEPT_AARCH64_FIQ 2\r
+#define EXCEPT_AARCH64_SERROR 3\r
\r
///\r
/// For coding convenience, define the maximum valid ARM exception.\r
///\r
-#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
+#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
\r
typedef struct {\r
// General Purpose Registers\r
- UINT64 X0;\r
- UINT64 X1;\r
- UINT64 X2;\r
- UINT64 X3;\r
- UINT64 X4;\r
- UINT64 X5;\r
- UINT64 X6;\r
- UINT64 X7;\r
- UINT64 X8;\r
- UINT64 X9;\r
- UINT64 X10;\r
- UINT64 X11;\r
- UINT64 X12;\r
- UINT64 X13;\r
- UINT64 X14;\r
- UINT64 X15;\r
- UINT64 X16;\r
- UINT64 X17;\r
- UINT64 X18;\r
- UINT64 X19;\r
- UINT64 X20;\r
- UINT64 X21;\r
- UINT64 X22;\r
- UINT64 X23;\r
- UINT64 X24;\r
- UINT64 X25;\r
- UINT64 X26;\r
- UINT64 X27;\r
- UINT64 X28;\r
- UINT64 FP; // x29 - Frame pointer\r
- UINT64 LR; // x30 - Link Register\r
- UINT64 SP; // x31 - Stack pointer\r
+ UINT64 X0;\r
+ UINT64 X1;\r
+ UINT64 X2;\r
+ UINT64 X3;\r
+ UINT64 X4;\r
+ UINT64 X5;\r
+ UINT64 X6;\r
+ UINT64 X7;\r
+ UINT64 X8;\r
+ UINT64 X9;\r
+ UINT64 X10;\r
+ UINT64 X11;\r
+ UINT64 X12;\r
+ UINT64 X13;\r
+ UINT64 X14;\r
+ UINT64 X15;\r
+ UINT64 X16;\r
+ UINT64 X17;\r
+ UINT64 X18;\r
+ UINT64 X19;\r
+ UINT64 X20;\r
+ UINT64 X21;\r
+ UINT64 X22;\r
+ UINT64 X23;\r
+ UINT64 X24;\r
+ UINT64 X25;\r
+ UINT64 X26;\r
+ UINT64 X27;\r
+ UINT64 X28;\r
+ UINT64 FP; // x29 - Frame pointer\r
+ UINT64 LR; // x30 - Link Register\r
+ UINT64 SP; // x31 - Stack pointer\r
\r
// FP/SIMD Registers\r
- UINT64 V0[2];\r
- UINT64 V1[2];\r
- UINT64 V2[2];\r
- UINT64 V3[2];\r
- UINT64 V4[2];\r
- UINT64 V5[2];\r
- UINT64 V6[2];\r
- UINT64 V7[2];\r
- UINT64 V8[2];\r
- UINT64 V9[2];\r
- UINT64 V10[2];\r
- UINT64 V11[2];\r
- UINT64 V12[2];\r
- UINT64 V13[2];\r
- UINT64 V14[2];\r
- UINT64 V15[2];\r
- UINT64 V16[2];\r
- UINT64 V17[2];\r
- UINT64 V18[2];\r
- UINT64 V19[2];\r
- UINT64 V20[2];\r
- UINT64 V21[2];\r
- UINT64 V22[2];\r
- UINT64 V23[2];\r
- UINT64 V24[2];\r
- UINT64 V25[2];\r
- UINT64 V26[2];\r
- UINT64 V27[2];\r
- UINT64 V28[2];\r
- UINT64 V29[2];\r
- UINT64 V30[2];\r
- UINT64 V31[2];\r
-\r
- UINT64 ELR; // Exception Link Register\r
- UINT64 SPSR; // Saved Processor Status Register\r
- UINT64 FPSR; // Floating Point Status Register\r
- UINT64 ESR; // Exception syndrome register\r
- UINT64 FAR; // Fault Address Register\r
+ UINT64 V0[2];\r
+ UINT64 V1[2];\r
+ UINT64 V2[2];\r
+ UINT64 V3[2];\r
+ UINT64 V4[2];\r
+ UINT64 V5[2];\r
+ UINT64 V6[2];\r
+ UINT64 V7[2];\r
+ UINT64 V8[2];\r
+ UINT64 V9[2];\r
+ UINT64 V10[2];\r
+ UINT64 V11[2];\r
+ UINT64 V12[2];\r
+ UINT64 V13[2];\r
+ UINT64 V14[2];\r
+ UINT64 V15[2];\r
+ UINT64 V16[2];\r
+ UINT64 V17[2];\r
+ UINT64 V18[2];\r
+ UINT64 V19[2];\r
+ UINT64 V20[2];\r
+ UINT64 V21[2];\r
+ UINT64 V22[2];\r
+ UINT64 V23[2];\r
+ UINT64 V24[2];\r
+ UINT64 V25[2];\r
+ UINT64 V26[2];\r
+ UINT64 V27[2];\r
+ UINT64 V28[2];\r
+ UINT64 V29[2];\r
+ UINT64 V30[2];\r
+ UINT64 V31[2];\r
+\r
+ UINT64 ELR; // Exception Link Register\r
+ UINT64 SPSR; // Saved Processor Status Register\r
+ UINT64 FPSR; // Floating Point Status Register\r
+ UINT64 ESR; // Exception syndrome register\r
+ UINT64 FAR; // Fault Address Register\r
} EFI_SYSTEM_CONTEXT_AARCH64;\r
\r
///\r
/// RISC-V processor exception types.\r
///\r
-#define EXCEPT_RISCV_INST_MISALIGNED 0\r
-#define EXCEPT_RISCV_INST_ACCESS_FAULT 1\r
-#define EXCEPT_RISCV_ILLEGAL_INST 2\r
-#define EXCEPT_RISCV_BREAKPOINT 3\r
-#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4\r
-#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5\r
-#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6\r
-#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11\r
-\r
-#define EXCEPT_RISCV_SOFTWARE_INT 0x0\r
-#define EXCEPT_RISCV_TIMER_INT 0x1\r
+#define EXCEPT_RISCV_INST_MISALIGNED 0\r
+#define EXCEPT_RISCV_INST_ACCESS_FAULT 1\r
+#define EXCEPT_RISCV_ILLEGAL_INST 2\r
+#define EXCEPT_RISCV_BREAKPOINT 3\r
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4\r
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5\r
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6\r
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11\r
+\r
+#define EXCEPT_RISCV_SOFTWARE_INT 0x0\r
+#define EXCEPT_RISCV_TIMER_INT 0x1\r
\r
typedef struct {\r
- UINT64 X0;\r
- UINT64 X1;\r
- UINT64 X2;\r
- UINT64 X3;\r
- UINT64 X4;\r
- UINT64 X5;\r
- UINT64 X6;\r
- UINT64 X7;\r
- UINT64 X8;\r
- UINT64 X9;\r
- UINT64 X10;\r
- UINT64 X11;\r
- UINT64 X12;\r
- UINT64 X13;\r
- UINT64 X14;\r
- UINT64 X15;\r
- UINT64 X16;\r
- UINT64 X17;\r
- UINT64 X18;\r
- UINT64 X19;\r
- UINT64 X20;\r
- UINT64 X21;\r
- UINT64 X22;\r
- UINT64 X23;\r
- UINT64 X24;\r
- UINT64 X25;\r
- UINT64 X26;\r
- UINT64 X27;\r
- UINT64 X28;\r
- UINT64 X29;\r
- UINT64 X30;\r
- UINT64 X31;\r
+ UINT64 X0;\r
+ UINT64 X1;\r
+ UINT64 X2;\r
+ UINT64 X3;\r
+ UINT64 X4;\r
+ UINT64 X5;\r
+ UINT64 X6;\r
+ UINT64 X7;\r
+ UINT64 X8;\r
+ UINT64 X9;\r
+ UINT64 X10;\r
+ UINT64 X11;\r
+ UINT64 X12;\r
+ UINT64 X13;\r
+ UINT64 X14;\r
+ UINT64 X15;\r
+ UINT64 X16;\r
+ UINT64 X17;\r
+ UINT64 X18;\r
+ UINT64 X19;\r
+ UINT64 X20;\r
+ UINT64 X21;\r
+ UINT64 X22;\r
+ UINT64 X23;\r
+ UINT64 X24;\r
+ UINT64 X25;\r
+ UINT64 X26;\r
+ UINT64 X27;\r
+ UINT64 X28;\r
+ UINT64 X29;\r
+ UINT64 X30;\r
+ UINT64 X31;\r
} EFI_SYSTEM_CONTEXT_RISCV64;\r
\r
///\r
/// Universal EFI_SYSTEM_CONTEXT definition.\r
///\r
typedef union {\r
- EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
- EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
- EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
- EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
- EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
- EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
- EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;\r
+ EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
+ EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
+ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
+ EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
+ EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
+ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;\r
} EFI_SYSTEM_CONTEXT;\r
\r
//\r
/// Machine type definition\r
///\r
typedef enum {\r
- IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
- IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
- IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
- IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
- IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
- IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
+ IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
+ IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
+ IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
+ IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
+ IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
+ IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
\r
-\r
//\r
// DebugSupport member function definitions\r
//\r
///\r
/// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r
///\r
- EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
- EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
- EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
- EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
- EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
+ EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
+ EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
+ EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
+ EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
+ EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
};\r
\r
-extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
+extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff