--- /dev/null
+/** @file\r
+ This file declares PCI Host Bridge Resource Allocation Protocol which \r
+ provides the basic interfaces to abstract a PCI host bridge resource allocation. \r
+ This protocol is mandatory if the system includes PCI devices.\r
+ \r
+ Copyright (c) 2007 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
+ Volume 5: Standards\r
+ \r
+**/\r
+\r
+#ifndef _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
+#define _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
+\r
+//\r
+// This file must be included because EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+// uses EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS\r
+//\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+///\r
+/// Global ID for the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+///\r
+#define EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID \\r
+ { \\r
+ 0xCF8034BE, 0x6768, 0x4d8b, {0xB7,0x39,0x7C,0xCE,0x68,0x3A,0x9F,0xBE } \\r
+ }\r
+\r
+///\r
+/// Forward declaration for EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+///\r
+typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL;\r
+\r
+/// If this bit is set, then the PCI Root Bridge does not\r
+/// support separate windows for Non-prefetchable and Prefetchable\r
+/// memory. A PCI bus driver needs to include requests for Prefetchable\r
+/// memory in the Non-prefetchable memory pool.\r
+///\r
+#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 1\r
+\r
+///\r
+/// If this bit is set, then the PCI Root Bridge supports\r
+/// 64 bit memory windows. If this bit is not set,\r
+/// the PCI bus driver needs to include requests for 64 bit\r
+/// memory address in the corresponding 32 bit memory pool.\r
+///\r
+#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2\r
+\r
+///\r
+/// A UINT64 value that contains the status of a PCI resource requested \r
+/// in the Configuration parameter returned by GetProposedResources()\r
+/// The legal values are EFI_RESOURCE_SATISFIED and EFI_RESOURCE_NOT_SATISFIED\r
+///\r
+typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;\r
+\r
+///\r
+/// The request of this resource type could be fulfilled. Used in the \r
+/// Configuration parameter returned by GetProposedResources() to identify\r
+/// a PCI resources request that can be satisfied.\r
+///\r
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
+\r
+///\r
+/// The request of this resource type could not be fulfilled for its\r
+/// absence in the host bridge resource pool. Used in the Configuration parameter \r
+/// returned by GetProposedResources() to identify a PCI resources request that\r
+/// can not be satisfied.\r
+///\r
+#define EFI_RESOURCE_NOT_SATISFIED 0xFFFFFFFFFFFFFFFFULL\r
+\r
+///\r
+/// This enum is used to specify the phase of the PCI enumaeration process\r
+///\r
+typedef enum {\r
+ ///\r
+ /// Reset the host bridge PCI apertures and internal data structures.\r
+ /// PCI enumerator should issue this notification before starting fresh\r
+ /// enumeration process. Enumeration cannot be restarted after sending\r
+ /// any other notification such as EfiPciHostBridgeBeginBusAllocation.\r
+ ///\r
+ EfiPciHostBridgeBeginEnumeration,\r
+\r
+ ///\r
+ /// The bus allocation phase is about to begin. No specific action\r
+ /// is required here. This notification can be used to perform any\r
+ /// chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeBeginBusAllocation,\r
+\r
+ ///\r
+ /// The bus allocation and bus programming phase is complete. No specific\r
+ /// action is required here. This notification can be used to perform any\r
+ /// chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeEndBusAllocation,\r
+ \r
+ ///\r
+ /// The resource allocation phase is about to begin.No specific action is\r
+ /// required here. This notification can be used to perform any chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeBeginResourceAllocation,\r
+ \r
+ ///\r
+ /// Allocate resources per previously submitted requests for all the PCI Root\r
+ /// Bridges. These resource settings are returned on the next call to\r
+ /// GetProposedResources(). \r
+ ///\r
+ EfiPciHostBridgeAllocateResources,\r
+ \r
+ ///\r
+ /// Program the Host Bridge hardware to decode previously allocated resources\r
+ /// (proposed resources) for all the PCI Root Bridges.\r
+ ///\r
+ EfiPciHostBridgeSetResources,\r
+ \r
+ ///\r
+ /// De-allocate previously allocated resources previously for all the PCI\r
+ /// Root Bridges and reset the I/O and memory apertures to initial state. \r
+ ///\r
+ EfiPciHostBridgeFreeResources,\r
+ \r
+ ///\r
+ /// The resource allocation phase is completed. No specific action is required\r
+ /// here. This notification can be used to perform any chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeEndResourceAllocation\r
+} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE;\r
+\r
+///\r
+/// Definitions of 2 notification points.\r
+///\r
+typedef enum {\r
+ ///\r
+ /// This notification is only applicable to PCI-PCI bridges and\r
+ /// indicates that the PCI enumerator is about to begin enumerating\r
+ /// the bus behind the PCI-PCI Bridge. This notification is sent after\r
+ /// the primary bus number, the secondary bus number and the subordinate\r
+ /// bus number registers in the PCI-PCI Bridge are programmed to valid\r
+ /// (not necessary final) values\r
+ ///\r
+ EfiPciBeforeChildBusEnumeration,\r
+\r
+ ///\r
+ /// This notification is sent before the PCI enumerator probes BAR registers\r
+ /// for every valid PCI function. \r
+ ///\r
+ EfiPciBeforeResourceCollection\r
+} EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE;\r
+\r
+/**\r
+ These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI \r
+ enumeration process.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] Phase The phase during enumeration\r
+\r
+ @retval EFI_SUCCESS The notification was accepted without any errors.\r
+ @retval EFI_INVALID_PARAMETER The Phase is invalid.\r
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error \r
+ is valid for a Phase of EfiPciHostBridgeAllocateResources if \r
+ SubmitResources() has not been called for one or more \r
+ PCI root bridges before this call.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid for \r
+ a Phase of EfiPciHostBridgeSetResources.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
+ This error is valid for a Phase of EfiPciHostBridgeAllocateResources\r
+ if the previously submitted resource requests cannot be fulfilled or were only \r
+ partially fulfilled\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
+ );\r
+\r
+/**\r
+ Returns the device handle of the next PCI root bridge that is associated with this host bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in,out] RootBridgeHandle Returns the device handle of the next PCI root bridge. On input, it holds the \r
+ RootBridgeHandle that was returned by the most recent call to \r
+ GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle \r
+ for the first PCI root bridge is returned.\r
+\r
+ @retval EFI_SUCCESS The requested attribute information was returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was returned \r
+ on a previous call to GetNextRootBridge().\r
+ @retval EFI_NOT_FOUND There are no more PCI root bridge device handles.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN OUT EFI_HANDLE *RootBridgeHandle\r
+ );\r
+\r
+/**\r
+ Returns the allocation attributes of a PCI root bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested.\r
+ @param[out] Attribute The pointer to attributes of the PCI root bridge.\r
+\r
+ @retval EFI_SUCCESS The requested attribute information was returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Attributes is NULL.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT UINT64 *Attributes\r
+ );\r
+\r
+/**\r
+ Sets up the specified PCI root bridge for the bus enumeration process.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge to be set up.\r
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The PCI root bridge was set up and the bus range was returned in \r
+ Configuration.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ );\r
+\r
+/**\r
+ Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance. \r
+ @param[in] RootBridgeHandle The PCI root bridge whose bus range is to be programmed.\r
+ @param[in] Configuration The pointer to the PCI bus resource descriptor..\r
+\r
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
+ resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource\r
+ descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI (2.0 & 3.0) resource \r
+ descriptors other than bus descriptors.\r
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource \r
+ descriptors.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ );\r
+\r
+/**\r
+ Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being \r
+ submitted.\r
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were \r
+ accepted.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
+ resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource \r
+ types that are not supported by this PCI root bridge. This error will \r
+ happen if the caller did not combine resources according to \r
+ Attributes that were returned by GetAllocAttributes().\r
+ @retval EFI_INVALID_PARAMETER "Address Range Maximum" is invalid.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
+ \r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ );\r
+\r
+/**\r
+ Returns the proposed resource settings for the specified PCI root bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge handle.\r
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ );\r
+\r
+/**\r
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various \r
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual \r
+ PCI controllers before enumeration.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The associated PCI root bridge handle.\r
+ @param[in] PciAddress The address of the PCI device on the PCI bus.\r
+ @param[in] Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in \r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator \r
+ should not enumerate this device, including its child devices if it is \r
+ a PCI-to-PCI bridge.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ );\r
+\r
+///\r
+/// Provides the basic interfaces to abstract a PCI host bridge resource allocation.\r
+///\r
+struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL {\r
+ ///\r
+ /// The notification from the PCI bus enumerator that it is about to enter\r
+ /// a certain phase during the enumeration process.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase;\r
+ \r
+ ///\r
+ /// Retrieves the device handle for the next PCI root bridge that is produced by the\r
+ /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached. \r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge;\r
+ \r
+ ///\r
+ /// Retrieves the allocation-related attributes of a PCI root bridge.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes;\r
+ \r
+ ///\r
+ /// Sets up a PCI root bridge for bus enumeration.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration;\r
+ \r
+ ///\r
+ /// Sets up the PCI root bridge so that it decodes a specific range of bus numbers.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers;\r
+ \r
+ ///\r
+ /// Submits the resource requirements for the specified PCI root bridge.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources;\r
+ \r
+ ///\r
+ /// Returns the proposed resource assignment for the specified PCI root bridges.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;\r
+ \r
+ ///\r
+ /// Provides hooks from the PCI bus driver to every PCI controller\r
+ /// (device/function) at various stages of the PCI enumeration process that\r
+ /// allow the host bridge driver to preinitialize individual PCI controllers\r
+ /// before enumeration. \r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController;\r
+};\r
+\r
+extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid;\r
+\r
+#endif\r
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