--- /dev/null
+/** @file\r
+ This file declares EFI IDE Controller Init Protocol\r
+ \r
+ The EFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information\r
+ to the IDE bus driver. This protocol is mandatory for IDE controllers if the\r
+ IDE devices behind the controller are to be enumerated by an IDE bus driver.\r
+ \r
+ There can only be one instance of EFI_IDE_CONTROLLER_INIT_PROTOCOL for each IDE\r
+ controller in a system. It is installed on the handle that corresponds to the\r
+ IDE controller. An IDE bus driver that wishes to manage an IDE bus and possibly\r
+ IDE devices in a system will have to retrieve the EFI_IDE_CONTROLLER_INIT_PROTOCOL\r
+ instance that is associated with the controller to be managed.\r
+ \r
+ A device handle for an IDE controller must contain an EFI_DEVICE_PATH_PROTOCOL.\r
+\r
+ Copyright (c) 2007 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
+ Volume 5: Standards\r
+ \r
+**/\r
+\r
+#ifndef _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_\r
+#define _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_\r
+\r
+///\r
+/// Global ID for the EFI_IDE_CONTROLLER_INIT_PROTOCOL\r
+///\r
+#define EFI_IDE_CONTROLLER_INIT_PROTOCOL_GUID \\r
+ { \\r
+ 0xa1e37052, 0x80d9, 0x4e65, {0xa3, 0x17, 0x3e, 0x9a, 0x55, 0xc4, 0x3e, 0xc9 } \\r
+ }\r
+\r
+///\r
+/// Forward declaration for EFI_IDE_CONTROLLER_INIT_PROTOCOL\r
+///\r
+typedef struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL EFI_IDE_CONTROLLER_INIT_PROTOCOL;\r
+\r
+///\r
+/// The phase of the IDE Controller enumeration\r
+///\r
+typedef enum {\r
+ ///\r
+ /// The IDE bus driver is about to begin enumerating the devices\r
+ /// behind the specified channel. This notification can be used to\r
+ /// perform any chipset-specific programming.\r
+ ///\r
+ EfiIdeBeforeChannelEnumeration,\r
+ ///\r
+ /// The IDE bus driver has completed enumerating the devices\r
+ /// behind the specified channel. This notification can be used to\r
+ /// perform any chipset-specific programming.\r
+ ///\r
+ EfiIdeAfterChannelEnumeration,\r
+ ///\r
+ /// The IDE bus driver is about to reset the devices behind the\r
+ /// specified channel. This notification can be used to perform any\r
+ /// chipset-specific programming.\r
+ ///\r
+ EfiIdeBeforeChannelReset,\r
+ ///\r
+ /// The IDE bus driver has completed resetting the devices behind\r
+ /// the specified channel. This notification can be used to perform\r
+ /// any chipset-specific programming. \r
+ ///\r
+ EfiIdeAfterChannelReset,\r
+ ///\r
+ /// The IDE bus driver is about to detect the presence of devices\r
+ /// behind the specified channel. This notification can be used to\r
+ /// set up the bus signals to default levels or for implementing\r
+ /// predelays.\r
+ ///\r
+ EfiIdeBusBeforeDevicePresenceDetection,\r
+ ///\r
+ /// The IDE bus driver is done with detecting the presence of\r
+ /// devices behind the specified channel. This notification can be\r
+ /// used to perform any chipset-specific programming. \r
+ ///\r
+ EfiIdeBusAfterDevicePresenceDetection,\r
+ ///\r
+ /// The IDE bus is requesting the IDE controller driver to\r
+ /// reprogram the IDE controller hardware and thereby reset all\r
+ /// the mode and timing settings to default settings. \r
+ ///\r
+ EfiIdeResetMode,\r
+ EfiIdeBusPhaseMaximum\r
+} EFI_IDE_CONTROLLER_ENUM_PHASE;\r
+\r
+///\r
+/// This extended mode describes the SATA physical protocol.\r
+/// SATA physical layers can operate at different speeds.\r
+/// These speeds are defined below. Various PATA protocols\r
+/// and associated modes are not applicable to SATA devices.\r
+///\r
+typedef enum {\r
+ EfiAtaSataTransferProtocol\r
+} EFI_ATA_EXT_TRANSFER_PROTOCOL;\r
+\r
+///\r
+/// Automatically detects the optimum SATA speed.\r
+///\r
+#define EFI_SATA_AUTO_SPEED 0\r
+\r
+///\r
+/// Indicates a first-generation (Gen1) SATA speed.\r
+///\r
+#define EFI_SATA_GEN1_SPEED 1\r
+\r
+///\r
+/// Indicates a second-generation (Gen2) SATA speed.\r
+///\r
+#define EFI_SATA_GEN2_SPEED 2\r
+\r
+///\r
+/// EFI_ATA_MODE structure\r
+///\r
+typedef struct {\r
+ BOOLEAN Valid; ///< TRUE if Mode is valid.\r
+ UINT32 Mode; ///< The actual ATA mode. This field is not a bit map.\r
+} EFI_ATA_MODE;\r
+\r
+///\r
+/// EFI_ATA_EXTENDED_MODE structure\r
+///\r
+typedef struct {\r
+ ///\r
+ /// An enumeration defining various transfer protocols other than the protocols\r
+ /// that exist at the time this specification was developed (i.e., PIO, single \r
+ /// word DMA, multiword DMA, and UDMA). Each transfer protocol is associated \r
+ /// with a mode. The various transfer protocols are defined by the ATA/ATAPI \r
+ /// specification. This enumeration makes the interface extensible because we \r
+ /// can support new transport protocols beyond UDMA. Type EFI_ATA_EXT_TRANSFER_PROTOCOL \r
+ /// is defined below.\r
+ ///\r
+ EFI_ATA_EXT_TRANSFER_PROTOCOL TransferProtocol;\r
+ ///\r
+ /// The mode for operating the transfer protocol that is identified by TransferProtocol.\r
+ ///\r
+ UINT32 Mode;\r
+} EFI_ATA_EXTENDED_MODE;\r
+\r
+///\r
+/// EFI_ATA_COLLECTIVE_MODE structure\r
+///\r
+typedef struct {\r
+ ///\r
+ /// This field specifies the PIO mode. PIO modes are defined in the ATA/ATAPI\r
+ /// specification. The ATA/ATAPI specification defines the enumeration. In \r
+ /// other words, a value of 1 in this field means PIO mode 1. The actual meaning\r
+ /// of PIO mode 1 is governed by the ATA/ATAPI specification. Type EFI_ATA_MODE\r
+ /// is defined below.\r
+ ///\r
+ EFI_ATA_MODE PioMode;\r
+ ///\r
+ /// This field specifies the single word DMA mode. Single word DMA modes are defined\r
+ /// in the ATA/ATAPI specification, versions 1 and 2. Single word DMA support was\r
+ /// obsoleted in the ATA/ATAPI specification, version 3; therefore, most devices and\r
+ /// controllers will not support this transfer mode. The ATA/ATAPI specification defines\r
+ /// the enumeration. In other words, a value of 1 in this field means single word DMA\r
+ /// mode 1. The actual meaning of single word DMA mode 1 is governed by the ATA/\r
+ /// ATAPI specification. \r
+ ///\r
+ EFI_ATA_MODE SingleWordDmaMode;\r
+ ///\r
+ /// This field specifies the multiword DMA mode. Various multiword DMA modes are\r
+ /// defined in the ATA/ATAPI specification. A value of 1 in this field means multiword\r
+ /// DMA mode 1. The actual meaning of multiword DMA mode 1 is governed by the\r
+ /// ATA/ATAPI specification. \r
+ ///\r
+ EFI_ATA_MODE MultiWordDmaMode;\r
+ ///\r
+ /// This field specifies the ultra DMA (UDMA) mode. UDMA modes are defined in the\r
+ /// ATA/ATAPI specification. A value of 1 in this field means UDMA mode 1. The\r
+ /// actual meaning of UDMA mode 1 is governed by the ATA/ATAPI specification. \r
+ ///\r
+ EFI_ATA_MODE UdmaMode;\r
+ ///\r
+ /// The number of extended-mode bitmap entries. Extended modes describe transfer\r
+ /// protocols beyond PIO, single word DMA, multiword DMA, and UDMA. This field\r
+ /// can be zero and provides extensibility. \r
+ ///\r
+ UINT32 ExtModeCount;\r
+ ///\r
+ /// ExtModeCount number of entries. Each entry represents a transfer protocol other\r
+ /// than the ones defined above (i.e., PIO, single word DMA, multiword DMA, and\r
+ /// UDMA). This field is defined for extensibility. At this time, only one extended\r
+ /// transfer protocol is defined to cover SATA transfers. Type\r
+ /// EFI_ATA_EXTENDED_MODE is defined below. \r
+ ///\r
+ EFI_ATA_EXTENDED_MODE ExtMode[1];\r
+} EFI_ATA_COLLECTIVE_MODE;\r
+\r
+///\r
+/// EFI_ATA_IDENTIFY_DATA structure\r
+///\r
+/// This structure definition is not part of the protocol\r
+/// definition because the ATA/ATAPI Specification controls\r
+/// the definition of all the fields. The ATA/ATAPI\r
+/// Specification can obsolete old fields or redefine existing\r
+/// fields. This definition is provided here for reference only.\r
+///\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT16 config; ///< General Configuration\r
+ UINT16 cylinders; ///< Number of Cylinders\r
+ UINT16 reserved_2;\r
+ UINT16 heads; ///< Number of logical heads\r
+ UINT16 vendor_data1;\r
+ UINT16 vendor_data2;\r
+ UINT16 sectors_per_track;\r
+ UINT16 vendor_specific_7_9[3];\r
+ CHAR8 SerialNo[20]; ///< ASCII\r
+ UINT16 vendor_specific_20_21[2];\r
+ UINT16 ecc_bytes_available;\r
+ CHAR8 FirmwareVer[8]; ///< ASCII\r
+ CHAR8 ModelName[40]; ///< ASCII\r
+ UINT16 multi_sector_cmd_max_sct_cnt;\r
+ UINT16 reserved_48;\r
+ UINT16 capabilities;\r
+ UINT16 reserved_50;\r
+ UINT16 pio_cycle_timing;\r
+ UINT16 reserved_52;\r
+ UINT16 field_validity;\r
+ UINT16 current_cylinders;\r
+ UINT16 current_heads;\r
+ UINT16 current_sectors;\r
+ UINT16 CurrentCapacityLsb;\r
+ UINT16 CurrentCapacityMsb;\r
+ UINT16 reserved_59;\r
+ UINT16 user_addressable_sectors_lo;\r
+ UINT16 user_addressable_sectors_hi;\r
+ UINT16 reserved_62;\r
+ UINT16 multi_word_dma_mode;\r
+ UINT16 advanced_pio_modes;\r
+ UINT16 min_multi_word_dma_cycle_time;\r
+ UINT16 rec_multi_word_dma_cycle_time;\r
+ UINT16 min_pio_cycle_time_without_flow_control;\r
+ UINT16 min_pio_cycle_time_with_flow_control;\r
+ UINT16 reserved_69_79[11];\r
+ UINT16 major_version_no;\r
+ UINT16 minor_version_no;\r
+ UINT16 command_set_supported_82; ///< word 82\r
+ UINT16 command_set_supported_83; ///< word 83\r
+ UINT16 command_set_feature_extn; ///< word 84\r
+ UINT16 command_set_feature_enb_85; ///< word 85\r
+ UINT16 command_set_feature_enb_86; ///< word 86\r
+ UINT16 command_set_feature_default; ///< word 87\r
+ UINT16 ultra_dma_mode; ///< word 88\r
+ UINT16 reserved_89_105[17];\r
+ UINT16 phy_logic_sector_support; ///< word 106\r
+ UINT16 reserved_107_116[10];\r
+ UINT16 logic_sector_size_lo; ///< word 117\r
+ UINT16 logic_sector_size_hi; ///< word 118\r
+ UINT16 reserved_119_127[9];\r
+ UINT16 security_status;\r
+ UINT16 vendor_data_129_159[31];\r
+ UINT16 reserved_160_208[49];\r
+ UINT16 alignment_logic_in_phy_blocks; ///< word 209\r
+ UINT16 reserved_210_255[46];\r
+} EFI_ATA_IDENTIFY_DATA;\r
+#pragma pack()\r
+\r
+///\r
+/// EFI_ATAPI_IDENTIFY_DATA structure\r
+///\r
+/// This structure definition is not part of the protocol\r
+/// definition because the ATA/ATAPI Specification controls\r
+/// the definition of all the fields. The ATA/ATAPI\r
+/// Specification can obsolete old fields or redefine existing\r
+/// fields. This definition is provided here for reference only.\r
+///\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT16 config; ///< General Configuration\r
+ UINT16 obsolete_1;\r
+ UINT16 specific_config;\r
+ UINT16 obsolete_3;\r
+ UINT16 retired_4_5[2];\r
+ UINT16 obsolete_6;\r
+ UINT16 cfa_reserved_7_8[2];\r
+ UINT16 retired_9;\r
+ CHAR8 SerialNo[20]; ///< ASCII\r
+ UINT16 retired_20_21[2];\r
+ UINT16 obsolete_22;\r
+ CHAR8 FirmwareVer[8]; ///< ASCII\r
+ CHAR8 ModelName[40]; ///< ASCII\r
+ UINT16 multi_sector_cmd_max_sct_cnt;\r
+ UINT16 reserved_48;\r
+ UINT16 capabilities_49;\r
+ UINT16 capabilities_50;\r
+ UINT16 obsolete_51_52[2];\r
+ UINT16 field_validity;\r
+ UINT16 obsolete_54_58[5];\r
+ UINT16 mutil_sector_setting;\r
+ UINT16 user_addressable_sectors_lo;\r
+ UINT16 user_addressable_sectors_hi;\r
+ UINT16 obsolete_62;\r
+ UINT16 multi_word_dma_mode;\r
+ UINT16 advanced_pio_modes;\r
+ UINT16 min_multi_word_dma_cycle_time;\r
+ UINT16 rec_multi_word_dma_cycle_time;\r
+ UINT16 min_pio_cycle_time_without_flow_control;\r
+ UINT16 min_pio_cycle_time_with_flow_control;\r
+ UINT16 reserved_69_74[6];\r
+ UINT16 queue_depth;\r
+ UINT16 reserved_76_79[4];\r
+ UINT16 major_version_no;\r
+ UINT16 minor_version_no;\r
+ UINT16 cmd_set_support_82;\r
+ UINT16 cmd_set_support_83;\r
+ UINT16 cmd_feature_support;\r
+ UINT16 cmd_feature_enable_85;\r
+ UINT16 cmd_feature_enable_86;\r
+ UINT16 cmd_feature_default;\r
+ UINT16 ultra_dma_select;\r
+ UINT16 time_required_for_sec_erase;\r
+ UINT16 time_required_for_enhanced_sec_erase;\r
+ UINT16 current_advanced_power_mgmt_value;\r
+ UINT16 master_pwd_revison_code;\r
+ UINT16 hardware_reset_result;\r
+ UINT16 current_auto_acoustic_mgmt_value;\r
+ UINT16 reserved_95_99[5];\r
+ UINT16 max_user_lba_for_48bit_addr[4];\r
+ UINT16 reserved_104_126[23];\r
+ UINT16 removable_media_status_notification_support;\r
+ UINT16 security_status;\r
+ UINT16 vendor_data_129_159[31];\r
+ UINT16 cfa_power_mode;\r
+ UINT16 cfa_reserved_161_175[15];\r
+ UINT16 current_media_serial_no[30];\r
+ UINT16 reserved_206_254[49];\r
+ UINT16 integrity_word;\r
+} EFI_ATAPI_IDENTIFY_DATA;\r
+#pragma pack()\r
+\r
+///\r
+/// This flag indicates whether the IDENTIFY data is a response from an ATA device\r
+/// (EFI_ATA_IDENTIFY_DATA) or response from an ATAPI device \r
+/// (EFI_ATAPI_IDENTIFY_DATA). According to the ATA/ATAPI specification,\r
+/// EFI_IDENTIFY_DATA is for an ATA device if bit 15 of the Config field is zero. \r
+/// The Config field is common to both EFI_ATA_IDENTIFY_DATA and \r
+/// EFI_ATAPI_IDENTIFY_DATA.\r
+///\r
+#define EFI_ATAPI_DEVICE_IDENTIFY_DATA 0x8000\r
+\r
+///\r
+/// EFI_IDENTIFY_DATA structure\r
+///\r
+typedef union {\r
+ ///\r
+ /// The data that is returned by an ATA device upon successful completion \r
+ /// of the ATA IDENTIFY_DEVICE command. \r
+ ///\r
+ EFI_ATA_IDENTIFY_DATA AtaData;\r
+ ///\r
+ /// The data that is returned by an ATAPI device upon successful completion\r
+ /// of the ATA IDENTIFY_PACKET_DEVICE command.\r
+ ///\r
+ EFI_ATAPI_IDENTIFY_DATA AtapiData;\r
+} EFI_IDENTIFY_DATA;\r
+\r
+/**\r
+ Returns the information about the specified IDE channel.\r
+ \r
+ This function can be used to obtain information about a particular IDE channel.\r
+ The IDE bus driver uses this information during the enumeration process. \r
+ \r
+ If Enabled is set to FALSE, the IDE bus driver will not scan the channel. Note \r
+ that it will not prevent an operating system driver from scanning the channel.\r
+ \r
+ For most of today's controllers, MaxDevices will either be 1 or 2. For SATA \r
+ controllers, this value will always be 1. SATA configurations can contain SATA \r
+ port multipliers. SATA port multipliers behave like SATA bridges and can support\r
+ up to 16 devices on the other side. If an SATA port out of the IDE controller \r
+ is connected to a port multiplier, MaxDevices will be set to the number of SATA \r
+ devices that the port multiplier supports. Because today's port multipliers \r
+ support up to 15 SATA devices, this number can be as large as 15. The IDE bus \r
+ driver is required to scan for the presence of port multipliers behind an SATA \r
+ controller and enumerate up to MaxDevices number of devices behind the port \r
+ multiplier. \r
+ \r
+ In this context, the devices behind a port multiplier constitute a channel. \r
+ \r
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
+ @param[in] Channel Zero-based channel number.\r
+ @param[out] Enabled TRUE if this channel is enabled. Disabled channels \r
+ are not scanned to see if any devices are present.\r
+ @param[out] MaxDevices The maximum number of IDE devices that the bus driver\r
+ can expect on this channel. For the ATA/ATAPI \r
+ specification, version 6, this number will either be \r
+ 1 or 2. For Serial ATA (SATA) configurations with a \r
+ port multiplier, this number can be as large as 15.\r
+\r
+ @retval EFI_SUCCESS Information was returned without any errors.\r
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_IDE_CONTROLLER_GET_CHANNEL_INFO)(\r
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
+ IN UINT8 Channel,\r
+ OUT BOOLEAN *Enabled,\r
+ OUT UINT8 *MaxDevices\r
+ );\r
+\r
+/**\r
+ The notifications from the IDE bus driver that it is about to enter a certain\r
+ phase of the IDE channel enumeration process.\r
+ \r
+ This function can be used to notify the IDE controller driver to perform \r
+ specific actions, including any chipset-specific initialization, so that the \r
+ chipset is ready to enter the next phase. Seven notification points are defined \r
+ at this time. \r
+ \r
+ More synchronization points may be added as required in the future. \r
+\r
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
+ @param[in] Phase The phase during enumeration.\r
+ @param[in] Channel Zero-based channel number.\r
+\r
+ @retval EFI_SUCCESS The notification was accepted without any errors.\r
+ @retval EFI_NOT_SUPPORTED Phase is not supported.\r
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
+ @retval EFI_NOT_READY This phase cannot be entered at this time; for \r
+ example, an attempt was made to enter a Phase \r
+ without having entered one or more previous \r
+ Phase.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_IDE_CONTROLLER_NOTIFY_PHASE)(\r
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
+ IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,\r
+ IN UINT8 Channel\r
+ );\r
+\r
+/**\r
+ Submits the device information to the IDE controller driver.\r
+\r
+ This function is used by the IDE bus driver to pass detailed information about \r
+ a particular device to the IDE controller driver. The IDE bus driver obtains \r
+ this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData\r
+ is the pointer to the response data buffer. The IdentifyData buffer is owned \r
+ by the IDE bus driver, and the IDE controller driver must make a local copy \r
+ of the entire buffer or parts of the buffer as needed. The original IdentifyData \r
+ buffer pointer may not be valid when\r
+ \r
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or\r
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point.\r
+ \r
+ The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to \r
+ compute the optimum mode for the device. These fields are not limited to the \r
+ timing information. For example, an implementation of the IDE controller driver \r
+ may examine the vendor and type/mode field to match known bad drives. \r
+ \r
+ The IDE bus driver may submit drive information in any order, as long as it \r
+ submits information for all the devices belonging to the enumeration group \r
+ before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device\r
+ in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()\r
+ should be called with IdentifyData set to NULL. The IDE controller driver may \r
+ not have any other mechanism to know whether a device is present or not. Therefore, \r
+ setting IdentifyData to NULL does not constitute an error condition. \r
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a \r
+ given (Channel, Device) pair. \r
+ \r
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
+ @param[in] Channel Zero-based channel number.\r
+ @param[in] Device Zero-based device number on the Channel.\r
+ @param[in] IdentifyData The device's response to the ATA IDENTIFY_DEVICE command.\r
+\r
+ @retval EFI_SUCCESS The information was accepted without any errors.\r
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
+ @retval EFI_INVALID_PARAMETER Device is invalid.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_IDE_CONTROLLER_SUBMIT_DATA)(\r
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
+ IN UINT8 Channel,\r
+ IN UINT8 Device,\r
+ IN EFI_IDENTIFY_DATA *IdentifyData\r
+ );\r
+\r
+/**\r
+ Disqualifies specific modes for an IDE device.\r
+\r
+ This function allows the IDE bus driver or other drivers (such as platform \r
+ drivers) to reject certain timing modes and request the IDE controller driver\r
+ to recalculate modes. This function allows the IDE bus driver and the IDE \r
+ controller driver to negotiate the timings on a per-device basis. This function \r
+ is useful in the case of drives that lie about their capabilities. An example \r
+ is when the IDE device fails to accept the timing modes that are calculated \r
+ by the IDE controller driver based on the response to the Identify Drive command.\r
+\r
+ If the IDE bus driver does not want to limit the ATA timing modes and leave that \r
+ decision to the IDE controller driver, it can either not call this function for \r
+ the given device or call this function and set the Valid flag to FALSE for all \r
+ modes that are listed in EFI_ATA_COLLECTIVE_MODE.\r
+ \r
+ The IDE bus driver may disqualify modes for a device in any order and any number \r
+ of times.\r
+ \r
+ This function can be called multiple times to invalidate multiple modes of the \r
+ same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI \r
+ specification for more information on PIO modes. \r
+ \r
+ For Serial ATA (SATA) controllers, this member function can be used to disqualify\r
+ a higher transfer rate mode on a given channel. For example, a platform driver\r
+ may inform the IDE controller driver to not use second-generation (Gen2) speeds \r
+ for a certain SATA drive.\r
+ \r
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
+ @param[in] Channel Zero-based channel number.\r
+ @param[in] Device Zero-based device number on the Channel.\r
+ @param[in] BadModes The modes that the device does not support and that\r
+ should be disqualified.\r
+\r
+ @retval EFI_SUCCESS The modes were accepted without any errors.\r
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
+ @retval EFI_INVALID_PARAMETER Device is invalid.\r
+ @retval EFI_INVALID_PARAMETER IdentifyData is NULL.\r
+ \r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_IDE_CONTROLLER_DISQUALIFY_MODE)(\r
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
+ IN UINT8 Channel,\r
+ IN UINT8 Device,\r
+ IN EFI_ATA_COLLECTIVE_MODE *BadModes\r
+ );\r
+\r
+/**\r
+ Returns the information about the optimum modes for the specified IDE device.\r
+\r
+ This function is used by the IDE bus driver to obtain the optimum ATA modes for\r
+ a specific device. The IDE controller driver takes into account the following \r
+ while calculating the mode:\r
+ - The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()\r
+ - The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()\r
+\r
+ The IDE bus driver is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() \r
+ for all the devices that belong to an enumeration group before calling \r
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group. \r
+ \r
+ The IDE controller driver will use controller- and possibly platform-specific \r
+ algorithms to arrive at SupportedModes. The IDE controller may base its \r
+ decision on user preferences and other considerations as well. This function \r
+ may be called multiple times because the IDE bus driver may renegotiate the mode \r
+ with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode().\r
+ \r
+ The IDE bus driver may collect timing information for various devices in any \r
+ order. The IDE bus driver is responsible for making sure that all the dependencies\r
+ are satisfied; for example, the SupportedModes information for device A that \r
+ was previously returned may become stale after a call to \r
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B.\r
+ \r
+ The buffer SupportedModes is allocated by the callee because the caller does \r
+ not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE \r
+ is defined in a way that allows for future extensibility and can be of variable \r
+ length. This memory pool should be deallocated by the caller when it is no \r
+ longer necessary. \r
+ \r
+ The IDE controller driver for a Serial ATA (SATA) controller can use this \r
+ member function to force a lower speed (first-generation [Gen1] speeds on a \r
+ second-generation [Gen2]-capable hardware). The IDE controller driver can \r
+ also allow the IDE bus driver to stay with the speed that has been negotiated \r
+ by the physical layer.\r
+ \r
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
+ @param[in] Channel Zero-based channel number.\r
+ @param[in] Device Zero-based device number on the Channel.\r
+ @param[out] SupportedModes The optimum modes for the device.\r
+\r
+ @retval EFI_SUCCESS SupportedModes was returned.\r
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
+ @retval EFI_INVALID_PARAMETER Device is invalid. \r
+ @retval EFI_INVALID_PARAMETER SupportedModes is NULL.\r
+ @retval EFI_NOT_READY Modes cannot be calculated due to a lack of \r
+ data. This error may happen if \r
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() \r
+ and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData() \r
+ were not called for at least one drive in the \r
+ same enumeration group.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_IDE_CONTROLLER_CALCULATE_MODE)(\r
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
+ IN UINT8 Channel,\r
+ IN UINT8 Device,\r
+ OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes\r
+ );\r
+\r
+/**\r
+ Commands the IDE controller driver to program the IDE controller hardware\r
+ so that the specified device can operate at the specified mode.\r
+\r
+ This function is used by the IDE bus driver to instruct the IDE controller \r
+ driver to program the IDE controller hardware to the specified modes. This \r
+ function can be called only once for a particular device. For a Serial ATA \r
+ (SATA) Advanced Host Controller Interface (AHCI) controller, no controller-\r
+ specific programming may be required.\r
+\r
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.\r
+ @param[in] Channel Zero-based channel number.\r
+ @param[in] Device Zero-based device number on the Channel.\r
+ @param[in] Modes The modes to set.\r
+\r
+ @retval EFI_SUCCESS The command was accepted without any errors.\r
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).\r
+ @retval EFI_INVALID_PARAMETER Device is invalid.\r
+ @retval EFI_NOT_READY Modes cannot be set at this time due to lack of data.\r
+ @retval EFI_DEVICE_ERROR Modes cannot be set due to hardware failure.\r
+ The IDE bus driver should not use this device.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_IDE_CONTROLLER_SET_TIMING)(\r
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,\r
+ IN UINT8 Channel,\r
+ IN UINT8 Device,\r
+ IN EFI_ATA_COLLECTIVE_MODE *Modes\r
+ );\r
+\r
+///\r
+/// Provides the basic interfaces to abstract an IDE controller.\r
+///\r
+struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL {\r
+ ///\r
+ /// Returns the information about a specific channel.\r
+ ///\r
+ EFI_IDE_CONTROLLER_GET_CHANNEL_INFO GetChannelInfo;\r
+ \r
+ ///\r
+ /// The notification that the IDE bus driver is about to enter the\r
+ /// specified phase during the enumeration process. \r
+ ///\r
+ EFI_IDE_CONTROLLER_NOTIFY_PHASE NotifyPhase;\r
+ \r
+ ///\r
+ /// Submits the Drive Identify data that was returned by the device.\r
+ ///\r
+ EFI_IDE_CONTROLLER_SUBMIT_DATA SubmitData;\r
+ \r
+ ///\r
+ /// Submits information about modes that should be disqualified. The specified \r
+ /// IDE device does not support these modes and these modes should not be \r
+ /// returned by EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode()\r
+ ///\r
+ EFI_IDE_CONTROLLER_DISQUALIFY_MODE DisqualifyMode;\r
+ \r
+ ///\r
+ /// Calculates and returns the optimum mode for a particular IDE device.\r
+ ///\r
+ EFI_IDE_CONTROLLER_CALCULATE_MODE CalculateMode;\r
+ \r
+ ///\r
+ /// Programs the IDE controller hardware to the default timing or per the modes\r
+ /// that were returned by the last call to EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode(). \r
+ ///\r
+ EFI_IDE_CONTROLLER_SET_TIMING SetTiming;\r
+ \r
+ ///\r
+ /// Set to TRUE if the enumeration group includes all the channels that are\r
+ /// produced by this controller. FALSE if an enumeration group consists of\r
+ /// only one channel. \r
+ ///\r
+ BOOLEAN EnumAll;\r
+ \r
+ ///\r
+ /// The number of channels that are produced by this controller. Parallel ATA\r
+ /// (PATA) controllers can support up to two channels. Advanced Host Controller \r
+ /// Interface (AHCI) Serial ATA (SATA) controllers can support up to 32 channels,\r
+ /// each of which can have up to one device. In the presence of a multiplier, \r
+ /// each channel can have 15 devices.\r
+ ///\r
+ UINT8 ChannelCount;\r
+};\r
+\r
+extern EFI_GUID gEfiIdeControllerInitProtocolGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file declares Incompatible PCI Device Support Protocol\r
+ \r
+ Allows the PCI bus driver to support resource allocation for some PCI devices \r
+ that do not comply with the PCI Specification.\r
+ \r
+ @par Note: \r
+ This protocol is optional. Only those platforms that implement this protocol \r
+ will have the capability to support incompatible PCI devices. The absence of \r
+ this protocol can cause the PCI bus driver to configure these incompatible \r
+ PCI devices incorrectly. As a result, these devices may not work properly. \r
+ \r
+ The EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL is used by the PCI bus driver\r
+ to support resource allocation for some PCI devices that do not comply with the \r
+ PCI Specification. This protocol can find some incompatible PCI devices and \r
+ report their special resource requirements to the PCI bus driver. The generic \r
+ PCI bus driver does not have prior knowledge of any incompatible PCI devices. \r
+ It interfaces with the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL to find out \r
+ if a device is incompatible and to obtain the special configuration requirements \r
+ for a specific incompatible PCI device.\r
+\r
+ This protocol is optional, and only one instance of this protocol can be present\r
+ in the system. If a platform supports this protocol, this protocol is produced \r
+ by a Driver Execution Environment (DXE) driver and must be made available before \r
+ the Boot Device Selection (BDS) phase. The PCI bus driver will look for the \r
+ presence of this protocol before it begins PCI enumeration. If this protocol \r
+ exists in a platform, it indicates that the platform has the capability to support\r
+ those incompatible PCI devices. However, final support for incompatible PCI \r
+ devices still depends on the implementation of the PCI bus driver. The PCI bus \r
+ driver may fully, partially, or not even support these incompatible devices. \r
+\r
+ During PCI bus enumeration, the PCI bus driver will probe the PCI Base Address \r
+ Registers (BARs) for each PCI device regardless of whether the PCI device is \r
+ incompatible or not to determine the resource requirements so that the PCI bus \r
+ driver can invoke the proper PCI resources for them. Generally, this resource \r
+ information includes the following:\r
+ - Resource type\r
+ - Resource length\r
+ - Alignment\r
+ \r
+ However, some incompatible PCI devices may have special requirements. As a result,\r
+ the length or the alignment that is derived through BAR probing may not be exactly \r
+ the same as the actual resource requirement of the device. For example, there \r
+ are some devices that request I/O resources at a length of 0x100 from their I/O\r
+ BAR, but these incompatible devices will never work correctly if an odd I/O base \r
+ address, such as 0x100, 0x300, or 0x500, is assigned to the BAR. Instead, these \r
+ devices request an even base address, such as 0x200 or 0x400. The Incompatible \r
+ PCI Device Support Protocol can then be used to obtain these special resource \r
+ requirements for these incompatible PCI devices. In this way, the PCI bus driver \r
+ will take special consideration for these devices during PCI resource allocation \r
+ to ensure that they can work correctly.\r
+ \r
+ This protocol may support the following incompatible PCI BAR types:\r
+ - I/O or memory length that is different from what the BAR reports\r
+ - I/O or memory alignment that is different from what the BAR reports\r
+ - Fixed I/O or memory base address\r
+ \r
+ See the Conventional PCI Specification 3.0 for the details of how a PCI BAR \r
+ reports the resource length and the alignment that it requires.\r
+\r
+ Copyright (c) 2007 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
+ Volume 5: Standards\r
+\r
+**/\r
+\r
+#ifndef _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_\r
+#define _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_\r
+\r
+///\r
+/// Global ID for EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
+///\r
+#define EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL_GUID \\r
+ { \\r
+ 0xeb23f55a, 0x7863, 0x4ac2, {0x8d, 0x3d, 0x95, 0x65, 0x35, 0xde, 0x03, 0x75} \\r
+ }\r
+\r
+///\r
+/// Forward declaration for EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
+///\r
+typedef struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL;\r
+\r
+/**\r
+ Returns a list of ACPI resource descriptors that detail the special resource\r
+ configuration requirements for an incompatible PCI device.\r
+ \r
+ This function returns a list of ACPI resource descriptors that detail the \r
+ special resource configuration requirements for an incompatible PCI device. \r
+ \r
+ Prior to bus enumeration, the PCI bus driver will look for the presence\r
+ of the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this\r
+ protocol can be present in the system. For each PCI device that the PCI bus \r
+ driver discovers, the PCI bus driver calls this function with the device's vendor\r
+ ID, device ID, revision ID, subsystem vendor ID, and subsystem device ID. If the\r
+ VendorId, DeviceId, RevisionId, SubsystemVendorId, or SubsystemDeviceId value is\r
+ set to (UINTN)-1, that field will be ignored. The ID values that are not (UINTN)-1\r
+ will be used to identify the current device. \r
+ \r
+ This function will only return EFI_SUCCESS. However, if the device is an \r
+ incompatible PCI device, a list of ACPI resource descriptors will be returned \r
+ in Configuration. Otherwise, NULL will be returned in Configuration instead. \r
+ The PCI bus driver does not need to allocate memory for Configuration. However, \r
+ it is the PCI bus driver's responsibility to free it. The PCI bus driver then \r
+ can configure this device with the information that is derived from this list \r
+ of resource nodes, rather than the result of BAR probing.\r
+\r
+ Only the following two resource descriptor types from the ACPI Specification \r
+ may be used to describe the incompatible PCI device resource requirements:\r
+ - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)\r
+ - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)\r
+\r
+ The QWORD Address Space Descriptor can describe memory, I/O, and bus number \r
+ ranges for dynamic or fixed resources. The configuration of a PCI root bridge \r
+ is described with one or more QWORD Address Space Descriptors, followed by an \r
+ End Tag. See the ACPI Specification for details on the field values.\r
+ \r
+ @param[in] This Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL \r
+ instance.\r
+ @param[in] VendorId A unique ID to identify the manufacturer of \r
+ the PCI device. See the Conventional PCI\r
+ Specification 3.0 for details.\r
+ @param[in] DeviceId A unique ID to identify the particular PCI \r
+ device. See the Conventional PCI Specification \r
+ 3.0 for details.\r
+ @param[in] RevisionId A PCI device-specific revision identifier. \r
+ See the Conventional PCI Specification 3.0\r
+ for details.\r
+ @param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the \r
+ Conventional PCI Specification 3.0 for details.\r
+ @param[in] SubsystemDeviceId Specifies the subsystem device ID. See the \r
+ Conventional PCI Specification 3.0 for details.\r
+ @param[out] Configuration A list of ACPI resource descriptors that detail\r
+ the configuration requirement.\r
+\r
+ @retval EFI_SUCCESS The function always returns EFI_SUCCESS.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE)(\r
+ IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,\r
+ IN UINTN VendorId,\r
+ IN UINTN DeviceId,\r
+ IN UINTN RevisionId,\r
+ IN UINTN SubsystemVendorId,\r
+ IN UINTN SubsystemDeviceId,\r
+ OUT VOID **Configuration\r
+ );\r
+\r
+///\r
+/// Interface structure for the Incompatible PCI Device Support Protocol\r
+///\r
+struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL {\r
+ ///\r
+ /// Returns a list of ACPI resource descriptors that detail any special\r
+ /// resource configuration requirements if the specified device is a recognized\r
+ /// incompatible PCI device.\r
+ ///\r
+ EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE CheckDevice;\r
+};\r
+\r
+extern EFI_GUID gEfiIncompatiblePciDeviceSupportProtocolGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file declares PCI Host Bridge Resource Allocation Protocol which \r
+ provides the basic interfaces to abstract a PCI host bridge resource allocation. \r
+ This protocol is mandatory if the system includes PCI devices.\r
+ \r
+ Copyright (c) 2007 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
+ Volume 5: Standards\r
+ \r
+**/\r
+\r
+#ifndef _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
+#define _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_\r
+\r
+//\r
+// This file must be included because EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+// uses EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS\r
+//\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+///\r
+/// Global ID for the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+///\r
+#define EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID \\r
+ { \\r
+ 0xCF8034BE, 0x6768, 0x4d8b, {0xB7,0x39,0x7C,0xCE,0x68,0x3A,0x9F,0xBE } \\r
+ }\r
+\r
+///\r
+/// Forward declaration for EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+///\r
+typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL;\r
+\r
+/// If this bit is set, then the PCI Root Bridge does not\r
+/// support separate windows for Non-prefetchable and Prefetchable\r
+/// memory. A PCI bus driver needs to include requests for Prefetchable\r
+/// memory in the Non-prefetchable memory pool.\r
+///\r
+#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 1\r
+\r
+///\r
+/// If this bit is set, then the PCI Root Bridge supports\r
+/// 64 bit memory windows. If this bit is not set,\r
+/// the PCI bus driver needs to include requests for 64 bit\r
+/// memory address in the corresponding 32 bit memory pool.\r
+///\r
+#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2\r
+\r
+///\r
+/// A UINT64 value that contains the status of a PCI resource requested \r
+/// in the Configuration parameter returned by GetProposedResources()\r
+/// The legal values are EFI_RESOURCE_SATISFIED and EFI_RESOURCE_NOT_SATISFIED\r
+///\r
+typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;\r
+\r
+///\r
+/// The request of this resource type could be fulfilled. Used in the \r
+/// Configuration parameter returned by GetProposedResources() to identify\r
+/// a PCI resources request that can be satisfied.\r
+///\r
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
+\r
+///\r
+/// The request of this resource type could not be fulfilled for its\r
+/// absence in the host bridge resource pool. Used in the Configuration parameter \r
+/// returned by GetProposedResources() to identify a PCI resources request that\r
+/// can not be satisfied.\r
+///\r
+#define EFI_RESOURCE_NOT_SATISFIED 0xFFFFFFFFFFFFFFFFULL\r
+\r
+///\r
+/// This enum is used to specify the phase of the PCI enumaeration process\r
+///\r
+typedef enum {\r
+ ///\r
+ /// Reset the host bridge PCI apertures and internal data structures.\r
+ /// PCI enumerator should issue this notification before starting fresh\r
+ /// enumeration process. Enumeration cannot be restarted after sending\r
+ /// any other notification such as EfiPciHostBridgeBeginBusAllocation.\r
+ ///\r
+ EfiPciHostBridgeBeginEnumeration,\r
+\r
+ ///\r
+ /// The bus allocation phase is about to begin. No specific action\r
+ /// is required here. This notification can be used to perform any\r
+ /// chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeBeginBusAllocation,\r
+\r
+ ///\r
+ /// The bus allocation and bus programming phase is complete. No specific\r
+ /// action is required here. This notification can be used to perform any\r
+ /// chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeEndBusAllocation,\r
+ \r
+ ///\r
+ /// The resource allocation phase is about to begin.No specific action is\r
+ /// required here. This notification can be used to perform any chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeBeginResourceAllocation,\r
+ \r
+ ///\r
+ /// Allocate resources per previously submitted requests for all the PCI Root\r
+ /// Bridges. These resource settings are returned on the next call to\r
+ /// GetProposedResources(). \r
+ ///\r
+ EfiPciHostBridgeAllocateResources,\r
+ \r
+ ///\r
+ /// Program the Host Bridge hardware to decode previously allocated resources\r
+ /// (proposed resources) for all the PCI Root Bridges.\r
+ ///\r
+ EfiPciHostBridgeSetResources,\r
+ \r
+ ///\r
+ /// De-allocate previously allocated resources previously for all the PCI\r
+ /// Root Bridges and reset the I/O and memory apertures to initial state. \r
+ ///\r
+ EfiPciHostBridgeFreeResources,\r
+ \r
+ ///\r
+ /// The resource allocation phase is completed. No specific action is required\r
+ /// here. This notification can be used to perform any chipset specific programming. \r
+ ///\r
+ EfiPciHostBridgeEndResourceAllocation\r
+} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE;\r
+\r
+///\r
+/// Definitions of 2 notification points.\r
+///\r
+typedef enum {\r
+ ///\r
+ /// This notification is only applicable to PCI-PCI bridges and\r
+ /// indicates that the PCI enumerator is about to begin enumerating\r
+ /// the bus behind the PCI-PCI Bridge. This notification is sent after\r
+ /// the primary bus number, the secondary bus number and the subordinate\r
+ /// bus number registers in the PCI-PCI Bridge are programmed to valid\r
+ /// (not necessary final) values\r
+ ///\r
+ EfiPciBeforeChildBusEnumeration,\r
+\r
+ ///\r
+ /// This notification is sent before the PCI enumerator probes BAR registers\r
+ /// for every valid PCI function. \r
+ ///\r
+ EfiPciBeforeResourceCollection\r
+} EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE;\r
+\r
+/**\r
+ These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI \r
+ enumeration process.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] Phase The phase during enumeration\r
+\r
+ @retval EFI_SUCCESS The notification was accepted without any errors.\r
+ @retval EFI_INVALID_PARAMETER The Phase is invalid.\r
+ @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error \r
+ is valid for a Phase of EfiPciHostBridgeAllocateResources if \r
+ SubmitResources() has not been called for one or more \r
+ PCI root bridges before this call.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid for \r
+ a Phase of EfiPciHostBridgeSetResources.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
+ This error is valid for a Phase of EfiPciHostBridgeAllocateResources\r
+ if the previously submitted resource requests cannot be fulfilled or were only \r
+ partially fulfilled\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
+ );\r
+\r
+/**\r
+ Returns the device handle of the next PCI root bridge that is associated with this host bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in,out] RootBridgeHandle Returns the device handle of the next PCI root bridge. On input, it holds the \r
+ RootBridgeHandle that was returned by the most recent call to \r
+ GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle \r
+ for the first PCI root bridge is returned.\r
+\r
+ @retval EFI_SUCCESS The requested attribute information was returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was returned \r
+ on a previous call to GetNextRootBridge().\r
+ @retval EFI_NOT_FOUND There are no more PCI root bridge device handles.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN OUT EFI_HANDLE *RootBridgeHandle\r
+ );\r
+\r
+/**\r
+ Returns the allocation attributes of a PCI root bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested.\r
+ @param[out] Attribute The pointer to attributes of the PCI root bridge.\r
+\r
+ @retval EFI_SUCCESS The requested attribute information was returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Attributes is NULL.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT UINT64 *Attributes\r
+ );\r
+\r
+/**\r
+ Sets up the specified PCI root bridge for the bus enumeration process.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge to be set up.\r
+ @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The PCI root bridge was set up and the bus range was returned in \r
+ Configuration.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ );\r
+\r
+/**\r
+ Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ instance. \r
+ @param[in] RootBridgeHandle The PCI root bridge whose bus range is to be programmed.\r
+ @param[in] Configuration The pointer to the PCI bus resource descriptor..\r
+\r
+ @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
+ resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource\r
+ descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI (2.0 & 3.0) resource \r
+ descriptors other than bus descriptors.\r
+ @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource \r
+ descriptors.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ );\r
+\r
+/**\r
+ Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being \r
+ submitted.\r
+ @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were \r
+ accepted.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
+ @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) \r
+ resource descriptor.\r
+ @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource \r
+ types that are not supported by this PCI root bridge. This error will \r
+ happen if the caller did not combine resources according to \r
+ Attributes that were returned by GetAllocAttributes().\r
+ @retval EFI_INVALID_PARAMETER "Address Range Maximum" is invalid.\r
+ @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
+ @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
+ \r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ );\r
+\r
+/**\r
+ Returns the proposed resource settings for the specified PCI root bridge.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL \r
+ instance.\r
+ @param[in] RootBridgeHandle The PCI root bridge handle.\r
+ @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ );\r
+\r
+/**\r
+ Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various \r
+ stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual \r
+ PCI controllers before enumeration.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ @param[in] RootBridgeHandle The associated PCI root bridge handle.\r
+ @param[in] PciAddress The address of the PCI device on the PCI bus.\r
+ @param[in] Phase The phase of the PCI device enumeration.\r
+\r
+ @retval EFI_SUCCESS The requested parameters were returned.\r
+ @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
+ @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in \r
+ EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
+ @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator \r
+ should not enumerate this device, including its child devices if it is \r
+ a PCI-to-PCI bridge.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER)(\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ );\r
+\r
+///\r
+/// Provides the basic interfaces to abstract a PCI host bridge resource allocation.\r
+///\r
+struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL {\r
+ ///\r
+ /// The notification from the PCI bus enumerator that it is about to enter\r
+ /// a certain phase during the enumeration process.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase;\r
+ \r
+ ///\r
+ /// Retrieves the device handle for the next PCI root bridge that is produced by the\r
+ /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached. \r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge;\r
+ \r
+ ///\r
+ /// Retrieves the allocation-related attributes of a PCI root bridge.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes;\r
+ \r
+ ///\r
+ /// Sets up a PCI root bridge for bus enumeration.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration;\r
+ \r
+ ///\r
+ /// Sets up the PCI root bridge so that it decodes a specific range of bus numbers.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers;\r
+ \r
+ ///\r
+ /// Submits the resource requirements for the specified PCI root bridge.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources;\r
+ \r
+ ///\r
+ /// Returns the proposed resource assignment for the specified PCI root bridges.\r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;\r
+ \r
+ ///\r
+ /// Provides hooks from the PCI bus driver to every PCI controller\r
+ /// (device/function) at various stages of the PCI enumeration process that\r
+ /// allow the host bridge driver to preinitialize individual PCI controllers\r
+ /// before enumeration. \r
+ ///\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController;\r
+};\r
+\r
+extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file declares EFI PCI Hot Plug Init Protocol.\r
+ \r
+ This protocol provides the necessary functionality to initialize the Hot Plug \r
+ Controllers (HPCs) and the buses that they control. This protocol also provides \r
+ information regarding resource padding.\r
+ \r
+ @par Note: \r
+ This protocol is required only on platforms that support one or more PCI Hot\r
+ Plug* slots or CardBus sockets. \r
+\r
+ The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus enumerator\r
+ to properly initialize the HPCs and CardBus sockets that require initialization. \r
+ The HPC initialization takes place before the PCI enumeration process is complete. \r
+ There cannot be more than one instance of this protocol in a system. This protocol \r
+ is installed on its own separate handle. \r
+ \r
+ Because the system may include multiple HPCs, one instance of this protocol \r
+ should represent all of them. The protocol functions use the device path of \r
+ the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it \r
+ will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If InitializeRootHpc()\r
+ is unable to initialize a root HPC, the PCI enumerator will ignore that root HPC \r
+ and continue the enumeration process. If the HPC is not initialized, the devices \r
+ that it controls may not be initialized, and no resource padding will be provided.\r
+\r
+ From the standpoint of the PCI bus enumerator, HPCs are divided into the following \r
+ two classes:\r
+\r
+ - Root HPC:\r
+ These HPCs must be initialized by calling InitializeRootHpc() during the \r
+ enumeration process. These HPCs will also require resource padding. The \r
+ platform code must have a priori knowledge of these devices and must know \r
+ how to initialize them. There may not be any way to access their PCI \r
+ configuration space before the PCI enumerator programs all the upstream\r
+ bridges and thus enables the path to these devices. The PCI bus enumerator \r
+ is responsible for determining the PCI bus address of the HPC before it \r
+ calls InitializeRootHpc().\r
+ - Nonroot HPC:\r
+ These HPCs will not need explicit initialization during enumeration process. \r
+ These HPCs will require resource padding. The platform code does not have \r
+ to have a priori knowledge of these devices.\r
+\r
+ Copyright (c) 2007 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
+ Volume 5: Standards\r
+\r
+**/\r
+\r
+#ifndef _EFI_PCI_HOT_PLUG_INIT_H_\r
+#define _EFI_PCI_HOT_PLUG_INIT_H_\r
+\r
+///\r
+/// Global ID for the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
+///\r
+#define EFI_PCI_HOT_PLUG_INIT_PROTOCOL_GUID \\r
+ { \\r
+ 0xaa0e8bc1, 0xdabc, 0x46b0, {0xa8, 0x44, 0x37, 0xb8, 0x16, 0x9b, 0x2b, 0xea } \\r
+ }\r
+\r
+///\r
+/// Forward declaration for EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
+///\r
+typedef struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL EFI_PCI_HOT_PLUG_INIT_PROTOCOL;\r
+\r
+///\r
+/// Describes the current state of an HPC\r
+///\r
+typedef UINT16 EFI_HPC_STATE;\r
+\r
+///\r
+/// The HPC initialization function was called and the HPC completed \r
+/// initialization, but it was not enabled for some reason. The HPC may be \r
+/// disabled in hardware, or it may be disabled due to user preferences, \r
+/// hardware failure, or other reasons. No resource padding is required.\r
+///\r
+#define EFI_HPC_STATE_INITIALIZED 0x01\r
+\r
+///\r
+/// The HPC initialization function was called, the HPC completed \r
+/// initialization, and it was enabled. Resource padding is required.\r
+///\r
+#define EFI_HPC_STATE_ENABLED 0x02\r
+\r
+///\r
+/// Location definition for PCI Hot Plug Controller\r
+///\r
+typedef struct{\r
+ ///\r
+ /// \r
+ /// The device path to the root HPC. An HPC cannot control its parent buses.\r
+ /// The PCI bus driver requires this information so that it can pass the \r
+ /// correct HpcPciAddress to the InitializeRootHpc() and GetResourcePadding() \r
+ /// functions. \r
+ ///\r
+ EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath;\r
+ ///\r
+ /// The device path to the Hot Plug Bus (HPB) that is controlled by the root \r
+ /// HPC. The PCI bus driver uses this information to check if a particular PCI \r
+ /// bus has hot-plug slots. The device path of a PCI bus is the same as the \r
+ /// device path of its parent. For Standard(PCI) Hot Plug Controllers (SHPCs) \r
+ /// and PCI Express*, HpbDevicePath is the same as HpcDevicePath.\r
+ ///\r
+ EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath;\r
+} EFI_HPC_LOCATION;\r
+\r
+///\r
+/// Describes how resource padding should be applied\r
+///\r
+typedef enum {\r
+ ///\r
+ /// Apply the padding at a PCI bus level. In other words, the resources\r
+ /// that are allocated to the bus containing hot-plug slots are padded by\r
+ /// the specified amount. If the hot-plug bus is behind a PCI-to-PCI\r
+ /// bridge, the PCI-to-PCI bridge apertures will indicate the padding\r
+ ///\r
+ EfiPaddingPciBus,\r
+ ///\r
+ /// Apply the padding at a PCI root bridge level. If a PCI root bridge\r
+ /// includes more than one hot-plug bus, the resource padding requests\r
+ /// for these buses are added together and the resources that are\r
+ /// allocated to the root bridge are padded by the specified amount. This\r
+ /// strategy may reduce the total amount of padding, but requires\r
+ /// reprogramming of PCI-to-PCI bridges in a hot-add event. If the hotplug\r
+ /// bus is behind a PCI-to-PCI bridge, the PCI-to-PCI bridge\r
+ /// apertures do not indicate the padding for that bus. \r
+ ///\r
+ EfiPaddingPciRootBridge\r
+} EFI_HPC_PADDING_ATTRIBUTES;\r
+\r
+/**\r
+ Returns a list of root Hot Plug Controllers (HPCs) that require initialization\r
+ during the boot process.\r
+\r
+ This procedure returns a list of root HPCs. The PCI bus driver must initialize \r
+ these controllers during the boot process. The PCI bus driver may or may not be \r
+ able to detect these HPCs. If the platform includes a PCI-to-CardBus bridge, it \r
+ can be included in this list if it requires initialization. The HpcList must be \r
+ self consistent. An HPC cannot control any of its parent buses. Only one HPC can \r
+ control a PCI bus. Because this list includes only root HPCs, no HPC in the list \r
+ can be a child of another HPC. This policy must be enforced by the \r
+ EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The PCI bus driver may not check for such \r
+ invalid conditions. The callee allocates the buffer HpcList\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.\r
+ @param[out] HpcCount The number of root HPCs that were returned.\r
+ @param[out] HpcList The list of root HPCs. HpcCount defines the number of\r
+ elements in this list.\r
+\r
+ @retval EFI_SUCCESS HpcList was returned.\r
+ @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient \r
+ resources.\r
+ @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_GET_ROOT_HPC_LIST)(\r
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
+ OUT UINTN *HpcCount,\r
+ OUT EFI_HPC_LOCATION **HpcList\r
+ );\r
+\r
+/**\r
+ Initializes one root Hot Plug Controller (HPC). This process may causes\r
+ initialization of its subordinate buses.\r
+ \r
+ This function initializes the specified HPC. At the end of initialization, \r
+ the hot-plug slots or sockets (controlled by this HPC) are powered and are \r
+ connected to the bus. All the necessary registers in the HPC are set up. For \r
+ a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set \r
+ up are defined in the PCI Standard Hot Plug Controller and Subsystem \r
+ Specification. \r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.\r
+ @param[in] HpcDevicePath The device path to the HPC that is being initialized.\r
+ @param[in] HpcPciAddress The address of the HPC function on the PCI bus.\r
+ @param[in] Event The event that should be signaled when the HPC \r
+ initialization is complete. Set to NULL if the \r
+ caller wants to wait until the entire initialization \r
+ process is complete.\r
+ @param[out] HpcState The state of the HPC hardware. The state is \r
+ EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_ENABLED.\r
+\r
+ @retval EFI_SUCCESS If Event is NULL, the specific HPC was successfully\r
+ initialized. If Event is not NULL, Event will be \r
+ signaled at a later time when initialization is complete.\r
+ @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
+ does not support the specified HPC.\r
+ @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient\r
+ resources.\r
+ @retval EFI_INVALID_PARAMETER HpcState is NULL.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_INITIALIZE_ROOT_HPC)(\r
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r
+ IN UINT64 HpcPciAddress,\r
+ IN EFI_EVENT Event, OPTIONAL\r
+ OUT EFI_HPC_STATE *HpcState\r
+ );\r
+\r
+/**\r
+ Returns the resource padding that is required by the PCI bus that is controlled\r
+ by the specified Hot Plug Controller (HPC).\r
+\r
+ This function returns the resource padding that is required by the PCI bus that\r
+ is controlled by the specified HPC. This member function is called for all the \r
+ root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This \r
+ function will be called before PCI resource allocation is completed. This function \r
+ must be called after all the root HPCs, with the possible exception of a \r
+ PCI-to-CardBus bridge, have completed initialization.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.\r
+ @param[in] HpcDevicePath The device path to the HPC.\r
+ @param[in] HpcPciAddress The address of the HPC function on the PCI bus.\r
+ @param[in] HpcState The state of the HPC hardware.\r
+ @param[out] Padding The amount of resource padding that is required by the\r
+ PCI bus under the control of the specified HPC.\r
+ @param[out] Attributes Describes how padding is accounted for. The padding\r
+ is returned in the form of ACPI 2.0 resource descriptors.\r
+\r
+ @retval EFI_SUCCESS The resource padding was successfully returned.\r
+ @retval EFI_UNSUPPORTED This instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r
+ does not support the specified HPC.\r
+ @retval EFI_NOT_READY This function was called before HPC initialization\r
+ is complete.\r
+ @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL.\r
+ @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding\r
+ cannot be allocated due to insufficient resources.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_GET_HOT_PLUG_PADDING)(\r
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r
+ IN UINT64 HpcPciAddress,\r
+ OUT EFI_HPC_STATE *HpcState,\r
+ OUT VOID **Padding,\r
+ OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes\r
+ );\r
+\r
+///\r
+/// This protocol provides the necessary functionality to initialize the\r
+/// Hot Plug Controllers (HPCs) and the buses that they control. This protocol\r
+/// also provides information regarding resource padding.\r
+///\r
+struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL {\r
+ ///\r
+ /// Returns a list of root HPCs and the buses that they control.\r
+ ///\r
+ EFI_GET_ROOT_HPC_LIST GetRootHpcList;\r
+ \r
+ ///\r
+ /// Initializes the specified root HPC.\r
+ ///\r
+ EFI_INITIALIZE_ROOT_HPC InitializeRootHpc;\r
+ \r
+ ///\r
+ /// Returns the resource padding that is required by the HPC.\r
+ ///\r
+ EFI_GET_HOT_PLUG_PADDING GetResourcePadding;\r
+};\r
+\r
+extern EFI_GUID gEfiPciHotPlugInitProtocolGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file declares PlatfromOpRom protocols which provides the interface between \r
+ the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific \r
+ driver to describe the unique features of a platform. This\r
+ protocol is optional.\r
+ \r
+ Copyright (c) 2007 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r
+ Volume 5: Standards\r
+\r
+**/\r
+\r
+#ifndef _PCI_PLATFORM_H_\r
+#define _PCI_PLATFORM_H_\r
+\r
+///\r
+/// This file must be included because the EFI_PCI_PLATFORM_PROTOCOL uses\r
+/// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE\r
+///\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+\r
+///\r
+/// Global ID for the EFI_PCI_PLATFORM_PROTOCOL\r
+///\r
+#define EFI_PCI_PLATFORM_PROTOCOL_GUID \\r
+ { \\r
+ 0x7d75280, 0x27d4, 0x4d69, {0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41} \\r
+ }\r
+\r
+///\r
+/// Forward declaration for EFI_PCI_PLATFORM_PROTOCOL\r
+///\r
+typedef struct _EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_PLATFORM_PROTOCOL;\r
+\r
+///\r
+/// EFI_PCI_PLATYFORM_POLICY that is a bitmask with the following legal combinations:\r
+/// - EFI_RESERVE_NONE_IO_ALIAS:<BR>\r
+/// Does not set aside either ISA or VGA I/O resources during PCI\r
+/// enumeration. By using this selection, the platform indicates that it does\r
+/// not want to support a PCI device that requires ISA or legacy VGA\r
+/// resources. If a PCI device driver asks for these resources, the request\r
+/// will be turned down.\r
+/// - EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r
+/// Sets aside the ISA I/O range and all the aliases during PCI\r
+/// enumeration. VGA I/O ranges and aliases are included in ISA alias\r
+/// ranges. In this scheme, 75 percent of the I/O space remains unused.\r
+/// By using this selection, the platform indicates that it wants to support\r
+/// PCI devices that require the following, at the cost of wasted I/O space:\r
+/// ISA range and its aliases\r
+/// Legacy VGA range and its aliases\r
+/// The PCI bus driver will not allocate I/O addresses out of the ISA I/O\r
+/// range and its aliases. The following are the ISA I/O ranges:\r
+/// - n100..n3FF\r
+/// - n500..n7FF\r
+/// - n900..nBFF\r
+/// - nD00..nFFF\r
+///\r
+/// In this case, the PCI bus driver will ask the PCI host bridge driver for\r
+/// larger I/O ranges. The PCI host bridge driver is not aware of the ISA\r
+/// aliasing policy and merely attempts to allocate the requested ranges.\r
+/// The first device that requests the legacy VGA range will get all the\r
+/// legacy VGA range plus its aliased addresses forwarded to it. The first\r
+/// device that requests the legacy ISA range will get all the legacy ISA\r
+/// range plus its aliased addresses forwarded to it.\r
+/// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:<BR>\r
+/// Sets aside the ISA I/O range (0x100\960x3FF) during PCI enumeration\r
+/// and the aliases of the VGA I/O ranges. By using this selection, the\r
+/// platform indicates that it will support VGA devices that require VGA\r
+/// ranges, including those that require VGA aliases. The platform further\r
+/// wants to support non-VGA devices that ask for the ISA range (0x100\96\r
+/// 3FF), but not if it also asks for the ISA aliases. The PCI bus driver will\r
+/// not allocate I/O addresses out of the legacy ISA I/O range (0x100\96\r
+/// 0x3FF) range or the aliases of the VGA I/O range. If a PCI device\r
+/// driver asks for the ISA I/O ranges, including aliases, the request will be\r
+/// turned down. The first device that requests the legacy VGA range will\r
+/// get all the legacy VGA range plus its aliased addresses forwarded to\r
+/// it. When the legacy VGA device asks for legacy VGA ranges and its\r
+/// aliases, all the upstream PCI-to-PCI bridges must be set up to perform\r
+/// 10-bit decode on legacy VGA ranges. To prevent two bridges from\r
+/// positively decoding the same address, all PCI-to-PCI bridges that are\r
+/// peers to this bridge will have to be set up to not decode ISA aliased\r
+/// ranges. In that case, all the devices behind the peer bridges can\r
+/// occupy only I/O addresses that are not ISA aliases. This is a limitation\r
+/// of PCI-to-PCI bridges and is described in the white paper PCI-to-PCI\r
+/// Bridges and Card Bus Controllers on Windows 2000, Windows XP,\r
+/// and Windows Server 2003. The PCI enumeration process must be\r
+/// cognizant of this restriction.\r
+/// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS:<BR>\r
+/// Sets aside the ISA I/O range (0x100\960x3FF) during PCI enumeration.\r
+/// VGA I/O ranges are included in the ISA range. By using this selection,\r
+/// the platform indicates that it wants to support PCI devices that require\r
+/// the ISA range and legacy VGA range, but it does not want to support\r
+/// devices that require ISA alias ranges or VGA alias ranges. The PCI\r
+/// bus driver will not allocate I/O addresses out of the legacy ISA I/O\r
+/// range (0x100\960x3FF). If a PCI device driver asks for the ISA I/O\r
+/// ranges, including aliases, the request will be turned down. By using\r
+/// this selection, the platform indicates that it will support VGA devices\r
+/// that require VGA ranges, but it will not support VGA devices that\r
+/// require VGA aliases. To truly support 16-bit VGA decode, all the PCIto-\r
+/// PCI bridges that are upstream to a VGA device, as well as\r
+/// upstream to the parent PCI root bridge, must support 16-bit VGA I/O\r
+/// decode. See the PCI-to-PCI Bridge Architecture Specification for\r
+/// information regarding the 16-bit VGA decode support. This\r
+/// requirement must hold true for every VGA device in the system. If any\r
+/// of these bridges does not support 16-bit VGA decode, it will positively\r
+/// decode all the aliases of the VGA I/O ranges and this selection must\r
+/// be treated like EFI_RESERVE_ISA_IO_NO_ALIAS |\r
+/// EFI_RESERVE_VGA_IO_ALIAS.\r
+///\r
+typedef UINT32 EFI_PCI_PLATFORM_POLICY;\r
+\r
+///\r
+/// Does not set aside either ISA or VGA I/O resources during PCI\r
+/// enumeration.\r
+///\r
+#define EFI_RESERVE_NONE_IO_ALIAS 0x0000\r
+\r
+///\r
+/// Sets aside ISA I/O range and all aliases\r
+/// - n100..n3FF\r
+/// - n500..n7FF\r
+/// - n900..nBFF\r
+/// - nD00..nFFF\r
+///\r
+#define EFI_RESERVE_ISA_IO_ALIAS 0x0001\r
+\r
+///\r
+/// Sets aside ISA I/O range 0x100-0x3FF\r
+///\r
+#define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002\r
+\r
+///\r
+/// Sets aside VGA I/O ranges and all aliases\r
+///\r
+#define EFI_RESERVE_VGA_IO_ALIAS 0x0004\r
+\r
+///\r
+/// Sets aside VGA I/O rangess\r
+///\r
+#define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008\r
+\r
+///\r
+/// EFI_PCI_EXECUTION_PHASE is used to call a platform protocol and execute\r
+/// platform-specific code.\r
+///\r
+typedef enum {\r
+ ///\r
+ /// The phase that indicates the entry point to the PCI Bus Notify phase. This\r
+ /// platform hook is called before the PCI bus driver calls the\r
+ /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.\r
+ ///\r
+ BeforePciHostBridge = 0,\r
+ ///\r
+ /// The phase that indicates the entry point to the PCI Bus Notify phase. This\r
+ /// platform hook is called before the PCI bus driver calls the\r
+ /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver.\r
+ ///\r
+ ChipsetEntry = 0,\r
+ ///\r
+ /// The phase that indicates the exit point to the Chipset Notify phase before\r
+ /// returning to the PCI Bus Driver Notify phase. This platform hook is called after\r
+ /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ /// driver.\r
+ ///\r
+ AfterPciHostBridge = 1,\r
+ ///\r
+ /// The phase that indicates the exit point to the Chipset Notify phase before\r
+ /// returning to the PCI Bus Driver Notify phase. This platform hook is called after\r
+ /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ /// driver.\r
+ ///\r
+ ChipsetExit = 1,\r
+ MaximumChipsetPhase\r
+} EFI_PCI_EXECUTION_PHASE;\r
+\r
+typedef EFI_PCI_EXECUTION_PHASE EFI_PCI_CHIPSET_EXECUTION_PHASE;\r
+\r
+/**\r
+ The notification from the PCI bus enumerator to the platform that it is\r
+ about to enter a certain phase during the enumeration process.\r
+\r
+ The PlatformNotify() function can be used to notify the platform driver so that\r
+ it can perform platform-specific actions. No specific actions are required.\r
+ Eight notification points are defined at this time. More synchronization points\r
+ may be added as required in the future. The PCI bus driver calls the platform driver\r
+ twice for every Phase-once before the PCI Host Bridge Resource Allocation Protocol\r
+ driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol\r
+ driver has been notified.\r
+ This member function may not perform any error checking on the input parameters. It\r
+ also does not return any error codes. If this member function detects any error condition,\r
+ it needs to handle those errors on its own because there is no way to surface any\r
+ errors to the caller.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
+ @param[in] HostBridge The handle of the host bridge controller.\r
+ @param[in] Phase The phase of the PCI bus enumeration.\r
+ @param[in] ChipsetPhase Defines the execution phase of the PCI chipset driver.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_PLATFORM_PHASE_NOTIFY)(\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE HostBridge,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,\r
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
+ );\r
+\r
+/**\r
+ The notification from the PCI bus enumerator to the platform for each PCI\r
+ controller at several predefined points during PCI controller initialization.\r
+\r
+ The PlatformPrepController() function can be used to notify the platform driver so that\r
+ it can perform platform-specific actions. No specific actions are required.\r
+ Several notification points are defined at this time. More synchronization points may be\r
+ added as required in the future. The PCI bus driver calls the platform driver twice for\r
+ every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver\r
+ is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has\r
+ been notified.\r
+ This member function may not perform any error checking on the input parameters. It also\r
+ does not return any error codes. If this member function detects any error condition, it\r
+ needs to handle those errors on its own because there is no way to surface any errors to\r
+ the caller.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
+ @param[in] HostBridge The associated PCI host bridge handle.\r
+ @param[in] RootBridge The associated PCI root bridge handle.\r
+ @param[in] PciAddress The address of the PCI device on the PCI bus.\r
+ @param[in] Phase The phase of the PCI controller enumeration.\r
+ @param[in] ChipsetPhase Defines the execution phase of the PCI chipset driver.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER)(\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE HostBridge,\r
+ IN EFI_HANDLE RootBridge,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,\r
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
+ );\r
+\r
+/**\r
+ Retrieves the platform policy regarding enumeration.\r
+\r
+ The GetPlatformPolicy() function retrieves the platform policy regarding PCI\r
+ enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol\r
+ driver can call this member function to retrieve the policy.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
+ @param[out] PciPolicy The platform policy with respect to VGA and ISA aliasing.\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+ @retval EFI_INVALID_PARAMETER PciPolicy is NULL.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_PLATFORM_GET_PLATFORM_POLICY)(\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy\r
+ );\r
+\r
+/**\r
+ Gets the PCI device's option ROM from a platform-specific location.\r
+\r
+ The GetPciRom() function gets the PCI device's option ROM from a platform-specific location.\r
+ The option ROM will be loaded into memory. This member function is used to return an image\r
+ that is packaged as a PCI 2.2 option ROM. The image may contain both legacy and EFI option\r
+ ROMs. See the UEFI 2.0 Specification for details. This member function can be used to return\r
+ option ROM images for embedded controllers. Option ROMs for embedded controllers are typically\r
+ stored in platform-specific storage, and this member function can retrieve it from that storage\r
+ and return it to the PCI bus driver. The PCI bus driver will call this member function before\r
+ scanning the ROM that is attached to any controller, which allows a platform to specify a ROM\r
+ image that is different from the ROM image on a PCI card.\r
+\r
+ @param[in] This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.\r
+ @param[in] PciHandle The handle of the PCI device.\r
+ @param[out] RomImage If the call succeeds, the pointer to the pointer to the option ROM image.\r
+ Otherwise, this field is undefined. The memory for RomImage is allocated\r
+ by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using the EFI Boot Service AllocatePool().\r
+ It is the caller's responsibility to free the memory using the EFI Boot Service\r
+ FreePool(), when the caller is done with the option ROM.\r
+ @param[out] RomSize If the call succeeds, a pointer to the size of the option ROM size. Otherwise,\r
+ this field is undefined.\r
+\r
+ @retval EFI_SUCCESS The option ROM was available for this device and loaded into memory.\r
+ @retval EFI_NOT_FOUND No option ROM was available for this device.\r
+ @retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM.\r
+ @retval EFI_DEVICE_ERROR An error occurred in getting the option ROM.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCI_PLATFORM_GET_PCI_ROM)(\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE PciHandle,\r
+ OUT VOID **RomImage,\r
+ OUT UINTN *RomSize\r
+ );\r
+\r
+///\r
+/// This protocol provides the interface between the PCI bus driver/PCI Host\r
+/// Bridge Resource Allocation driver and a platform-specific driver to describe\r
+/// the unique features of a platform.\r
+///\r
+struct _EFI_PCI_PLATFORM_PROTOCOL {\r
+ ///\r
+ /// The notification from the PCI bus enumerator to the platform that it is about to \r
+ /// enter a certain phase during the enumeration process.\r
+ ///\r
+ EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify;\r
+ ///\r
+ /// The notification from the PCI bus enumerator to the platform for each PCI \r
+ /// controller at several predefined points during PCI controller initialization.\r
+ /// \r
+ EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;\r
+ /// \r
+ /// Retrieves the platform policy regarding enumeration.\r
+ ///\r
+ EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy;\r
+ ///\r
+ /// Gets the PCI device\92s option ROM from a platform-specific location.\r
+ ///\r
+ EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom;\r
+};\r
+\r
+extern EFI_GUID gEfiPciPlatformProtocolGuid;\r
+\r
+#endif\r
## Include/Protocol/MpService.h\r
gEfiMpServiceProtocolGuid = { 0x3fdda605, 0xa76e, 0x4f46, { 0xad, 0x29, 0x12, 0xf4, 0x53, 0x1b, 0x3d, 0x08 }}\r
\r
+ ## Include/Protocol/PciHostBridgeResourceAllocation.h\r
+ gEfiPciHostBridgeResourceAllocationProtocolGuid = { 0xCF8034BE, 0x6768, 0x4d8b, { 0xb7, 0x39, 0x7c, 0xce, 0x68, 0x3a, 0x9f, 0xbe }}\r
+\r
+ ## Include/Protocol/PciPlatform.h\r
+ gEfiPciPlatformProtocolGuid = { 0x07d75280, 0x27d4, 0x4d69, { 0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41 }}\r
+\r
+ ## Include/Protocol/IncompatiblePciDeviceSupport.h\r
+ gEfiIncompatiblePciDeviceSupportProtocolGuid = { 0xeb23f55a, 0x7863, 0x4ac2, { 0x8d, 0x3d, 0x95, 0x65, 0x35, 0xde, 0x03, 0x75 }}\r
+ \r
+ ## Include/Protocol/PciHotPlugInit.h\r
+ gEfiPciHotPlugInitProtocolGuid = { 0xaa0e8bc1, 0xdabc, 0x46b0, { 0xa8, 0x44, 0x37, 0xb8, 0x16, 0x9b, 0x2b, 0xea }}\r
+ \r
## This protocol is used to add or remove all PCI child devices on the PCI root bridge.\r
## Include/Protocol/PciHotPlugRequest.h\r
gEfiPciHotPlugRequestProtocolGuid = { 0x19CB87AB, 0x2CB9, 0x4665, { 0x83, 0x60, 0xDD, 0xCF, 0x60, 0x54, 0xF7, 0x9D }}\r
-\r
+ \r
+ ## Include/Protocol/IdeControllerInit.h\r
+ gEfiIdeControllerInitProtocolGuid = { 0xa1e37052, 0x80d9, 0x4e65, { 0xa3, 0x17, 0x3e, 0x9a, 0x55, 0xc4, 0x3e, 0xc9 }}\r
+ \r
## Disk Info protocol is used to export Inquiry Data for a drive.\r
## Include/Protocol/DiskInfo.h\r
gEfiDiskInfoProtocolGuid = { 0xD432A67F, 0x14DC, 0x484B, { 0xB3, 0xBB, 0x3F, 0x02, 0x91, 0x84, 0x93, 0x27 }}\r
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