-;------------------------------------------------------------------------------
-;
-; DisableInterrupts() for ARM
-;
-; Copyright (c) 2006 - 2009, Intel Corporation<BR>
-; Portions copyright (c) 2008-2009 Apple Inc.<BR>
-; All rights reserved. This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- EXPORT DisableInterrupts
-
- AREA Interrupt_disable, CODE, READONLY
-
-;/**
-; Disables CPU interrupts.
-;
-;**/
-;VOID
-;EFIAPI
-;DisableInterrupts (
-; VOID
-; );
-;
-DisableInterrupts
- MRS R0,CPSR
- ORR R0,R0,#0x80 ;Disable IRQ interrupts
- MSR CPSR_c,R0
- BX LR
-
- END
+;------------------------------------------------------------------------------ \r
+;\r
+; DisableInterrupts() for ARM\r
+;\r
+; Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+; Portions copyright (c) 2008-2009 Apple Inc.<BR>\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ EXPORT DisableInterrupts\r
+\r
+ AREA Interrupt_disable, CODE, READONLY\r
+\r
+;/**\r
+; Disables CPU interrupts.\r
+;\r
+;**/\r
+;VOID\r
+;EFIAPI\r
+;DisableInterrupts (\r
+; VOID\r
+; );\r
+;\r
+DisableInterrupts\r
+ MRS R0,CPSR\r
+ ORR R0,R0,#0x80 ;Disable IRQ interrupts\r
+ MSR CPSR_c,R0\r
+ BX LR\r
+ \r
+ END\r