## @file\r
# Base Library implementation.\r
#\r
-# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
#\r
BaseLibInternals.h\r
\r
[Sources.Ia32]\r
+ Ia32/WriteTr.nasm\r
+\r
Ia32/Wbinvd.c | MSFT \r
Ia32/WriteMm7.c | MSFT \r
Ia32/WriteMm6.c | MSFT \r
Ia32/DivU64x32Remainder.asm | INTEL \r
Ia32/DivU64x32.nasm| INTEL\r
Ia32/DivU64x32.asm | INTEL \r
- Ia32/DisablePaging32.asm | INTEL \r
+ Ia32/DisablePaging32.nasm| INTEL\r
+ Ia32/DisablePaging32.asm | INTEL\r
Ia32/DisableInterrupts.nasm| INTEL\r
Ia32/DisableInterrupts.asm | INTEL \r
Ia32/CpuPause.nasm| INTEL\r
Ia32/EnableDisableInterrupts.S | GCC \r
Ia32/EnablePaging64.nasm| GCC\r
Ia32/EnablePaging64.S | GCC \r
+ Ia32/DisablePaging32.nasm| GCC\r
Ia32/DisablePaging32.S | GCC \r
Ia32/EnablePaging32.nasm| GCC\r
Ia32/EnablePaging32.S | GCC \r
Ia32/InternalSwitchStack.c | MSFT\r
Ia32/InternalSwitchStack.c | INTEL\r
Ia32/InternalSwitchStack.S | GCC\r
+ Ia32/InternalSwitchStack.nasm | GCC\r
Ia32/Non-existing.c\r
Unaligned.c\r
X86WriteIdtr.c\r
X86EnablePaging32.c\r
X86DisablePaging64.c\r
X86DisablePaging32.c\r
+ X86RdRand.c\r
\r
[Sources.X64]\r
X64/Thunk16.nasm\r
X64/EnableCache.asm\r
X64/DisableCache.nasm\r
X64/DisableCache.asm\r
+ X64/WriteTr.nasm\r
\r
X64/CpuBreakpoint.c | MSFT \r
X64/WriteMsr64.c | MSFT \r
X64/ReadEflags.nasm| MSFT\r
X64/ReadEflags.asm | MSFT\r
\r
+ X64/CpuBreakpoint.nasm| INTEL\r
X64/CpuBreakpoint.asm | INTEL \r
+ X64/WriteMsr64.nasm| INTEL\r
X64/WriteMsr64.asm | INTEL \r
+ X64/ReadMsr64.nasm| INTEL\r
X64/ReadMsr64.asm | INTEL \r
X64/RdRand.nasm| INTEL\r
X64/RdRand.asm | INTEL\r
X86EnablePaging32.c\r
X86DisablePaging64.c\r
X86DisablePaging32.c\r
+ X86RdRand.c\r
X64/GccInline.c | GCC\r
X64/Thunk16.S | XCODE \r
X64/SwitchStack.nasm| GCC\r