1. Port X64, IPF and EBC arch for BaseLib

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ebc / CpuBreakpoint.c

diff --git a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
new file mode 100644 (file)
index 0000000..352e1c7
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
@@ -0,0 +1,164 @@
+/** @file\r
+  Base Library CPU Functions for EBC\r
+\r
+  Copyright (c) 2006, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+extern\r
+UINT64\r
+_break (\r
+  CHAR8 BreakCode\r
+  );\r
+\r
+/**\r
+  Generates a breakpoint on the CPU.\r
+\r
+  Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+  that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+  VOID\r
+  )\r
+{\r
+  _break (3);\r
+}\r
+\r
+/**\r
+  Used to serialize load and store operations.\r
+\r
+  All loads and stores that proceed calls to this function are guaranteed to be\r
+  globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+/**\r
+  Disables CPU interrupts.\r
+\r
+  Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts.\r
+\r
+  Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+  Retrieves the current CPU interrupt state.\r
+\r
+  Retrieves the current CPU interrupt state. Returns TRUE is interrupts are\r
+  currently enabled. Otherwise returns FALSE.\r
+\r
+  @retval TRUE  CPU interrupts are enabled.\r
+  @retval FALSE CPU interrupts are disabled.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+GetInterruptState (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+  return FALSE;\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableDisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  EnableInterrupts ();\r
+  DisableInterrupts ();\r
+}\r
+\r
+/**\r
+  Requests CPU to pause for a short period of time.\r
+\r
+  Requests CPU to pause for a short period of time. Typically used in MP\r
+  systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+/**\r
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+\r
+  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuFlushTlb (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+  Places the CPU in a sleep state until an interrupt is received.\r
+\r
+  Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+  are disabled prior to calling this function, then the CPU will be placed in a\r
+  sleep state indefinitely.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSleep (\r
+  VOID\r
+  )\r
+{\r
+}\r