MdePkg/BaseLib: Support IA32 processors without CLFLUSH

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / EnableCache.c

diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.c b/MdePkg/Library/BaseLib/Ia32/EnableCache.c
index 59e2b43213b94ac2b9cb67ae4077b04d7c2e6d84..ec4ea45f5b553ec563140d622a92b98befc4b8e1 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/EnableCache.c
+++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.c
@@ -1,11 +1,11 @@
 /** @file\r
   AsmEnableCache function\r
 \r
-  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
-  All rights reserved. This program and the accompanying materials\r
+  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
+  http://opensource.org/licenses/bsd-license.php.\r
 \r
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
@@ -13,10 +13,10 @@
 **/\r
 \r
 /**\r
-  Enabled caches.\r
+  Perform a WBINVD and clear both the CD and NW bits of CR0.\r
 \r
-  Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
-  the NW bit of CR0 to 0\r
+  Enables the caches by executing a WBINVD instruction and then clear both the CD and NW\r
+  bits of CR0 to 0.  This function is only available on IA-32 and x64.\r
 \r
 **/\r
 VOID\r