Use CPUID Leaf 01 to detect support for CLFLUSH instruction.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17212
6f19259b-4bc3-4df7-8a09-
765794883524
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; );\r
;------------------------------------------------------------------------------\r
AsmFlushCacheLine PROC\r
+ ;\r
+ ; If the CPU does not support CLFLUSH instruction, \r
+ ; then promote flush range to flush entire cache.\r
+ ;\r
+ mov eax, 1\r
+ cpuid\r
mov eax, [esp + 4]\r
+ test edx, BIT19\r
+ jz @F\r
clflush [eax]\r
ret\r
+@@:\r
+ wbinvd\r
+ ret\r
AsmFlushCacheLine ENDP\r
\r
END\r
/** @file\r
AsmFlushCacheLine function\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IN VOID *LinearAddress\r
)\r
{\r
+ //\r
+ // If the CPU does not support CLFLUSH instruction, \r
+ // then promote flush range to flush entire cache.\r
+ //\r
_asm {\r
- mov eax, LinearAddress\r
+ mov eax, 1\r
+ cpuid\r
+ test edx, BIT19\r
+ jz NoClflush\r
+ mov eax, [esp + 4]\r
clflush [eax]\r
+ jmp Done\r
+NoClflush:\r
+ wbinvd\r
+Done:\r
}\r
+ \r
+ return LinearAddress;\r
}\r
\r
/** @file\r
GCC inline implementation of BaseLib processor specific functions.\r
\r
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
IN VOID *LinearAddress\r
)\r
{\r
+ UINT32 RegEdx;\r
+\r
+ //\r
+ // If the CPU does not support CLFLUSH instruction, \r
+ // then promote flush range to flush entire cache.\r
+ //\r
+ AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);\r
+ if ((RegEdx & BIT19) == 0) {\r
+ __asm__ __volatile__ ("wbinvd":::"memory");\r
+ return LinearAddress;\r
+ }\r
+\r
+\r
__asm__ __volatile__ (\r
"clflush (%0)"\r
: "+a" (LinearAddress) \r
: "memory"\r
);\r
\r
- return LinearAddress;\r
+ return LinearAddress;\r
}\r
\r
\r