+\r
+\r
+\r
+/**\r
+ Flushes a cache line from all the instruction and data caches within the\r
+ coherency domain of the CPU.\r
+\r
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
+ This function is only available on IA-32 and x64.\r
+\r
+ @param LinearAddress The address of the cache line to flush. If the CPU is\r
+ in a physical addressing mode, then LinearAddress is a\r
+ physical address. If the CPU is in a virtual\r
+ addressing mode, then LinearAddress is a virtual\r
+ address.\r
+\r
+ @return LinearAddress\r
+**/\r