MdePkg/BaseLib: Support IA32 processors without CLFLUSH

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / GccInline.c

diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index e6a9e171f425abaf3ec9a499b751121f42cc2f47..f52a1fe171f33c3fdd64a922dbca328771958c65 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1,12 +1,12 @@
 /** @file\r
   GCC inline implementation of BaseLib processor specific functions.\r
   \r
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
+  http://opensource.org/licenses/bsd-license.php.\r
 \r
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
@@ -1026,7 +1026,7 @@ AsmReadTr (
   Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
   function is only available on IA-32 and X64.\r
 \r
-  @param  Gdtr  Pointer to a GDTR descriptor.\r
+  @param  Gdtr  The pointer to a GDTR descriptor.\r
 \r
 **/\r
 VOID\r
@@ -1048,7 +1048,7 @@ InternalX86ReadGdtr (
   Writes and the current GDTR descriptor specified by Gdtr. This function is\r
   only available on IA-32 and X64.\r
 \r
-  @param  Gdtr  Pointer to a GDTR descriptor.\r
+  @param  Gdtr  The pointer to a GDTR descriptor.\r
 \r
 **/\r
 VOID\r
@@ -1072,7 +1072,7 @@ InternalX86WriteGdtr (
   Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
   function is only available on IA-32 and X64.\r
 \r
-  @param  Idtr  Pointer to a IDTR descriptor.\r
+  @param  Idtr  The pointer to a IDTR descriptor.\r
 \r
 **/\r
 VOID\r
@@ -1082,7 +1082,7 @@ InternalX86ReadIdtr (
   )\r
 {\r
   __asm__ __volatile__ (\r
-    "sldt  %0"\r
+    "sidt  %0"\r
     : "=m" (*Idtr)\r
     );\r
 }\r
@@ -1094,7 +1094,7 @@ InternalX86ReadIdtr (
   Writes the current IDTR descriptor and returns it in Idtr. This function is\r
   only available on IA-32 and X64.\r
 \r
-  @param  Idtr  Pointer to a IDTR descriptor.\r
+  @param  Idtr  The pointer to a IDTR descriptor.\r
 \r
 **/\r
 VOID\r
@@ -1167,7 +1167,7 @@ AsmWriteLdtr (
   Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
   available on IA-32 and X64.\r
 \r
-  @param  Buffer  Pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+  @param  Buffer  The pointer to a buffer to save the floating point/SSE/SSE2 context.\r
 \r
 **/\r
 VOID\r
@@ -1191,7 +1191,7 @@ InternalX86FxSave (
   by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
   only available on IA-32 and X64.\r
 \r
-  @param  Buffer  Pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+  @param  Buffer  The pointer to a buffer to save the floating point/SSE/SSE2 context.\r
 \r
 **/\r
 VOID\r
@@ -1745,6 +1745,19 @@ AsmFlushCacheLine (
   IN      VOID                      *LinearAddress\r
   )\r
 {\r
+  UINT32  RegEdx;\r
+\r
+  //\r
+  // If the CPU does not support CLFLUSH instruction, \r
+  // then promote flush range to flush entire cache.\r
+  //\r
+  AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);\r
+  if ((RegEdx & BIT19) == 0) {\r
+    __asm__ __volatile__ ("wbinvd":::"memory");\r
+    return LinearAddress;\r
+  }\r
+\r
+\r
   __asm__ __volatile__ (\r
     "clflush (%0)"\r
     : "+a" (LinearAddress) \r
@@ -1752,7 +1765,7 @@ AsmFlushCacheLine (
     : "memory"\r
     );\r
     \r
-    return LinearAddress;\r
+  return LinearAddress;\r
 }\r
 \r
 \r