MdePkg/Baseib: Filter/trace MSR access for IA32/X64

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / GccInlinePriv.c

diff --git a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
index 30aa63243be8d29742c241b81f1800e935b76f06..40e8c08beb31c1e944107e82e3866d6a16999e38 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c
@@ -2,7 +2,7 @@
   GCC inline implementation of BaseLib processor specific functions that use\r
   privlidged instructions.\r
 \r
-  Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -10,6 +10,7 @@
 \r
 \r
 #include "BaseLibInternals.h"\r
+#include <Library/RegisterFilterLib.h>\r
 \r
 /**\r
   Enables CPU interrupts.\r
@@ -63,12 +64,17 @@ AsmReadMsr64 (
   )\r
 {\r
   UINT64 Data;\r
-\r
-  __asm__ __volatile__ (\r
-    "rdmsr"\r
-    : "=A" (Data)   // %0\r
-    : "c"  (Index)  // %1\r
-    );\r
+  BOOLEAN Flag;\r
+\r
+  Flag = FilterBeforeMsrRead (Index, &Data);\r
+  if (Flag) {\r
+    __asm__ __volatile__ (\r
+      "rdmsr"\r
+      : "=A" (Data)   // %0\r
+      : "c"  (Index)  // %1\r
+      );\r
+  }\r
+  FilterAfterMsrRead (Index, &Data);\r
 \r
   return Data;\r
 }\r
@@ -97,12 +103,18 @@ AsmWriteMsr64 (
   IN      UINT64                    Value\r
   )\r
 {\r
-  __asm__ __volatile__ (\r
-    "wrmsr"\r
-    :\r
-    : "c" (Index),\r
-      "A" (Value)\r
-    );\r
+  BOOLEAN  Flag;\r
+\r
+  Flag = FilterBeforeMsrWrite (Index, &Value);\r
+  if (Flag) {\r
+    __asm__ __volatile__ (\r
+      "wrmsr"\r
+      :\r
+      : "c" (Index),\r
+        "A" (Value)\r
+      );\r
+  }\r
+  FilterAfterMsrWrite (Index, &Value);\r
 \r
   return Value;\r
 }\r