+++ /dev/null
-/** @file\r
- AsmFlushCacheRange() function for IPF.\r
-\r
- Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-\r
-#include "BaseLibInternals.h"\r
-\r
-/**\r
- Flush a range of cache lines in the cache coherency domain of the calling\r
- CPU.\r
-\r
- Flushes the cache lines specified by Address and Length. If Address is not aligned\r
- on a cache line boundary, then entire cache line containing Address is flushed.\r
- If Address + Length is not aligned on a cache line boundary, then the entire cache\r
- line containing Address + Length - 1 is flushed. This function may choose to flush\r
- the entire cache if that is more efficient than flushing the specified range. If\r
- Length is 0, the no cache lines are flushed. Address is returned.\r
- This function is only available on IPF.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the instruction lines to invalidate. If\r
- the CPU is in a physical addressing mode, then Address is a\r
- physical address. If the CPU is in a virtual addressing mode,\r
- then Address is a virtual address.\r
-\r
- @param Length The number of bytes to invalidate from the instruction cache.\r
-\r
- @return Address.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-AsmFlushCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- )\r
-{\r
- ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
- return InternalFlushCacheRange (Address, Length);\r
-}\r