+++ /dev/null
-// @file\r
-// Contains the macros required by calling procedures in Itanium-based assembly code.\r
-//\r
-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-\r
-#ifndef __IA64PROC_I__\r
-#define __IA64PROC_I__\r
-\r
-//\r
-// Delcare the begin of assembly function entry.\r
-//\r
-// @param name Name of function in assembly code.\r
-//\r
-#define PROCEDURE_ENTRY(name) .##text; \\r
- .##type name, @function; \\r
- .##proc name; \\r
-name::\r
-\r
-//\r
-// End of assembly function.\r
-//\r
-// @param name Name of function in assembly code.\r
-//\r
-#define PROCEDURE_EXIT(name) .##endp name\r
-\r
-//\r
-// NESTED_SETUP Requires number of locals (l) >= 3\r
-//\r
-#define NESTED_SETUP(i,l,o,r) \\r
- alloc loc1=ar##.##pfs,i,l,o,r ;\\r
- mov loc0=b0\r
-\r
-//\r
-// End of Nested\r
-//\r
-#define NESTED_RETURN \\r
- mov b0=loc0 ;\\r
- mov ar##.##pfs=loc1 ;;\\r
- br##.##ret##.##dpnt b0;;\r
-\r
-//\r
-// Export assembly function as the global function.\r
-//\r
-// @param Function Name of function in assembly code.\r
-//\r
-#define GLOBAL_FUNCTION(Function) \\r
- .##type Function, @function; \\r
- .##globl Function\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- Processor or Compiler specific defines and types for Intel Itanium(TM) processors.\r
-\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials are licensed and made available\r
-under the terms and conditions of the BSD License which accompanies this\r
-distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php.\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __PROCESSOR_BIND_H__\r
-#define __PROCESSOR_BIND_H__\r
-\r
-\r
-///\r
-/// Define the processor type so other code can make processor-based choices.\r
-///\r
-#define MDE_CPU_IPF\r
-\r
-\r
-//\r
-// Make sure we are using the correct packing rules per EFI specification\r
-//\r
-#pragma pack()\r
-\r
-\r
-#if defined(__INTEL_COMPILER)\r
-//\r
-// Disable ICC's remark #869: "Parameter" was never referenced warning.\r
-// This is legal ANSI C code so we disable the remark that is turned on with -Wall\r
-//\r
-#pragma warning ( disable : 869 )\r
-\r
-//\r
-// Disable ICC's remark #1418: external function definition with no prior declaration.\r
-// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
-//\r
-#pragma warning ( disable : 1418 )\r
-\r
-//\r
-// Disable ICC's remark #1419: external declaration in primary source file\r
-// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
-//\r
-#pragma warning ( disable : 1419 )\r
-\r
-//\r
-// Disable ICC's remark #593: "Variable" was set but never used.\r
-// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
-//\r
-#pragma warning ( disable : 593 )\r
-\r
-#endif\r
-\r
-\r
-#if defined(_MSC_EXTENSIONS)\r
-//\r
-// Disable warning that make it impossible to compile at /W4\r
-// This only works for Microsoft* tools\r
-//\r
-\r
-//\r
-// Disabling bitfield type checking warnings.\r
-//\r
-#pragma warning ( disable : 4214 )\r
-\r
-//\r
-// Disabling the unreferenced formal parameter warnings.\r
-//\r
-#pragma warning ( disable : 4100 )\r
-\r
-//\r
-// Disable slightly different base types warning as CHAR8 * can not be set\r
-// to a constant string.\r
-//\r
-#pragma warning ( disable : 4057 )\r
-\r
-//\r
-// Disable warning on conversion from function pointer to a data pointer\r
-//\r
-#pragma warning ( disable : 4054 )\r
-\r
-//\r
-// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning\r
-//\r
-#pragma warning ( disable : 4127 )\r
-\r
-//\r
-// Can not cast a function pointer to a data pointer. We need to do this on\r
-// Itanium processors to get access to the PLABEL.\r
-//\r
-#pragma warning ( disable : 4514 )\r
-\r
-//\r
-// This warning is caused by functions defined but not used. For precompiled header only.\r
-//\r
-#pragma warning ( disable : 4505 )\r
-\r
-//\r
-// This warning is caused by empty (after preprocessing) source file. For precompiled header only.\r
-//\r
-#pragma warning ( disable : 4206 )\r
-\r
-#endif\r
-\r
-#if defined(_MSC_EXTENSIONS)\r
- //\r
- // use Microsoft C compiler dependent integer width types\r
- //\r
-\r
- ///\r
- /// 8-byte unsigned value.\r
- ///\r
- typedef unsigned __int64 UINT64;\r
- ///\r
- /// 8-byte signed value.\r
- ///\r
- typedef __int64 INT64;\r
- ///\r
- /// 4-byte unsigned value.\r
- ///\r
- typedef unsigned __int32 UINT32;\r
- ///\r
- /// 4-byte signed value.\r
- ///\r
- typedef __int32 INT32;\r
- ///\r
- /// 2-byte unsigned value.\r
- ///\r
- typedef unsigned short UINT16;\r
- ///\r
- /// 2-byte Character. Unless otherwise specified all strings are stored in the\r
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
- ///\r
- typedef unsigned short CHAR16;\r
- ///\r
- /// 2-byte signed value.\r
- ///\r
- typedef short INT16;\r
- ///\r
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
- /// values are undefined.\r
- ///\r
- typedef unsigned char BOOLEAN;\r
- ///\r
- /// 1-byte unsigned value.\r
- ///\r
- typedef unsigned char UINT8;\r
- ///\r
- /// 1-byte Character.\r
- ///\r
- typedef char CHAR8;\r
- ///\r
- /// 1-byte signed value.\r
- ///\r
- typedef signed char INT8;\r
-#else\r
- ///\r
- /// 8-byte unsigned value.\r
- ///\r
- typedef unsigned long long UINT64;\r
- ///\r
- /// 8-byte signed value.\r
- ///\r
- typedef long long INT64;\r
- ///\r
- /// 4-byte unsigned value.\r
- ///\r
- typedef unsigned int UINT32;\r
- ///\r
- /// 4-byte signed value.\r
- ///\r
- typedef int INT32;\r
- ///\r
- /// 2-byte unsigned value.\r
- ///\r
- typedef unsigned short UINT16;\r
- ///\r
- /// 2-byte Character. Unless otherwise specified all strings are stored in the\r
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
- ///\r
- typedef unsigned short CHAR16;\r
- ///\r
- /// 2-byte signed value.\r
- ///\r
- typedef short INT16;\r
- ///\r
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
- /// values are undefined.\r
- ///\r
- typedef unsigned char BOOLEAN;\r
- ///\r
- /// 1-byte unsigned value.\r
- ///\r
- typedef unsigned char UINT8;\r
- ///\r
- /// 1-byte Character.\r
- ///\r
- typedef char CHAR8;\r
- ///\r
- /// 1-byte signed value.\r
- ///\r
- typedef signed char INT8;\r
-#endif\r
-\r
-///\r
-/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;\r
-/// 8 bytes on supported 64-bit processor instructions.)\r
-///\r
-typedef UINT64 UINTN;\r
-///\r
-/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;\r
-/// 8 bytes on supported 64-bit processor instructions.)\r
-///\r
-typedef INT64 INTN;\r
-\r
-\r
-//\r
-// Processor specific defines\r
-//\r
-\r
-///\r
-/// A value of native width with the highest bit set.\r
-///\r
-#define MAX_BIT 0x8000000000000000ULL\r
-///\r
-/// A value of native width with the two highest bits set.\r
-///\r
-#define MAX_2_BITS 0xC000000000000000ULL\r
-\r
-///\r
-/// The maximum legal Itanium-based address\r
-///\r
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL\r
-\r
-///\r
-/// Maximum legal Itanium-based INTN and UINTN values.\r
-///\r
-#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)\r
-#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)\r
-\r
-///\r
-/// Minimum legal Itanium-based INTN value.\r
-///\r
-#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)\r
-\r
-///\r
-/// Per the Itanium Software Conventions and Runtime Architecture Guide,\r
-/// section 3.3.4, IPF stack must always be 16-byte aligned.\r
-///\r
-#define CPU_STACK_ALIGNMENT 16\r
-\r
-///\r
-/// Page allocation granularity for Itanium\r
-///\r
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x2000)\r
-\r
-//\r
-// Modifier to ensure that all protocol member functions and EFI intrinsics\r
-// use the correct C calling convention. All protocol member functions and\r
-// EFI intrinsics are required to modify their member functions with EFIAPI.\r
-//\r
-#ifdef EFIAPI\r
- ///\r
- /// If EFIAPI is already defined, then we use that definition.\r
- ///\r
-#elif defined(_MSC_EXTENSIONS)\r
- ///\r
- /// Microsoft* compiler-specific method for EFIAPI calling convention.\r
- ///\r
- #define EFIAPI __cdecl\r
-#else\r
- #define EFIAPI\r
-#endif\r
-\r
-///\r
-/// For GNU assembly code, .global or .globl can declare global symbols.\r
-/// Define this macro to unify the usage.\r
-///\r
-#define ASM_GLOBAL .globl\r
-\r
-///\r
-/// A pointer to a function in IPF points to a plabel.\r
-///\r
-typedef struct {\r
- UINT64 EntryPoint;\r
- UINT64 GP;\r
-} EFI_PLABEL;\r
-\r
-///\r
-/// PAL Call return structure.\r
-///\r
-typedef struct {\r
- UINT64 Status;\r
- UINT64 r9;\r
- UINT64 r10;\r
- UINT64 r11;\r
-} PAL_CALL_RETURN;\r
-\r
-/**\r
- Return the pointer to the first instruction of a function given a function pointer.\r
- For Itanium processors, all function calls are made through a PLABEL, so a pointer to a function\r
- is actually a pointer to a PLABEL. The pointer to the first instruction of the function\r
- is contained within the PLABEL. This macro may be used to retrieve a pointer to the first\r
- instruction of a function independent of the CPU architecture being used. This is very\r
- useful when printing function addresses through DEBUG() macros.\r
-\r
- @param FunctionPointer A pointer to a function.\r
-\r
- @return The pointer to the first instruction of a function given a function pointer.\r
-\r
-**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(((EFI_PLABEL *)(FunctionPointer))->EntryPoint)\r
-\r
-#ifndef __USER_LABEL_PREFIX__\r
-#define __USER_LABEL_PREFIX__\r
-#endif\r
-\r
-#endif\r
-\r
\r
#endif // defined (MDE_CPU_IA32)\r
\r
-#if defined (MDE_CPU_IPF)\r
-\r
-///\r
-/// The Itanium architecture context buffer used by SetJump() and LongJump().\r
-///\r
-typedef struct {\r
- UINT64 F2[2];\r
- UINT64 F3[2];\r
- UINT64 F4[2];\r
- UINT64 F5[2];\r
- UINT64 F16[2];\r
- UINT64 F17[2];\r
- UINT64 F18[2];\r
- UINT64 F19[2];\r
- UINT64 F20[2];\r
- UINT64 F21[2];\r
- UINT64 F22[2];\r
- UINT64 F23[2];\r
- UINT64 F24[2];\r
- UINT64 F25[2];\r
- UINT64 F26[2];\r
- UINT64 F27[2];\r
- UINT64 F28[2];\r
- UINT64 F29[2];\r
- UINT64 F30[2];\r
- UINT64 F31[2];\r
- UINT64 R4;\r
- UINT64 R5;\r
- UINT64 R6;\r
- UINT64 R7;\r
- UINT64 SP;\r
- UINT64 BR0;\r
- UINT64 BR1;\r
- UINT64 BR2;\r
- UINT64 BR3;\r
- UINT64 BR4;\r
- UINT64 BR5;\r
- UINT64 InitialUNAT;\r
- UINT64 AfterSpillUNAT;\r
- UINT64 PFS;\r
- UINT64 BSP;\r
- UINT64 Predicates;\r
- UINT64 LoopCount;\r
- UINT64 FPSR;\r
-} BASE_LIBRARY_JUMP_BUFFER;\r
-\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 0x10\r
-\r
-#endif // defined (MDE_CPU_IPF)\r
-\r
#if defined (MDE_CPU_X64)\r
///\r
/// The x64 architecture context buffer used by SetJump() and LongJump().\r
VOID\r
);\r
\r
-#if defined (MDE_CPU_IPF)\r
-\r
-/**\r
- Flush a range of cache lines in the cache coherency domain of the calling\r
- CPU.\r
-\r
- Flushes the cache lines specified by Address and Length. If Address is not aligned\r
- on a cache line boundary, then entire cache line containing Address is flushed.\r
- If Address + Length is not aligned on a cache line boundary, then the entire cache\r
- line containing Address + Length - 1 is flushed. This function may choose to flush\r
- the entire cache if that is more efficient than flushing the specified range. If\r
- Length is 0, the no cache lines are flushed. Address is returned.\r
- This function is only available on Itanium processors.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the instruction lines to invalidate. If\r
- the CPU is in a physical addressing mode, then Address is a\r
- physical address. If the CPU is in a virtual addressing mode,\r
- then Address is a virtual address.\r
-\r
- @param Length The number of bytes to invalidate from the instruction cache.\r
-\r
- @return Address.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-AsmFlushCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- );\r
-\r
-\r
-/**\r
- Executes an FC instruction.\r
- Executes an FC instruction on the cache line specified by Address.\r
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on Itanium processors.\r
-\r
- @param Address The Address of cache line to be flushed.\r
-\r
- @return The address of FC instruction executed.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmFc (\r
- IN UINT64 Address\r
- );\r
-\r
-\r
-/**\r
- Executes an FC.I instruction.\r
- Executes an FC.I instruction on the cache line specified by Address.\r
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).\r
- An implementation may flush a larger region. This function is only available on Itanium processors.\r
-\r
- @param Address The Address of cache line to be flushed.\r
-\r
- @return The address of the FC.I instruction executed.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmFci (\r
- IN UINT64 Address\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of a Processor Identifier Register (CPUID).\r
-\r
- Reads and returns the current value of Processor Identifier Register specified by Index.\r
- The Index of largest implemented CPUID (One less than the number of implemented CPUID\r
- registers) is determined by CPUID [3] bits {7:0}.\r
- No parameter checking is performed on Index. If the Index value is beyond the\r
- implemented CPUID register range, a Reserved Register/Field fault may occur. The caller\r
- must either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults. This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Processor Identifier Register index to read.\r
-\r
- @return The current value of Processor Identifier Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadCpuid (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Processor Status Register (PSR).\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of PSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPsr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Processor Status Register (PSR).\r
-\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PSR.\r
-\r
- @return The 64-bit value written to the PSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePsr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #0 (KR0).\r
-\r
- Reads and returns the current value of KR0.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #1 (KR1).\r
-\r
- Reads and returns the current value of KR1.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #2 (KR2).\r
-\r
- Reads and returns the current value of KR2.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #3 (KR3).\r
-\r
- Reads and returns the current value of KR3.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #4 (KR4).\r
-\r
- Reads and returns the current value of KR4.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR4.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr4 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #5 (KR5).\r
-\r
- Reads and returns the current value of KR5.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR5.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr5 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #6 (KR6).\r
-\r
- Reads and returns the current value of KR6.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR6.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr6 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Kernel Register #7 (KR7).\r
-\r
- Reads and returns the current value of KR7.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of KR7.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadKr7 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #0 (KR0).\r
-\r
- Writes the current value of KR0. The 64-bit value written to\r
- the KR0 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR0.\r
-\r
- @return The 64-bit value written to the KR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr0 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #1 (KR1).\r
-\r
- Writes the current value of KR1. The 64-bit value written to\r
- the KR1 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR1.\r
-\r
- @return The 64-bit value written to the KR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr1 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #2 (KR2).\r
-\r
- Writes the current value of KR2. The 64-bit value written to\r
- the KR2 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR2.\r
-\r
- @return The 64-bit value written to the KR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr2 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #3 (KR3).\r
-\r
- Writes the current value of KR3. The 64-bit value written to\r
- the KR3 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR3.\r
-\r
- @return The 64-bit value written to the KR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr3 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #4 (KR4).\r
-\r
- Writes the current value of KR4. The 64-bit value written to\r
- the KR4 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR4.\r
-\r
- @return The 64-bit value written to the KR4.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr4 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #5 (KR5).\r
-\r
- Writes the current value of KR5. The 64-bit value written to\r
- the KR5 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR5.\r
-\r
- @return The 64-bit value written to the KR5.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr5 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #6 (KR6).\r
-\r
- Writes the current value of KR6. The 64-bit value written to\r
- the KR6 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR6.\r
-\r
- @return The 64-bit value written to the KR6.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr6 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Kernel Register #7 (KR7).\r
-\r
- Writes the current value of KR7. The 64-bit value written to\r
- the KR7 is returned. This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to KR7.\r
-\r
- @return The 64-bit value written to the KR7.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteKr7 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Counter Register (ITC).\r
-\r
- Reads and returns the current value of ITC.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItc (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Vector Register (ITV).\r
-\r
- Reads and returns the current value of ITV.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interval Timer Match Register (ITM).\r
-\r
- Reads and returns the current value of ITM.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of ITM.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadItm (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Counter Register (ITC).\r
-\r
- Writes the current value of ITC. The 64-bit value written to the ITC is returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITC.\r
-\r
- @return The 64-bit value written to the ITC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItc (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Match Register (ITM).\r
-\r
- Writes the current value of ITM. The 64-bit value written to the ITM is returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITM.\r
-\r
- @return The 64-bit value written to the ITM.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItm (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interval Timer Vector Register (ITV).\r
-\r
- Writes the current value of ITV. The 64-bit value written to the ITV is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to ITV.\r
-\r
- @return The 64-bit value written to the ITV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteItv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Default Control Register (DCR).\r
-\r
- Reads and returns the current value of DCR. This function is only available on Itanium processors.\r
-\r
- @return The current value of DCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadDcr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Interruption Vector Address Register (IVA).\r
-\r
- Reads and returns the current value of IVA. This function is only available on Itanium processors.\r
-\r
- @return The current value of IVA.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIva (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Page Table Address Register (PTA).\r
-\r
- Reads and returns the current value of PTA. This function is only available on Itanium processors.\r
-\r
- @return The current value of PTA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPta (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Default Control Register (DCR).\r
-\r
- Writes the current value of DCR. The 64-bit value written to the DCR is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to DCR.\r
-\r
- @return The 64-bit value written to the DCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteDcr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Interruption Vector Address Register (IVA).\r
-\r
- Writes the current value of IVA. The 64-bit value written to the IVA is returned.\r
- The size of vector table is 32 K bytes and is 32 K bytes aligned\r
- the low 15 bits of Value is ignored when written.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to IVA.\r
-\r
- @return The 64-bit value written to the IVA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteIva (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Page Table Address Register (PTA).\r
-\r
- Writes the current value of PTA. The 64-bit value written to the PTA is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PTA.\r
-\r
- @return The 64-bit value written to the PTA.\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePta (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Interrupt ID Register (LID).\r
-\r
- Reads and returns the current value of LID. This function is only available on Itanium processors.\r
-\r
- @return The current value of LID.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLid (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Vector Register (IVR).\r
-\r
- Reads and returns the current value of IVR. This function is only available on Itanium processors.\r
-\r
- @return The current value of IVR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIvr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Task Priority Register (TPR).\r
-\r
- Reads and returns the current value of TPR. This function is only available on Itanium processors.\r
-\r
- @return The current value of TPR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadTpr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #0 (IRR0).\r
-\r
- Reads and returns the current value of IRR0. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #1 (IRR1).\r
-\r
- Reads and returns the current value of IRR1. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #2 (IRR2).\r
-\r
- Reads and returns the current value of IRR2. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of External Interrupt Request Register #3 (IRR3).\r
-\r
- Reads and returns the current value of IRR3. This function is only available on Itanium processors.\r
-\r
- @return The current value of IRR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIrr3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Vector Register (PMV).\r
-\r
- Reads and returns the current value of PMV. This function is only available on Itanium processors.\r
-\r
- @return The current value of PMV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Corrected Machine Check Vector Register (CMCV).\r
-\r
- Reads and returns the current value of CMCV. This function is only available on Itanium processors.\r
-\r
- @return The current value of CMCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadCmcv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Redirection Register #0 (LRR0).\r
-\r
- Reads and returns the current value of LRR0. This function is only available on Itanium processors.\r
-\r
- @return The current value of LRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Local Redirection Register #1 (LRR1).\r
-\r
- Reads and returns the current value of LRR1. This function is only available on Itanium processors.\r
-\r
- @return The current value of LRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadLrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Page Local Interrupt ID Register (LID).\r
-\r
- Writes the current value of LID. The 64-bit value written to the LID is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LID.\r
-\r
- @return The 64-bit value written to the LID.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLid (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Task Priority Register (TPR).\r
-\r
- Writes the current value of TPR. The 64-bit value written to the TPR is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding to\r
- reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to TPR.\r
-\r
- @return The 64-bit value written to the TPR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteTpr (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Performs a write operation on End OF External Interrupt Register (EOI).\r
-\r
- Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmWriteEoi (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Vector Register (PMV).\r
-\r
- Writes the current value of PMV. The 64-bit value written to the PMV is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to PMV.\r
-\r
- @return The 64-bit value written to the PMV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).\r
-\r
- Writes the current value of CMCV. The 64-bit value written to the CMCV is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to CMCV.\r
-\r
- @return The 64-bit value written to the CMCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteCmcv (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Local Redirection Register #0 (LRR0).\r
-\r
- Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LRR0.\r
-\r
- @return The 64-bit value written to the LRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLrr0 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Local Redirection Register #1 (LRR1).\r
-\r
- Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned.\r
- No parameter checking is performed on Value. All bits of Value corresponding\r
- to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Value is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to LRR1.\r
-\r
- @return The 64-bit value written to the LRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteLrr1 (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Instruction Breakpoint Register (IBR).\r
-\r
- The Instruction Breakpoint Registers are used in pairs. The even numbered\r
- registers contain breakpoint addresses, and the odd numbered registers contain\r
- breakpoint mask conditions. At least four instruction registers pairs are implemented\r
- on all processor models. Implemented registers are contiguous starting with\r
- register 0. No parameter checking is performed on Index, and if the Index value\r
- is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
- occur. The caller must either guarantee that Index is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Instruction Breakpoint Register index to read.\r
-\r
- @return The current value of Instruction Breakpoint Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadIbr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Data Breakpoint Register (DBR).\r
-\r
- The Data Breakpoint Registers are used in pairs. The even numbered registers\r
- contain breakpoint addresses, and odd numbered registers contain breakpoint\r
- mask conditions. At least four data registers pairs are implemented on all processor\r
- models. Implemented registers are contiguous starting with register 0.\r
- No parameter checking is performed on Index. If the Index value is beyond\r
- the implemented DBR register range, a Reserved Register/Field fault may occur.\r
- The caller must either guarantee that Index is valid, or the caller must set up\r
- fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Data Breakpoint Register index to read.\r
-\r
- @return The current value of Data Breakpoint Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadDbr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Configuration Register (PMC).\r
-\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow\r
- status registers (PMC [0]... PMC [3]). Processor implementations may provide\r
- additional implementation-dependent PMC and PMD to increase the number of\r
- 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
- register set is implementation dependent. No parameter checking is performed\r
- on Index. If the Index value is beyond the implemented PMC register range,\r
- zero value will be returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Configuration Register index to read.\r
-\r
- @return The current value of Performance Monitor Configuration Register\r
- specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmc (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of Performance Monitor Data Register (PMD).\r
-\r
- All processor implementations provide at least 4 performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter\r
- overflow status registers (PMC [0]... PMC [3]). Processor implementations may\r
- provide additional implementation-dependent PMC and PMD to increase the number\r
- of 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD\r
- register set is implementation dependent. No parameter checking is performed\r
- on Index. If the Index value is beyond the implemented PMD register range,\r
- zero value will be returned.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Data Register index to read.\r
-\r
- @return The current value of Performance Monitor Data Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadPmd (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Instruction Breakpoint Register (IBR).\r
-\r
- Writes current value of Instruction Breakpoint Register specified by Index.\r
- The Instruction Breakpoint Registers are used in pairs. The even numbered\r
- registers contain breakpoint addresses, and odd numbered registers contain\r
- breakpoint mask conditions. At least four instruction registers pairs are implemented\r
- on all processor models. Implemented registers are contiguous starting with\r
- register 0. No parameter checking is performed on Index. If the Index value\r
- is beyond the implemented IBR register range, a Reserved Register/Field fault may\r
- occur. The caller must either guarantee that Index is valid, or the caller must\r
- set up fault handlers to catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Instruction Breakpoint Register index to write.\r
- @param Value The 64-bit value to write to IBR.\r
-\r
- @return The 64-bit value written to the IBR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteIbr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Data Breakpoint Register (DBR).\r
-\r
- Writes current value of Data Breakpoint Register specified by Index.\r
- The Data Breakpoint Registers are used in pairs. The even numbered registers\r
- contain breakpoint addresses, and odd numbered registers contain breakpoint\r
- mask conditions. At least four data registers pairs are implemented on all processor\r
- models. Implemented registers are contiguous starting with register 0. No parameter\r
- checking is performed on Index. If the Index value is beyond the implemented\r
- DBR register range, a Reserved Register/Field fault may occur. The caller must\r
- either guarantee that Index is valid, or the caller must set up fault handlers to\r
- catch the faults.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Data Breakpoint Register index to write.\r
- @param Value The 64-bit value to write to DBR.\r
-\r
- @return The 64-bit value written to the DBR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteDbr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Configuration Register (PMC).\r
-\r
- Writes current value of Performance Monitor Configuration Register specified by Index.\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow status\r
- registers (PMC [0]... PMC [3]). Processor implementations may provide additional\r
- implementation-dependent PMC and PMD to increase the number of 'generic' performance\r
- counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation\r
- dependent. No parameter checking is performed on Index. If the Index value is\r
- beyond the implemented PMC register range, the write is ignored.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Configuration Register index to write.\r
- @param Value The 64-bit value to write to PMC.\r
-\r
- @return The 64-bit value written to the PMC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmc (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of 64-bit Performance Monitor Data Register (PMD).\r
-\r
- Writes current value of Performance Monitor Data Register specified by Index.\r
- All processor implementations provide at least four performance counters\r
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow\r
- status registers (PMC [0]... PMC [3]). Processor implementations may provide\r
- additional implementation-dependent PMC and PMD to increase the number of 'generic'\r
- performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set\r
- is implementation dependent. No parameter checking is performed on Index. If the\r
- Index value is beyond the implemented PMD register range, the write is ignored.\r
- This function is only available on Itanium processors.\r
-\r
- @param Index The 8-bit Performance Monitor Data Register index to write.\r
- @param Value The 64-bit value to write to PMD.\r
-\r
- @return The 64-bit value written to the PMD.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWritePmd (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Global Pointer (GP).\r
-\r
- Reads and returns the current value of GP.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of GP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadGp (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Write the current value of 64-bit Global Pointer (GP).\r
-\r
- Writes the current value of GP. The 64-bit value written to the GP is returned.\r
- No parameter checking is performed on Value.\r
- This function is only available on Itanium processors.\r
-\r
- @param Value The 64-bit value to write to GP.\r
-\r
- @return The 64-bit value written to the GP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteGp (\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of 64-bit Stack Pointer (SP).\r
-\r
- Reads and returns the current value of SP.\r
- This function is only available on Itanium processors.\r
-\r
- @return The current value of SP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadSp (\r
- VOID\r
- );\r
-\r
-\r
-///\r
-/// Valid Index value for AsmReadControlRegister().\r
-///\r
-#define IPF_CONTROL_REGISTER_DCR 0\r
-#define IPF_CONTROL_REGISTER_ITM 1\r
-#define IPF_CONTROL_REGISTER_IVA 2\r
-#define IPF_CONTROL_REGISTER_PTA 8\r
-#define IPF_CONTROL_REGISTER_IPSR 16\r
-#define IPF_CONTROL_REGISTER_ISR 17\r
-#define IPF_CONTROL_REGISTER_IIP 19\r
-#define IPF_CONTROL_REGISTER_IFA 20\r
-#define IPF_CONTROL_REGISTER_ITIR 21\r
-#define IPF_CONTROL_REGISTER_IIPA 22\r
-#define IPF_CONTROL_REGISTER_IFS 23\r
-#define IPF_CONTROL_REGISTER_IIM 24\r
-#define IPF_CONTROL_REGISTER_IHA 25\r
-#define IPF_CONTROL_REGISTER_LID 64\r
-#define IPF_CONTROL_REGISTER_IVR 65\r
-#define IPF_CONTROL_REGISTER_TPR 66\r
-#define IPF_CONTROL_REGISTER_EOI 67\r
-#define IPF_CONTROL_REGISTER_IRR0 68\r
-#define IPF_CONTROL_REGISTER_IRR1 69\r
-#define IPF_CONTROL_REGISTER_IRR2 70\r
-#define IPF_CONTROL_REGISTER_IRR3 71\r
-#define IPF_CONTROL_REGISTER_ITV 72\r
-#define IPF_CONTROL_REGISTER_PMV 73\r
-#define IPF_CONTROL_REGISTER_CMCV 74\r
-#define IPF_CONTROL_REGISTER_LRR0 80\r
-#define IPF_CONTROL_REGISTER_LRR1 81\r
-\r
-/**\r
- Reads a 64-bit control register.\r
-\r
- Reads and returns the control register specified by Index. The valid Index valued\r
- are defined above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only\r
- available on Itanium processors.\r
-\r
- @param Index The index of the control register to read.\r
-\r
- @return The control register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegister (\r
- IN UINT64 Index\r
- );\r
-\r
-\r
-///\r
-/// Valid Index value for AsmReadApplicationRegister().\r
-///\r
-#define IPF_APPLICATION_REGISTER_K0 0\r
-#define IPF_APPLICATION_REGISTER_K1 1\r
-#define IPF_APPLICATION_REGISTER_K2 2\r
-#define IPF_APPLICATION_REGISTER_K3 3\r
-#define IPF_APPLICATION_REGISTER_K4 4\r
-#define IPF_APPLICATION_REGISTER_K5 5\r
-#define IPF_APPLICATION_REGISTER_K6 6\r
-#define IPF_APPLICATION_REGISTER_K7 7\r
-#define IPF_APPLICATION_REGISTER_RSC 16\r
-#define IPF_APPLICATION_REGISTER_BSP 17\r
-#define IPF_APPLICATION_REGISTER_BSPSTORE 18\r
-#define IPF_APPLICATION_REGISTER_RNAT 19\r
-#define IPF_APPLICATION_REGISTER_FCR 21\r
-#define IPF_APPLICATION_REGISTER_EFLAG 24\r
-#define IPF_APPLICATION_REGISTER_CSD 25\r
-#define IPF_APPLICATION_REGISTER_SSD 26\r
-#define IPF_APPLICATION_REGISTER_CFLG 27\r
-#define IPF_APPLICATION_REGISTER_FSR 28\r
-#define IPF_APPLICATION_REGISTER_FIR 29\r
-#define IPF_APPLICATION_REGISTER_FDR 30\r
-#define IPF_APPLICATION_REGISTER_CCV 32\r
-#define IPF_APPLICATION_REGISTER_UNAT 36\r
-#define IPF_APPLICATION_REGISTER_FPSR 40\r
-#define IPF_APPLICATION_REGISTER_ITC 44\r
-#define IPF_APPLICATION_REGISTER_PFS 64\r
-#define IPF_APPLICATION_REGISTER_LC 65\r
-#define IPF_APPLICATION_REGISTER_EC 66\r
-\r
-/**\r
- Reads a 64-bit application register.\r
-\r
- Reads and returns the application register specified by Index. The valid Index\r
- valued are defined above in "Related Definitions".\r
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only\r
- available on Itanium processors.\r
-\r
- @param Index The index of the application register to read.\r
-\r
- @return The application register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegister (\r
- IN UINT64 Index\r
- );\r
-\r
-\r
-/**\r
- Reads the current value of a Machine Specific Register (MSR).\r
-\r
- Reads and returns the current value of the Machine Specific Register specified by Index. No\r
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on Itanium processors.\r
-\r
- @param Index The 8-bit Machine Specific Register index to read.\r
-\r
- @return The current value of the Machine Specific Register specified by Index.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadMsr (\r
- IN UINT8 Index\r
- );\r
-\r
-\r
-/**\r
- Writes the current value of a Machine Specific Register (MSR).\r
-\r
- Writes Value to the Machine Specific Register specified by Index. Value is returned. No\r
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
- only available on Itanium processors.\r
-\r
- @param Index The 8-bit Machine Specific Register index to write.\r
- @param Value The 64-bit value to write to the Machine Specific Register.\r
-\r
- @return The 64-bit value to write to the Machine Specific Register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmWriteMsr (\r
- IN UINT8 Index,\r
- IN UINT64 Value\r
- );\r
-\r
-\r
-/**\r
- Determines if the CPU is currently executing in virtual, physical, or mixed mode.\r
-\r
- Determines the current execution mode of the CPU.\r
- If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.\r
- If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
- If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
- and -1 is returned.\r
- This function is only available on Itanium processors.\r
-\r
- @retval 1 The CPU is in virtual mode.\r
- @retval 0 The CPU is in physical mode.\r
- @retval -1 The CPU is in mixed mode.\r
-\r
-**/\r
-INT64\r
-EFIAPI\r
-AsmCpuVirtual (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Makes a PAL procedure call.\r
-\r
- This is a wrapper function to make a PAL procedure call. Based on the Index\r
- value this API will make static or stacked PAL call. The following table\r
- describes the usage of PAL Procedure Index Assignment. Architected procedures\r
- may be designated as required or optional. If a PAL procedure is specified\r
- as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the\r
- Status field of the PAL_CALL_RETURN structure.\r
- This indicates that the procedure is not present in this PAL implementation.\r
- It is the caller's responsibility to check for this return code after calling\r
- any optional PAL procedure.\r
- No parameter checking is performed on the 5 input parameters, but there are\r
- some common rules that the caller should follow when making a PAL call. Any\r
- address passed to PAL as buffers for return parameters must be 8-byte aligned.\r
- Unaligned addresses may cause undefined results. For those parameters defined\r
- as reserved or some fields defined as reserved must be zero filled or the invalid\r
- argument return value may be returned or undefined result may occur during the\r
- execution of the procedure. If the PalEntryPoint does not point to a valid\r
- PAL entry point then the system behavior is undefined. This function is only\r
- available on Itanium processors.\r
-\r
- @param PalEntryPoint The PAL procedure calls entry point.\r
- @param Index The PAL procedure Index number.\r
- @param Arg2 The 2nd parameter for PAL procedure calls.\r
- @param Arg3 The 3rd parameter for PAL procedure calls.\r
- @param Arg4 The 4th parameter for PAL procedure calls.\r
-\r
- @return structure returned from the PAL Call procedure, including the status and return value.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-EFIAPI\r
-AsmPalCall (\r
- IN UINT64 PalEntryPoint,\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- );\r
-#endif // defined (MDE_CPU_IPF)\r
-\r
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
/// IA32 and x64 Specific Functions.\r
//\r
#if defined (MDE_CPU_IA32)\r
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006\r
-#elif defined (MDE_CPU_IPF)\r
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0002\r
#elif defined (MDE_CPU_X64)\r
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007\r
#elif defined (MDE_CPU_ARM)\r
\r
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)\r
\r
-#elif defined (MDE_CPU_IPF)\r
-\r
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
- (((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))\r
-\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
-\r
#elif defined (MDE_CPU_X64)\r
\r
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
\r
#if defined (MDE_CPU_IA32)\r
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32\r
-#elif defined (MDE_CPU_IPF)\r
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA64\r
#elif defined (MDE_CPU_X64)\r
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64\r
#elif defined (MDE_CPU_EBC)\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources.IA32]\r
[Sources.X64]\r
X86Cache.c\r
\r
-[Sources.IPF]\r
- IpfCache.c\r
-\r
[Sources.EBC]\r
EbcCache.c\r
\r
BaseLib\r
DebugLib\r
\r
-[LibraryClasses.Ipf]\r
- PalLib\r
-\r
+++ /dev/null
-/** @file\r
- Cache Maintenance Functions.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/CacheMaintenanceLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PalLib.h>\r
-\r
-/**\r
- Invalidates the entire instruction cache in cache coherency domain of the\r
- calling CPU.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-InvalidateInstructionCache (\r
- VOID\r
- )\r
-{\r
- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
-}\r
-\r
-/**\r
- Invalidates a range of instruction cache lines in the cache coherency domain\r
- of the calling CPU.\r
-\r
- Invalidates the instruction cache lines specified by Address and Length. If\r
- Address is not aligned on a cache line boundary, then entire instruction\r
- cache line containing Address is invalidated. If Address + Length is not\r
- aligned on a cache line boundary, then the entire instruction cache line\r
- containing Address + Length -1 is invalidated. This function may choose to\r
- invalidate the entire instruction cache if that is more efficient than\r
- invalidating the specified range. If Length is 0, then no instruction cache\r
- lines are invalidated. Address is returned.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the instruction cache lines to\r
- invalidate. If the CPU is in a physical addressing mode, then\r
- Address is a physical address. If the CPU is in a virtual\r
- addressing mode, then Address is a virtual address.\r
-\r
- @param Length The number of bytes to invalidate from the instruction cache.\r
-\r
- @return Address.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- )\r
-{\r
- return AsmFlushCacheRange (Address, Length);\r
-}\r
-\r
-/**\r
- Writes back and invalidates the entire data cache in cache coherency domain\r
- of the calling CPU.\r
-\r
- Writes back and invalidates the entire data cache in cache coherency domain\r
- of the calling CPU. This function guarantees that all dirty cache lines are\r
- written back to system memory, and also invalidates all the data cache lines\r
- in the cache coherency domain of the calling CPU.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-WriteBackInvalidateDataCache (\r
- VOID\r
- )\r
-{\r
- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
-}\r
-\r
-/**\r
- Writes back and invalidates a range of data cache lines in the cache\r
- coherency domain of the calling CPU.\r
-\r
- Writes back and invalidates the data cache lines specified by Address and\r
- Length. If Address is not aligned on a cache line boundary, then entire data\r
- cache line containing Address is written back and invalidated. If Address +\r
- Length is not aligned on a cache line boundary, then the entire data cache\r
- line containing Address + Length -1 is written back and invalidated. This\r
- function may choose to write back and invalidate the entire data cache if\r
- that is more efficient than writing back and invalidating the specified\r
- range. If Length is 0, then no data cache lines are written back and\r
- invalidated. Address is returned.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the data cache lines to write back and\r
- invalidate. If the CPU is in a physical addressing mode, then\r
- Address is a physical address. If the CPU is in a virtual\r
- addressing mode, then Address is a virtual address.\r
- @param Length The number of bytes to write back and invalidate from the\r
- data cache.\r
-\r
- @return Address of cache invalidation.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- )\r
-{\r
- return AsmFlushCacheRange (Address, Length);\r
-}\r
-\r
-/**\r
- Writes Back the entire data cache in cache coherency domain of the calling\r
- CPU.\r
-\r
- Writes Back the entire data cache in cache coherency domain of the calling\r
- CPU. This function guarantees that all dirty cache lines are written back to\r
- system memory. This function may also invalidate all the data cache lines in\r
- the cache coherency domain of the calling CPU.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-WriteBackDataCache (\r
- VOID\r
- )\r
-{\r
- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
-}\r
-\r
-/**\r
- Writes Back a range of data cache lines in the cache coherency domain of the\r
- calling CPU.\r
-\r
- Writes Back the data cache lines specified by Address and Length. If Address\r
- is not aligned on a cache line boundary, then entire data cache line\r
- containing Address is written back. If Address + Length is not aligned on a\r
- cache line boundary, then the entire data cache line containing Address +\r
- Length -1 is written back. This function may choose to write back the entire\r
- data cache if that is more efficient than writing back the specified range.\r
- If Length is 0, then no data cache lines are written back. This function may\r
- also invalidate all the data cache lines in the specified range of the cache\r
- coherency domain of the calling CPU. Address is returned.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the data cache lines to write back. If\r
- the CPU is in a physical addressing mode, then Address is a\r
- physical address. If the CPU is in a virtual addressing\r
- mode, then Address is a virtual address.\r
- @param Length The number of bytes to write back from the data cache.\r
-\r
- @return Address of cache written in main memory.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- )\r
-{\r
- return AsmFlushCacheRange (Address, Length);\r
-}\r
-\r
-/**\r
- Invalidates the entire data cache in cache coherency domain of the calling\r
- CPU.\r
-\r
- Invalidates the entire data cache in cache coherency domain of the calling\r
- CPU. This function must be used with care because dirty cache lines are not\r
- written back to system memory. It is typically used for cache diagnostics. If\r
- the CPU does not support invalidation of the entire data cache, then a write\r
- back and invalidate operation should be performed on the entire data cache.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-InvalidateDataCache (\r
- VOID\r
- )\r
-{\r
- //\r
- // Invalidation of the entire data cache without writing back is not supported\r
- // on IPF architecture, so a write back and invalidate operation is performed.\r
- //\r
- WriteBackInvalidateDataCache ();\r
-}\r
-\r
-/**\r
- Invalidates a range of data cache lines in the cache coherency domain of the\r
- calling CPU.\r
-\r
- Invalidates the data cache lines specified by Address and Length. If Address\r
- is not aligned on a cache line boundary, then entire data cache line\r
- containing Address is invalidated. If Address + Length is not aligned on a\r
- cache line boundary, then the entire data cache line containing Address +\r
- Length -1 is invalidated. This function must never invalidate any cache lines\r
- outside the specified range. If Length is 0, then no data cache lines are\r
- invalidated. Address is returned. This function must be used with care\r
- because dirty cache lines are not written back to system memory. It is\r
- typically used for cache diagnostics. If the CPU does not support\r
- invalidation of a data cache range, then a write back and invalidate\r
- operation should be performed on the data cache range.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the data cache lines to invalidate. If\r
- the CPU is in a physical addressing mode, then Address is a\r
- physical address. If the CPU is in a virtual addressing mode,\r
- then Address is a virtual address.\r
- @param Length The number of bytes to invalidate from the data cache.\r
-\r
- @return Address.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- )\r
-{\r
- //\r
- // Invalidation of a data cache range without writing back is not supported on\r
- // IPF architecture, so write back and invalidate operation is performed.\r
- //\r
- return AsmFlushCacheRange (Address, Length);\r
-}\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources.IA32]\r
X64/CpuFlushTlb.nasm| GCC\r
X64/CpuFlushTlb.S | GCC\r
\r
-[Sources.IPF]\r
- Ipf/CpuFlushTlb.s\r
- Ipf/CpuSleep.c\r
-\r
[Sources.EBC]\r
Ebc/CpuSleepFlushTlb.c\r
\r
MdePkg/MdePkg.dec\r
\r
\r
-[LibraryClasses.IPF]\r
- PalLib\r
- BaseLib\r
-\r
+++ /dev/null
-/// @file\r
-/// CpuFlushTlb() function for Itanium-based architecture.\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: CpuFlushTlb.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-ASM_GLOBAL PalCall\r
-.type PalCall, @function\r
-\r
-.proc CpuFlushTlb\r
-.type CpuFlushTlb, @function\r
-CpuFlushTlb::\r
- alloc loc0 = ar.pfs, 0, 3, 5, 0\r
- mov out0 = 0\r
- mov out1 = 6\r
- mov out2 = 0\r
- mov out3 = 0\r
- mov loc1 = b0\r
- mov out4 = 0\r
- brl.call.sptk b0 = PalCall\r
- mov loc2 = psr // save PSR\r
- mov ar.pfs = loc0\r
- extr.u r14 = r10, 32, 32 // r14 <- count1\r
- rsm 1 << 14 // Disable interrupts\r
- extr.u r15 = r11, 32, 32 // r15 <- stride1\r
- extr.u r10 = r10, 0, 32 // r10 <- count2\r
- add r10 = -1, r10\r
- extr.u r11 = r11, 0, 32 // r11 <- stride2\r
- br.cond.sptk LoopPredicate\r
-LoopOuter:\r
- mov ar.lc = r10 // LC <- count2\r
- mov ar.ec = r0 // EC <- 0\r
-Loop:\r
- ptc.e r9\r
- add r9 = r11, r9 // r9 += stride2\r
- br.ctop.sptk Loop\r
- add r9 = r15, r9 // r9 += stride1\r
-LoopPredicate:\r
- cmp.ne p6 = r0, r14 // count1 == 0?\r
- add r14 = -1, r14\r
-(p6) br.cond.sptk LoopOuter\r
- mov psr.l = loc2\r
- mov b0 = loc1\r
- br.ret.sptk.many b0\r
-.endp\r
+++ /dev/null
-/** @file\r
- Base Library CPU functions for Itanium\r
-\r
- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Library/PalLib.h>\r
-#include <Library/BaseLib.h>\r
-\r
-/**\r
- Places the CPU in a sleep state until an interrupt is received.\r
-\r
- Places the CPU in a sleep state until an interrupt is received. If interrupts\r
- are disabled prior to calling this function, then the CPU will be placed in a\r
- sleep state indefinitely.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-CpuSleep (\r
- VOID\r
- )\r
-{\r
- UINT64 Tpr;\r
-\r
- //\r
- // It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state\r
- // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.\r
- // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.\r
- // If interrupts are enabled, then just use current TRP setting.\r
- //\r
- if (GetInterruptState ()) {\r
- //\r
- // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.\r
- //\r
- PalCall (PAL_HALT_LIGHT, 0, 0, 0);\r
- } else {\r
- //\r
- // If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.\r
- //\r
-\r
- //\r
- // Save TPR\r
- //\r
- Tpr = AsmReadTpr();\r
- //\r
- // Set TPR.mmi to mask all external interrupts\r
- //\r
- AsmWriteTpr (BIT16 | Tpr);\r
-\r
- PalCall (PAL_HALT_LIGHT, 0, 0, 0);\r
-\r
- //\r
- // Restore TPR\r
- //\r
- AsmWriteTpr (Tpr);\r
- }\r
-}\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
CONSTRUCTOR = BaseDebugLibSerialPortConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
LIBRARY_CLASS = DebugPrintErrorLevelLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# this ExtractGuidedSectionLib couldn't be used for guided section extraction that is required\r
# by PEI and DXE core for recovery or capsule image processing, etc.\r
#\r
-# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 EBC IPF ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources]\r
IoLibEbc.c\r
IoLib.c\r
\r
-[Sources.IPF]\r
- IoLibIpf.c\r
-\r
[Sources.ARM]\r
IoLibArm.c\r
\r
DebugLib\r
BaseLib\r
\r
-[LibraryClasses.IPF]\r
- PcdLib\r
-\r
-[Pcd.IPF]\r
- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf ## SOMETIMES_CONSUMES\r
-\r
+++ /dev/null
-/** @file\r
- Common I/O Library routines.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-\r
-#include "BaseIoLibIntrinsicInternal.h"\r
-#include <Library/PcdLib.h>\r
-\r
-#define MAP_PORT_BASE_TO_MEM(_Port) \\r
- ((((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff))\r
-\r
-/**\r
- Translates I/O port address to memory address.\r
-\r
- This function translates I/O port address to memory address by adding the 64MB\r
- aligned I/O Port space to the I/O address.\r
- If I/O Port space base is not 64MB aligned, then ASSERT ().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The memory address.\r
-\r
-**/\r
-UINTN\r
-InternalGetMemoryMapAddress (\r
- IN UINTN Port\r
- )\r
-{\r
- UINTN Address;\r
- UINTN IoBlockBaseAddress;\r
-\r
- Address = MAP_PORT_BASE_TO_MEM (Port);\r
- IoBlockBaseAddress = PcdGet64(PcdIoBlockBaseAddressForIpf);\r
-\r
- //\r
- // Make sure that the I/O Port space base is 64MB aligned.\r
- //\r
- ASSERT ((IoBlockBaseAddress & 0x3ffffff) == 0);\r
- Address += IoBlockBaseAddress;\r
-\r
- return Address;\r
-}\r
-\r
-/**\r
- Reads an 8-bit I/O port.\r
-\r
- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoRead8 (\r
- IN UINTN Port\r
- )\r
-{\r
- return MmioRead8 (InternalGetMemoryMapAddress (Port));\r
-}\r
-\r
-/**\r
- Reads a 16-bit I/O port.\r
-\r
- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
- If Port is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoRead16 (\r
- IN UINTN Port\r
- )\r
-{\r
- return MmioRead16 (InternalGetMemoryMapAddress (Port));\r
-}\r
-\r
-/**\r
- Reads a 32-bit I/O port.\r
-\r
- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
- If Port is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoRead32 (\r
- IN UINTN Port\r
- )\r
-{\r
- return MmioRead32 (InternalGetMemoryMapAddress (Port));\r
-}\r
-\r
-/**\r
- Reads a 64-bit I/O port.\r
-\r
- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
- If Port is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoRead64 (\r
- IN UINTN Port\r
- )\r
-{\r
- ASSERT (FALSE);\r
- return 0;\r
-}\r
-\r
-\r
-/**\r
- Writes an 8-bit I/O port.\r
-\r
- Writes the 8-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
- )\r
-{\r
- return MmioWrite8 (InternalGetMemoryMapAddress (Port), Value);\r
-}\r
-\r
-/**\r
- Writes a 16-bit I/O port.\r
-\r
- Writes the 16-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
- If Port is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
- )\r
-{\r
- return MmioWrite16 (InternalGetMemoryMapAddress (Port), Value);\r
-}\r
-\r
-/**\r
- Writes a 32-bit I/O port.\r
-\r
- Writes the 32-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
- If Port is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
- )\r
-{\r
- return MmioWrite32 (InternalGetMemoryMapAddress (Port), Value);\r
-}\r
-\r
-/**\r
- Writes a 64-bit I/O port.\r
-\r
- Writes the 64-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
- If Port is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
- )\r
-{\r
- ASSERT (FALSE);\r
- return 0;\r
-}\r
-\r
-/**\r
- Reads an 8-bit I/O port fifo into a block of memory.\r
-\r
- Reads the 8-bit I/O fifo port specified by Port.\r
- The port is read Count times, and the read data is\r
- stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINT8 *Buffer8;\r
-\r
- Buffer8 = (UINT8 *)Buffer;\r
- while (Count-- > 0) {\r
- *Buffer8++ = IoRead8 (Port);\r
- }\r
-}\r
-\r
-/**\r
- Reads a 16-bit I/O port fifo into a block of memory.\r
-\r
- Reads the 16-bit I/O fifo port specified by Port.\r
- The port is read Count times, and the read data is\r
- stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINT16 *Buffer16;\r
-\r
- Buffer16 = (UINT16 *)Buffer;\r
- while (Count-- > 0) {\r
- *Buffer16++ = IoRead16 (Port);\r
- }\r
-}\r
-\r
-/**\r
- Reads a 32-bit I/O port fifo into a block of memory.\r
-\r
- Reads the 32-bit I/O fifo port specified by Port.\r
- The port is read Count times, and the read data is\r
- stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINT32 *Buffer32;\r
-\r
- Buffer32 = (UINT32 *)Buffer;\r
- while (Count-- > 0) {\r
- *Buffer32++ = IoRead32 (Port);\r
- }\r
-}\r
-\r
-/**\r
- Writes a block of memory into an 8-bit I/O port fifo.\r
-\r
- Writes the 8-bit I/O fifo port specified by Port.\r
- The port is written Count times, and the write data is\r
- retrieved from the provided Buffer.\r
-\r
- This function must guarantee that all I/O write and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Count The number of times to write I/O port.\r
- @param Buffer The buffer to retrieve the write data from.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINT8 *Buffer8;\r
-\r
- Buffer8 = (UINT8 *)Buffer;\r
- while (Count-- > 0) {\r
- IoWrite8 (Port, *Buffer8++);\r
- }\r
-}\r
-\r
-/**\r
- Writes a block of memory into a 16-bit I/O port fifo.\r
-\r
- Writes the 16-bit I/O fifo port specified by Port.\r
- The port is written Count times, and the write data is\r
- retrieved from the provided Buffer.\r
-\r
- This function must guarantee that all I/O write and write operations are\r
- serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Count The number of times to write I/O port.\r
- @param Buffer The buffer to retrieve the write data from.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINT16 *Buffer16;\r
-\r
- Buffer16 = (UINT16 *)Buffer;\r
- while (Count-- > 0) {\r
- IoWrite16 (Port, *Buffer16++);\r
- }\r
-}\r
-\r
-/**\r
- Writes a block of memory into a 32-bit I/O port fifo.\r
-\r
- Writes the 32-bit I/O fifo port specified by Port.\r
- The port is written Count times, and the write data is\r
- retrieved from the provided Buffer.\r
-\r
- This function must guarantee that all I/O write and write operations are\r
- serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Count The number of times to write I/O port.\r
- @param Buffer The buffer to retrieve the write data from.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINT32 *Buffer32;\r
-\r
- Buffer32 = (UINT32 *)Buffer;\r
- while (Count-- > 0) {\r
- IoWrite32 (Port, *Buffer32++);\r
- }\r
-}\r
-\r
-/**\r
- Reads an 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioRead8 (\r
- IN UINTN Address\r
- )\r
-{\r
- UINT8 Data;\r
-\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- Data = *((volatile UINT8 *) Address);\r
- MemoryFence ();\r
-\r
- return Data;\r
-}\r
-\r
-/**\r
- Reads a 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioRead16 (\r
- IN UINTN Address\r
- )\r
-{\r
- UINT16 Data;\r
-\r
- //\r
- // Make sure that Address is 16-bit aligned.\r
- //\r
- ASSERT ((Address & 1) == 0);\r
-\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- Data = *((volatile UINT16 *) Address);\r
- MemoryFence ();\r
-\r
- return Data;\r
-}\r
-\r
-/**\r
- Reads a 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioRead32 (\r
- IN UINTN Address\r
- )\r
-{\r
- UINT32 Data;\r
-\r
- //\r
- // Make sure that Address is 32-bit aligned.\r
- //\r
- ASSERT ((Address & 3) == 0);\r
-\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- Data = *((volatile UINT32 *) Address);\r
- MemoryFence ();\r
-\r
- return Data;\r
-}\r
-\r
-/**\r
- Reads a 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
- If Address is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioRead64 (\r
- IN UINTN Address\r
- )\r
-{\r
- UINT64 Data;\r
-\r
- //\r
- // Make sure that Address is 64-bit aligned.\r
- //\r
- ASSERT ((Address & 7) == 0);\r
-\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- Data = *((volatile UINT64 *) Address);\r
- MemoryFence ();\r
-\r
- return Data;\r
-\r
-}\r
-\r
-/**\r
- Writes an 8-bit MMIO register.\r
-\r
- Writes the 8-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
- @return Value.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
- )\r
-{\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- *((volatile UINT8 *) Address) = Value;\r
- MemoryFence ();\r
-\r
- return Value;\r
-}\r
-\r
-/**\r
- Writes a 16-bit MMIO register.\r
-\r
- Writes the 16-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
- @return Value.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
- )\r
-{\r
- //\r
- // Make sure that Address is 16-bit aligned.\r
- //\r
- ASSERT ((Address & 1) == 0);\r
-\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- *((volatile UINT16 *) Address) = Value;\r
- MemoryFence ();\r
-\r
- return Value;\r
-}\r
-\r
-/**\r
- Writes a 32-bit MMIO register.\r
-\r
- Writes the 32-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
- @return Value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
- )\r
-{\r
- //\r
- // Make sure that Address is 32-bit aligned.\r
- //\r
- ASSERT ((Address & 3) == 0);\r
-\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- *((volatile UINT32 *) Address) = Value;\r
- MemoryFence ();\r
-\r
- return Value;\r
-}\r
-\r
-/**\r
- Writes a 64-bit MMIO register.\r
-\r
- Writes the 64-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
- If Address is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
- )\r
-{\r
- //\r
- // Make sure that Address is 64-bit aligned.\r
- //\r
- ASSERT ((Address & 7) == 0);\r
-\r
- Address |= BIT63;\r
-\r
- MemoryFence ();\r
- *((volatile UINT64 *) Address) = Value;\r
- MemoryFence ();\r
-\r
- return Value;\r
-}\r
LIBRARY_CLASS = BaseLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources]\r
X64/RdRand.S | GCC\r
ChkStkGcc.c | GCC\r
\r
-[Sources.IPF]\r
- Ipf/AccessGp.s\r
- Ipf/ReadCpuid.s\r
- Ipf/ExecFc.s\r
- Ipf/AsmPalCall.s\r
- Ipf/AccessPsr.s\r
- Ipf/AccessPmr.s\r
- Ipf/AccessKr.s\r
- Ipf/AccessKr7.s\r
- Ipf/AccessGcr.s\r
- Ipf/AccessEicr.s\r
- Ipf/AccessDbr.s\r
- Ipf/AccessMsr.s | INTEL\r
- Ipf/AccessMsr.s | GCC\r
- Ipf/AccessMsrDb.s | MSFT\r
- Ipf/InternalFlushCacheRange.s\r
- Ipf/FlushCacheRange.c\r
- Ipf/InternalSwitchStack.c\r
- Ipf/GetInterruptState.s\r
- Ipf/CpuPause.s\r
- Ipf/CpuBreakpoint.c | INTEL\r
- Ipf/CpuBreakpointMsc.c | MSFT\r
- Ipf/AsmCpuMisc.s | GCC\r
- Ipf/Unaligned.c\r
- Ipf/SwitchStack.s\r
- Ipf/LongJmp.s\r
- Ipf/SetJmp.s\r
- Ipf/ReadCr.s\r
- Ipf/ReadAr.s\r
- Ipf/Ia64gen.h\r
- Ipf/Asm.h\r
- Math64.c\r
-\r
[Sources.EBC]\r
Ebc/CpuBreakpoint.c\r
Ebc/SetJumpLongJump.c\r
/** @file\r
Declaration of internal functions in BaseLib.\r
\r
- Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
OUT UINT64 *Rand\r
);\r
\r
-\r
-#elif defined (MDE_CPU_IPF)\r
-//\r
-//\r
-// IPF specific functions\r
-//\r
-\r
-/**\r
- Reads control register DCR.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_DCR.\r
-\r
- @return The 64-bit control register DCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterDcr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register ITM.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_ITM.\r
-\r
- @return The 64-bit control register ITM.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterItm (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IVA.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IVA.\r
-\r
- @return The 64-bit control register IVA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIva (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register PTA.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_PTA.\r
-\r
- @return The 64-bit control register PTA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterPta (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IPSR.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IPSR.\r
-\r
- @return The 64-bit control register IPSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIpsr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register ISR.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_ISR.\r
-\r
- @return The 64-bit control register ISR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIsr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IIP.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IIP.\r
-\r
- @return The 64-bit control register IIP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIip (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IFA.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IFA.\r
-\r
- @return The 64-bit control register IFA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIfa (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register ITIR.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_ITIR.\r
-\r
- @return The 64-bit control register ITIR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterItir (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IIPA.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IIPA.\r
-\r
- @return The 64-bit control register IIPA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIipa (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IFS.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IFS.\r
-\r
- @return The 64-bit control register IFS.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIfs (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IIM.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IIM.\r
-\r
- @return The 64-bit control register IIM.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIim (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IHA.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IHA.\r
-\r
- @return The 64-bit control register IHA.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIha (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register LID.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_LID.\r
-\r
- @return The 64-bit control register LID.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterLid (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IVR.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IVR.\r
-\r
- @return The 64-bit control register IVR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIvr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register TPR.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_TPR.\r
-\r
- @return The 64-bit control register TPR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterTpr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register EOI.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_EOI.\r
-\r
- @return The 64-bit control register EOI.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterEoi (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IRR0.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IRR0.\r
-\r
- @return The 64-bit control register IRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IRR1.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IRR1.\r
-\r
- @return The 64-bit control register IRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IRR2.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IRR2.\r
-\r
- @return The 64-bit control register IRR2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIrr2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register IRR3.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_IRR3.\r
-\r
- @return The 64-bit control register IRR3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterIrr3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register ITV.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_ITV.\r
-\r
- @return The 64-bit control register ITV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterItv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register PMV.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_PMV.\r
-\r
- @return The 64-bit control register PMV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterPmv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register CMCV.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_CMCV.\r
-\r
- @return The 64-bit control register CMCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterCmcv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register LRR0.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_LRR0.\r
-\r
- @return The 64-bit control register LRR0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterLrr0 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads control register LRR1.\r
-\r
- This is a worker function for AsmReadControlRegister()\r
- when its parameter Index is IPF_CONTROL_REGISTER_LRR1.\r
-\r
- @return The 64-bit control register LRR1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadControlRegisterLrr1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register K0.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K0.\r
-\r
- @return The 64-bit application register K0.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK0 (\r
- VOID\r
- );\r
-\r
-\r
-\r
-/**\r
- Reads application register K1.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K1.\r
-\r
- @return The 64-bit application register K1.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK1 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register K2.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K2.\r
-\r
- @return The 64-bit application register K2.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK2 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register K3.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K3.\r
-\r
- @return The 64-bit application register K3.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK3 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register K4.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K4.\r
-\r
- @return The 64-bit application register K4.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK4 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register K5.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K5.\r
-\r
- @return The 64-bit application register K5.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK5 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register K6.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K6.\r
-\r
- @return The 64-bit application register K6.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK6 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register K7.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_K7.\r
-\r
- @return The 64-bit application register K7.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterK7 (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register RSC.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_RSC.\r
-\r
- @return The 64-bit application register RSC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterRsc (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register BSP.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_BSP.\r
-\r
- @return The 64-bit application register BSP.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterBsp (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register BSPSTORE.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_BSPSTORE.\r
-\r
- @return The 64-bit application register BSPSTORE.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterBspstore (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register RNAT.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_RNAT.\r
-\r
- @return The 64-bit application register RNAT.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterRnat (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register FCR.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_FCR.\r
-\r
- @return The 64-bit application register FCR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterFcr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register EFLAG.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_EFLAG.\r
-\r
- @return The 64-bit application register EFLAG.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterEflag (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register CSD.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_CSD.\r
-\r
- @return The 64-bit application register CSD.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterCsd (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register SSD.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_SSD.\r
-\r
- @return The 64-bit application register SSD.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterSsd (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register CFLG.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_CFLG.\r
-\r
- @return The 64-bit application register CFLG.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterCflg (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register FSR.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_FSR.\r
-\r
- @return The 64-bit application register FSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterFsr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register FIR.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_FIR.\r
-\r
- @return The 64-bit application register FIR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterFir (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register FDR.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_FDR.\r
-\r
- @return The 64-bit application register FDR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterFdr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register CCV.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_CCV.\r
-\r
- @return The 64-bit application register CCV.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterCcv (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register UNAT.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_UNAT.\r
-\r
- @return The 64-bit application register UNAT.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterUnat (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register FPSR.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_FPSR.\r
-\r
- @return The 64-bit application register FPSR.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterFpsr (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register ITC.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_ITC.\r
-\r
- @return The 64-bit application register ITC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterItc (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register PFS.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_PFS.\r
-\r
- @return The 64-bit application register PFS.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterPfs (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register LC.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_LC.\r
-\r
- @return The 64-bit application register LC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterLc (\r
- VOID\r
- );\r
-\r
-\r
-/**\r
- Reads application register EC.\r
-\r
- This is a worker function for AsmReadApplicationRegister()\r
- when its parameter Index is IPF_APPLICATION_REGISTER_EC.\r
-\r
- @return The 64-bit application register EC.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-AsmReadApplicationRegisterEc (\r
- VOID\r
- );\r
-\r
-\r
-\r
-/**\r
- Transfers control to a function starting with a new stack.\r
-\r
- Transfers control to the function specified by EntryPoint using the new stack\r
- specified by NewStack and passing in the parameters specified by Context1 and\r
- Context2. Context1 and Context2 are optional and may be NULL. The function\r
- EntryPoint must never return.\r
-\r
- If EntryPoint is NULL, then ASSERT().\r
- If NewStack is NULL, then ASSERT().\r
-\r
- @param EntryPoint A pointer to function to call with the new stack.\r
- @param Context1 A pointer to the context to pass into the EntryPoint\r
- function.\r
- @param Context2 A pointer to the context to pass into the EntryPoint\r
- function.\r
- @param NewStack A pointer to the new stack to use for the EntryPoint\r
- function.\r
- @param NewBsp A pointer to the new memory location for RSE backing\r
- store.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmSwitchStackAndBackingStore (\r
- IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
- IN VOID *Context1, OPTIONAL\r
- IN VOID *Context2, OPTIONAL\r
- IN VOID *NewStack,\r
- IN VOID *NewBsp\r
- );\r
-\r
-/**\r
- Internal worker function to invalidate a range of instruction cache lines\r
- in the cache coherency domain of the calling CPU.\r
-\r
- Internal worker function to invalidate the instruction cache lines specified\r
- by Address and Length. If Address is not aligned on a cache line boundary,\r
- then entire instruction cache line containing Address is invalidated. If\r
- Address + Length is not aligned on a cache line boundary, then the entire\r
- instruction cache line containing Address + Length -1 is invalidated. This\r
- function may choose to invalidate the entire instruction cache if that is more\r
- efficient than invalidating the specified range. If Length is 0, the no instruction\r
- cache lines are invalidated. Address is returned.\r
- This function is only available on IPF.\r
-\r
- @param Address The base address of the instruction cache lines to\r
- invalidate. If the CPU is in a physical addressing mode, then\r
- Address is a physical address. If the CPU is in a virtual\r
- addressing mode, then Address is a virtual address.\r
-\r
- @param Length The number of bytes to invalidate from the instruction cache.\r
-\r
- @return Address\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-InternalFlushCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- );\r
-\r
#else\r
\r
#endif\r
+++ /dev/null
-/// @file\r
-/// IPF specific Debug Breakpoint Registers accessing functions\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessDbr.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadDbr\r
-//\r
-// This routine is used to Reads the current value of Data Breakpoint Register (DBR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit DBR index to read.\r
-//\r
-// Return Value: The current value of DBR by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadDbr, @function\r
-.proc AsmReadDbr\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadDbr::\r
- mov r8 = dbr[in0];;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadDbr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteDbr\r
-//\r
-// This routine is used to write the current value to Data Breakpoint Register (DBR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit DBR index to read.\r
-// The value should be written to DBR\r
-//\r
-// Return Value: The value written to DBR.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteDbr, @function\r
-.proc AsmWriteDbr\r
-.regstk 2, 0, 0, 0\r
-\r
-AsmWriteDbr::\r
- mov dbr[in0] = in1\r
- mov r8 = in1;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteDbr\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadIbr\r
-//\r
-// This routine is used to Reads the current value of Instruction Breakpoint Register (IBR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit IBR index.\r
-//\r
-// Return Value: The current value of IBR by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadIbr, @function\r
-.proc AsmReadIbr\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadIbr::\r
- mov r8 = ibr[in0];;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadIbr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteIbr\r
-//\r
-// This routine is used to write the current value to Instruction Breakpoint Register (IBR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit IBR index.\r
-// The value should be written to IBR\r
-//\r
-// Return Value: The value written to IBR.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteIbr, @function\r
-.proc AsmWriteIbr\r
-.regstk 2, 0, 0, 0\r
-\r
-AsmWriteIbr::\r
- mov ibr[in0] = in1\r
- mov r8 = in1;;\r
- srlz.i;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteIbr\r
+++ /dev/null
-/// @file\r
-/// IPF specific External Interrupt Control Registers accessing functions\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessEicr.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadLid\r
-//\r
-// This routine is used to read the value of Local Interrupt ID Register (LID).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of LID.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadLid, @function\r
-.proc AsmReadLid\r
-\r
-AsmReadLid::\r
- mov r8 = cr.lid;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadLid\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteLid\r
-//\r
-// This routine is used to write the value to Local Interrupt ID Register (LID).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to LID.\r
-//\r
-// Return Value: The value written to LID.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteLid, @function\r
-.proc AsmWriteLid\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteLid::\r
- mov cr.lid = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteLid\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadIvr\r
-//\r
-// This routine is used to read the value of External Interrupt Vector Register (IVR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of IVR.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadIvr, @function\r
-.proc AsmReadIvr\r
-\r
-AsmReadIvr::\r
- mov r8 = cr.ivr;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadIvr\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadTpr\r
-//\r
-// This routine is used to read the value of Task Priority Register (TPR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of TPR.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadTpr, @function\r
-.proc AsmReadTpr\r
-\r
-AsmReadTpr::\r
- mov r8 = cr.tpr;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadTpr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteTpr\r
-//\r
-// This routine is used to write the value to Task Priority Register (TPR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to TPR.\r
-//\r
-// Return Value: The value written to TPR.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteTpr, @function\r
-.proc AsmWriteTpr\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteTpr::\r
- mov cr.tpr = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteTpr\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteEoi\r
-//\r
-// This routine is used to write the value to End of External Interrupt Register (EOI).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to EOI.\r
-//\r
-// Return Value: The value written to EOI.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteEoi, @function\r
-.proc AsmWriteEoi\r
-\r
-AsmWriteEoi::\r
- mov cr.eoi = r0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteEoi\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadIrr0\r
-//\r
-// This routine is used to Read the value of External Interrupt Request Register 0 (IRR0).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of IRR0.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadIrr0, @function\r
-.proc AsmReadIrr0\r
-\r
-AsmReadIrr0::\r
- mov r8 = cr.irr0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadIrr0\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadIrr1\r
-//\r
-// This routine is used to Read the value of External Interrupt Request Register 1 (IRR1).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of IRR1.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadIrr1, @function\r
-.proc AsmReadIrr1\r
-\r
-AsmReadIrr1::\r
- mov r8 = cr.irr1;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadIrr1\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadIrr2\r
-//\r
-// This routine is used to Read the value of External Interrupt Request Register 2 (IRR2).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of IRR2.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadIrr2, @function\r
-.proc AsmReadIrr2\r
-\r
-AsmReadIrr2::\r
- mov r8 = cr.irr2;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadIrr2\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadIrr3\r
-//\r
-// This routine is used to Read the value of External Interrupt Request Register 3 (IRR3).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of IRR3.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadIrr3, @function\r
-.proc AsmReadIrr3\r
-\r
-AsmReadIrr3::\r
- mov r8 = cr.irr3;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadIrr3\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadItv\r
-//\r
-// This routine is used to Read the value of Interval Timer Vector Register (ITV).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of ITV.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadItv, @function\r
-.proc AsmReadItv\r
-\r
-AsmReadItv::\r
- mov r8 = cr.itv;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadItv\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteItv\r
-//\r
-// This routine is used to write the value to Interval Timer Vector Register (ITV).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to ITV\r
-//\r
-// Return Value: The value written to ITV.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteItv, @function\r
-.proc AsmWriteItv\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteItv::\r
- mov cr.itv = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteItv\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadPmv\r
-//\r
-// This routine is used to Read the value of Performance Monitoring Vector Register (PMV).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of PMV.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadPmv, @function\r
-.proc AsmReadPmv\r
-\r
-AsmReadPmv::\r
- mov r8 = cr.pmv;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadPmv\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWritePmv\r
-//\r
-// This routine is used to write the value to Performance Monitoring Vector Register (PMV).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to PMV\r
-//\r
-// Return Value: The value written to PMV.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWritePmv, @function\r
-.proc AsmWritePmv\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWritePmv::\r
- mov cr.pmv = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWritePmv\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadCmcv\r
-//\r
-// This routine is used to Read the value of Corrected Machine Check Vector Register (CMCV).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of CMCV.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadCmcv, @function\r
-.proc AsmReadCmcv\r
-\r
-AsmReadCmcv::\r
- mov r8 = cr.cmcv;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadCmcv\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteCmcv\r
-//\r
-// This routine is used to write the value to Corrected Machine Check Vector Register (CMCV).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to CMCV\r
-//\r
-// Return Value: The value written to CMCV.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteCmcv, @function\r
-.proc AsmWriteCmcv\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteCmcv::\r
- mov cr.cmcv = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteCmcv\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadLrr0\r
-//\r
-// This routine is used to read the value of Local Redirection Register 0 (LRR0).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of LRR0.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadLrr0, @function\r
-.proc AsmReadLrr0\r
-\r
-AsmReadLrr0::\r
- mov r8 = cr.lrr0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadLrr0\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteLrr0\r
-//\r
-// This routine is used to write the value to Local Redirection Register 0 (LRR0).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to LRR0.\r
-//\r
-// Return Value: The value written to LRR0.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteLrr0, @function\r
-.proc AsmWriteLrr0\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteLrr0::\r
- mov cr.lrr0 = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteLrr0\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadLrr1\r
-//\r
-// This routine is used to read the value of Local Redirection Register 1 (LRR1).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of LRR1.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadLrr1, @function\r
-.proc AsmReadLrr1\r
-\r
-AsmReadLrr1::\r
- mov r8 = cr.lrr1;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadLrr1\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteLrr1\r
-//\r
-// This routine is used to write the value to Local Redirection Register 1 (LRR1).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to LRR1.\r
-//\r
-// Return Value: The value written to LRR1.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteLrr1, @function\r
-.proc AsmWriteLrr1\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteLrr1::\r
- mov cr.lrr1 = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteLrr1\r
-\r
+++ /dev/null
-/// @file\r
-/// IPF specific Global Control Registers accessing functions\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessGcr.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadDcr\r
-//\r
-// This routine is used to Read the value of Default Control Register (DCR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of DCR.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadDcr, @function\r
-.proc AsmReadDcr\r
-\r
-AsmReadDcr::\r
- mov r8 = cr.dcr;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadDcr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteDcr\r
-//\r
-// This routine is used to write the value to Default Control Register (DCR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to DCR\r
-//\r
-// Return Value: The value written to DCR.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteDcr, @function\r
-.proc AsmWriteDcr\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteDcr::\r
- mov cr.dcr = in0\r
- mov r8 = in0;;\r
- srlz.i;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteDcr\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadItc\r
-//\r
-// This routine is used to Read the value of Interval Timer Counter Register (ITC).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of ITC.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadItc, @function\r
-.proc AsmReadItc\r
-\r
-AsmReadItc::\r
- mov r8 = ar.itc;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadItc\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteItc\r
-//\r
-// This routine is used to write the value to Interval Timer Counter Register (ITC).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to the ITC\r
-//\r
-// Return Value: The value written to the ITC.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteItc, @function\r
-.proc AsmWriteItc\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteItc::\r
- mov ar.itc = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteItc\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadItm\r
-//\r
-// This routine is used to Read the value of Interval Timer Match Register (ITM).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of ITM.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadItm, @function\r
-.proc AsmReadItm\r
-\r
-AsmReadItm::\r
- mov r8 = cr.itm;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadItm\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteItm\r
-//\r
-// This routine is used to write the value to Interval Timer Match Register (ITM).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to ITM\r
-//\r
-// Return Value: The value written to ITM.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteItm, @function\r
-.proc AsmWriteItm\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteItm::\r
- mov cr.itm = in0\r
- mov r8 = in0;;\r
- srlz.d;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteItm\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadIva\r
-//\r
-// This routine is used to read the value of Interruption Vector Address Register (IVA).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of IVA.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadIva, @function\r
-.proc AsmReadIva\r
-\r
-AsmReadIva::\r
- mov r8 = cr.iva;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadIva\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteIva\r
-//\r
-// This routine is used to write the value to Interruption Vector Address Register (IVA).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to IVA\r
-//\r
-// Return Value: The value written to IVA.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteIva, @function\r
-.proc AsmWriteIva\r
-.regstk 1, 3, 0, 0\r
-\r
-AsmWriteIva::\r
- alloc loc1=ar.pfs,1,4,0,0 ;;\r
-\r
- mov loc2 = psr\r
- rsm 0x6000 // Make sure interrupts are masked\r
-\r
- mov cr.iva = in0\r
- srlz.i;;\r
- mov psr.l = loc2;;\r
- srlz.i;;\r
- srlz.d;;\r
- mov ar.pfs=loc1 ;;\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteIva\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadPta\r
-//\r
-// This routine is used to read the value of Page Table Address Register (PTA).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current value of PTA.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadPta, @function\r
-.proc AsmReadPta\r
-\r
-AsmReadPta::\r
- mov r8 = cr.pta;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadPta\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWritePta\r
-//\r
-// This routine is used to write the value to Page Table Address Register (PTA)).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written to PTA\r
-//\r
-// Return Value: The value written to PTA.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWritePta, @function\r
-.proc AsmWritePta\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWritePta::\r
- mov cr.pta = in0\r
- mov r8 = in0;;\r
- srlz.i;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWritePta\r
+++ /dev/null
-/// @file\r
-/// IPF specific Global Pointer and Stack Pointer accessing functions\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessGp.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadGp\r
-//\r
-// This routine is used to read the current value of 64-bit Global Pointer (GP).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current GP value.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadGp, @function\r
-.proc AsmReadGp\r
-\r
-AsmReadGp::\r
- mov r8 = gp;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadGp\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteGp\r
-//\r
-// This routine is used to write the current value of 64-bit Global Pointer (GP).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written.\r
-//\r
-// Return Value: The value have been written.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteGp, @function\r
-.proc AsmWriteGp\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWriteGp::\r
- mov gp = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteGp\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadSp\r
-//\r
-// This routine is used to read the current value of 64-bit Stack Pointer (SP).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current SP value.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadSp, @function\r
-.proc AsmReadSp\r
-\r
-AsmReadSp::\r
- mov r8 = sp;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadSp\r
+++ /dev/null
-/// @file\r
-/// IPF specific AsmReadKrX() and AsmWriteKrX() functions, 'X' is from '0' to '6'\r
-///\r
-/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessKr.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr0\r
-//\r
-// This routine is used to get KR0.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR0.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr0, @function\r
-.proc AsmReadKr0\r
-\r
-AsmReadKr0::\r
- mov r8 = ar.k0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr0\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr0\r
-//\r
-// This routine is used to Write KR0.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR0.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-\r
-.text\r
-.type AsmWriteKr0, @function\r
-.proc AsmWriteKr0\r
-.regstk 1, 3, 0, 0\r
-\r
-AsmWriteKr0::\r
- alloc loc1=ar.pfs,1,4,0,0 ;;\r
- mov loc2 = psr;;\r
- rsm 0x6000;; // Masking interrupts\r
- mov ar.k0 = in0\r
- srlz.i;;\r
- mov psr.l = loc2;;\r
- srlz.i;;\r
- srlz.d;;\r
- mov r8 = in0;;\r
- mov ar.pfs=loc1 ;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr0\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr1\r
-//\r
-// This routine is used to get KR1.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR1.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr1, @function\r
-.proc AsmReadKr1\r
-\r
-AsmReadKr1::\r
- mov r8 = ar.k1;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr1\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr1\r
-//\r
-// This routine is used to Write KR1.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR1.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteKr1, @function\r
-.proc AsmWriteKr1\r
-\r
-AsmWriteKr1::\r
- mov ar.k1 = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr1\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr2\r
-//\r
-// This routine is used to get KR2.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR2.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr2, @function\r
-.proc AsmReadKr2\r
-\r
-AsmReadKr2::\r
- mov r8 = ar.k2;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr2\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr2\r
-//\r
-// This routine is used to Write KR2.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR2.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteKr2, @function\r
-.proc AsmWriteKr2\r
-\r
-AsmWriteKr2::\r
- mov ar.k2 = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr2\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr3\r
-//\r
-// This routine is used to get KR3.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR3.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr3, @function\r
-.proc AsmReadKr3\r
-\r
-AsmReadKr3::\r
- mov r8 = ar.k3;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr3\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr3\r
-//\r
-// This routine is used to Write KR3.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR3.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteKr3, @function\r
-.proc AsmWriteKr3\r
-\r
-AsmWriteKr3::\r
- mov ar.k3 = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr3\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr4\r
-//\r
-// This routine is used to get KR4.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR4.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr4, @function\r
-.proc AsmReadKr4\r
-\r
-AsmReadKr4::\r
- mov r8 = ar.k4;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr4\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr4\r
-//\r
-// This routine is used to Write KR4.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR4.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteKr4, @function\r
-.proc AsmWriteKr4\r
-\r
-AsmWriteKr4::\r
- mov ar.k4 = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr4\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr5\r
-//\r
-// This routine is used to get KR5.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR5.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr5, @function\r
-.proc AsmReadKr5\r
-\r
-AsmReadKr5::\r
- mov r8 = ar.k5;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr5\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr5\r
-//\r
-// This routine is used to Write KR5.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR5.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteKr5, @function\r
-.proc AsmWriteKr5\r
-\r
-AsmWriteKr5::\r
- mov ar.k5 = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr5\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr6\r
-//\r
-// This routine is used to get KR6.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR6.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr6, @function\r
-.proc AsmReadKr6\r
-\r
-AsmReadKr6::\r
- mov r8 = ar.k6;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr6\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr6\r
-//\r
-// This routine is used to write KR6.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR6.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteKr6, @function\r
-.proc AsmWriteKr6\r
-\r
-AsmWriteKr6::\r
- mov ar.k6 = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr6\r
+++ /dev/null
-/// @file\r
-/// IPF specific AsmReadKr7() and AsmWriteKr7()\r
-///\r
-/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessKr7.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadKr7\r
-//\r
-// This routine is used to get KR7.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value store in KR7.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadKr7, @function\r
-.proc AsmReadKr7\r
-\r
-AsmReadKr7::\r
- mov r8 = ar.k7;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadKr7\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteKr7\r
-//\r
-// This routine is used to write KR7.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : None.\r
-//\r
-// Return Value: The value written to the KR7.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteKr7, @function\r
-.proc AsmWriteKr7\r
-.regstk 1, 3, 0, 0\r
-\r
-AsmWriteKr7::\r
- mov ar.k7 = in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWriteKr7\r
+++ /dev/null
-/// @file\r
-/// IPF specific Machine Specific Registers accessing functions.\r
-///\r
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-///\r
-///\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadMsr\r
-//\r
-// Reads the current value of a Machine Specific Register (MSR).\r
-//\r
-// Reads and returns the current value of the Machine Specific Register specified by Index. No\r
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
-// only available on IPF.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit Machine Specific Register index to read.\r
-//\r
-// Return Value: The current value of the Machine Specific Register specified by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadMsr, @function\r
-.proc AsmReadMsr\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadMsr::\r
- mov r8=msr[in0];;\r
- br.ret.sptk b0;;\r
-.endp AsmReadMsr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteMsr\r
-//\r
-// Writes the current value of a Machine Specific Register (MSR).\r
-//\r
-// Writes Value to the Machine Specific Register specified by Index. Value is returned. No\r
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
-// only available on IPF.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit Machine Specific Register index to write.\r
-// The 64-bit value to write to the Machine Specific Register.\r
-//\r
-// Return Value: The 64-bit value to write to the Machine Specific Register.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteMsr, @function\r
-.proc AsmWriteMsr\r
-.regstk 2, 0, 0, 0\r
-\r
-AsmWriteMsr::\r
- mov msr[in0] = in1\r
- mov r8 = in1;;\r
- srlz.d;;\r
- br.ret.sptk b0;;\r
-.endp AsmWriteMsr\r
-\r
+++ /dev/null
-/// @file\r
-/// IPF specific Machine Specific Registers accessing functions. \r
-/// This implementation uses raw data to prepresent the assembly instruction of \r
-/// mov msr[]= and mov =msr[].\r
-///\r
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-///\r
-///\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadMsr\r
-//\r
-// Reads the current value of a Machine Specific Register (MSR).\r
-//\r
-// Reads and returns the current value of the Machine Specific Register specified by Index. No\r
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
-// only available on IPF.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit Machine Specific Register index to read.\r
-//\r
-// Return Value: The current value of the Machine Specific Register specified by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadMsr, @function\r
-.proc AsmReadMsr\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadMsr::\r
-//\r
-// The follow 16 bytes stand for the bundle of \r
-// mov r8=msr[in0];;\r
-// since MSFT tool chain does not support mov =msr[] instruction\r
-//\r
- data1 0x0D\r
- data1 0x40\r
- data1 0x00\r
- data1 0x40\r
- data1 0x16\r
- data1 0x04\r
- data1 0x00\r
- data1 0x00\r
- data1 0x00\r
- data1 0x02\r
- data1 0x00\r
- data1 0x00\r
- data1 0x00\r
- data1 0x00\r
- data1 0x04\r
- data1 0x00\r
- br.ret.sptk b0;;\r
-.endp AsmReadMsr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWriteMsr\r
-//\r
-// Writes the current value of a Machine Specific Register (MSR).\r
-//\r
-// Writes Value to the Machine Specific Register specified by Index. Value is returned. No\r
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR\r
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that\r
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is\r
-// only available on IPF.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit Machine Specific Register index to write.\r
-// The 64-bit value to write to the Machine Specific Register.\r
-//\r
-// Return Value: The 64-bit value to write to the Machine Specific Register.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWriteMsr, @function\r
-.proc AsmWriteMsr\r
-.regstk 2, 0, 0, 0\r
-\r
-AsmWriteMsr::\r
-//\r
-// The follow 16 bytes stand for the bundle of \r
-// mov msr[in0] = in1\r
-// mov r8 = in1;;\r
-// since MSFT tool chain does not support mov msr[]= instruction\r
-//\r
- data1 0x0D\r
- data1 0x00\r
- data1 0x84\r
- data1 0x40\r
- data1 0x06\r
- data1 0x04\r
- data1 0x00\r
- data1 0x00\r
- data1 0x00\r
- data1 0x02\r
- data1 0x00\r
- data1 0x00\r
- data1 0x01\r
- data1 0x08\r
- data1 0x01\r
- data1 0x84\r
- srlz.d;;\r
- br.ret.sptk b0;;\r
-.endp AsmWriteMsr\r
-\r
+++ /dev/null
-/// @file\r
-/// IPF specific Performance Monitor Configuration/Data Registers accessing functions\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessPmr.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadPmc\r
-//\r
-// This routine is used to Reads the current value of Performance Monitor Configuration Register (PMC).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit PMC index.\r
-//\r
-// Return Value: The current value of PMC by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadPmc, @function\r
-.proc AsmReadPmc\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadPmc::\r
- srlz.i;;\r
- srlz.d;;\r
- mov r8 = pmc[in0];;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadPmc\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWritePmc\r
-//\r
-// This routine is used to write the current value to a Performance Monitor Configuration Register (PMC).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit PMC index.\r
-// The value should be written to PMC\r
-//\r
-// Return Value: The value written to PMC.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWritePmc, @function\r
-.proc AsmWritePmc\r
-.regstk 2, 0, 0, 0\r
-\r
-AsmWritePmc::\r
- mov pmc[in0] = in1\r
- mov r8 = in1;;\r
- srlz.i;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWritePmc\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadPmd\r
-//\r
-// This routine is used to Reads the current value of Performance Monitor Data Register (PMD).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit PMD index.\r
-//\r
-// Return Value: The current value of PMD by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadPmd, @function\r
-.proc AsmReadPmd\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadPmd::\r
- srlz.i;;\r
- srlz.d;;\r
- mov r8 = pmd[in0];;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadPmd\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWritePmd\r
-//\r
-// This routine is used to write the current value to Performance Monitor Data Register (PMD).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit PMD index.\r
-// The value should be written to PMD\r
-//\r
-// Return Value: The value written to PMD.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWritePmd, @function\r
-.proc AsmWritePmd\r
-.regstk 2, 0, 0, 0\r
-\r
-AsmWritePmd::\r
- mov pmd[in0] = in1\r
- mov r8 = in1;;\r
- srlz.i;;\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWritePmd\r
+++ /dev/null
-/// @file\r
-/// IPF specific Processor Status Register accessing functions\r
-///\r
-/// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AccessPsr.s\r
-///\r
-///\r
-\r
-#define CpuModeMask 0x0000001008020000\r
-\r
-#define CpuInVirtualMode 0x1\r
-#define CpuInPhysicalMode 0x0\r
-#define CpuInMixMode (0x0 - 0x1)\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadPsr\r
-//\r
-// This routine is used to read the current value of Processor Status Register (PSR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry :\r
-//\r
-// Return Value: The current PSR value.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadPsr, @function\r
-.proc AsmReadPsr\r
-\r
-AsmReadPsr::\r
- mov r8 = psr;;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadPsr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmWritePsr\r
-//\r
-// This routine is used to write the value of Processor Status Register (PSR).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The value need to be written.\r
-//\r
-// Return Value: The value have been written.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmWritePsr, @function\r
-.proc AsmWritePsr\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmWritePsr::\r
- mov psr.l = in0\r
- mov r8 = in0;;\r
- srlz.d;;\r
- srlz.i;;\r
- br.ret.dpnt b0;;\r
-.endp AsmWritePsr\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmCpuVirtual\r
-//\r
-// This routine is used to determines if the CPU is currently executing\r
-// in virtual, physical, or mixed mode.\r
-//\r
-// If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.\r
-// If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.\r
-// If the CPU is not in physical mode or virtual mode, then it is in mixed mode,\r
-// and -1 is returned.\r
-//\r
-// Arguments:\r
-//\r
-// On Entry: None\r
-//\r
-// Return Value: The CPU mode flag\r
-// return 1 The CPU is in virtual mode.\r
-// return 0 The CPU is in physical mode.\r
-// return -1 The CPU is in mixed mode.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmCpuVirtual, @function\r
-.proc AsmCpuVirtual\r
-\r
-AsmCpuVirtual::\r
- mov r29 = psr\r
- movl r30 = CpuModeMask;;\r
- and r28 = r30, r29;;\r
- cmp.eq p6, p7 = r30, r28;;\r
-(p6) mov r8 = CpuInVirtualMode;;\r
-(p6) br.ret.dpnt b0;;\r
-(p7) cmp.eq p6, p7 = 0x0, r28;;\r
-(p6) mov r8 = CpuInPhysicalMode;;\r
-(p7) mov r8 = CpuInMixMode;;\r
- br.ret.dpnt b0;;\r
-.endp AsmCpuVirtual\r
+++ /dev/null
-/** @file\r
-\r
- This module contains generic macros for an assembly writer.\r
-\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php.\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-**/\r
-\r
-#ifndef _ASM_H_\r
-#define _ASM_H_\r
-\r
-#define TRUE 1\r
-#define FALSE 0\r
-#define PROCEDURE_ENTRY(name) .##text; \\r
- .##type name, @function; \\r
- .##proc name; \\r
- name::\r
-\r
-#define PROCEDURE_EXIT(name) .##endp name\r
-\r
-#endif // _ASM_H\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of CallPalProcStacked on Itanium-based\r
-/// architecture.\r
-///\r
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AsmCpuMisc.s\r
-///\r
-///\r
-\r
-\r
-.text\r
-.proc CpuBreakpoint\r
-.type CpuBreakpoint, @function\r
-\r
-CpuBreakpoint::\r
- break.i 0;;\r
- br.ret.dpnt b0;;\r
-\r
-.endp CpuBreakpoint\r
-\r
-.proc MemoryFence\r
-.type MemoryFence, @function\r
-\r
-MemoryFence::\r
- mf;; // memory access ordering\r
-\r
- // do we need the mf.a also here?\r
- mf.a // wait for any IO to complete?\r
- \r
- // not sure if we need serialization here, just put it, in case...\r
- \r
- srlz.d;;\r
- srlz.i;;\r
- \r
- br.ret.dpnt b0;;\r
-.endp MemoryFence\r
-\r
-.proc DisableInterrupts\r
-.type DisableInterrupts, @function\r
-\r
-DisableInterrupts::\r
- rsm 0x4000\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-\r
-.endp DisableInterrupts\r
-\r
-.proc EnableInterrupts\r
-.type EnableInterrupts, @function\r
-\r
-EnableInterrupts::\r
- ssm 0x4000\r
- srlz.d;;\r
- br.ret.dpnt b0;;\r
-\r
-.endp EnableInterrupts\r
-\r
-.proc EnableDisableInterrupts\r
-.type EnableDisableInterrupts, @function\r
-\r
-EnableDisableInterrupts::\r
- ssm 0x4000\r
- srlz.d;;\r
- srlz.i;;\r
- rsm 0x4000\r
- srlz.d;;\r
-\r
- br.ret.dpnt b0;;\r
-\r
-.endp EnableDisableInterrupts\r
-\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of CallPalProcStacked on Itanium-based\r
-/// architecture.\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: AsmPalCall.s\r
-///\r
-///\r
-\r
-\r
-//-----------------------------------------------------------------------------\r
-//++\r
-// AsmPalCall\r
-//\r
-// Makes a PAL procedure call.\r
-// This is function to make a PAL procedure call. Based on the Index\r
-// value this API will make static or stacked PAL call. The following table\r
-// describes the usage of PAL Procedure Index Assignment. Architected procedures\r
-// may be designated as required or optional. If a PAL procedure is specified\r
-// as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the\r
-// Status field of the PAL_CALL_RETURN structure.\r
-// This indicates that the procedure is not present in this PAL implementation.\r
-// It is the caller's responsibility to check for this return code after calling\r
-// any optional PAL procedure.\r
-// No parameter checking is performed on the 5 input parameters, but there are\r
-// some common rules that the caller should follow when making a PAL call. Any\r
-// address passed to PAL as buffers for return parameters must be 8-byte aligned.\r
-// Unaligned addresses may cause undefined results. For those parameters defined\r
-// as reserved or some fields defined as reserved must be zero filled or the invalid\r
-// argument return value may be returned or undefined result may occur during the\r
-// execution of the procedure. If the PalEntryPoint does not point to a valid\r
-// PAL entry point then the system behavior is undefined. This function is only\r
-// available on IPF.\r
-//\r
-// On Entry :\r
-// in0: PAL_PROC entrypoint\r
-// in1-in4 : PAL_PROC arguments\r
-//\r
-// Return Value:\r
-//\r
-// As per stacked calling conventions.\r
-//\r
-//--\r
-//---------------------------------------------------------------------------\r
-\r
-//\r
-// PAL function calls\r
-//\r
-#define PAL_MC_CLEAR_LOG 0x0015\r
-#define PAL_MC_DYNAMIC_STATE 0x0018\r
-#define PAL_MC_ERROR_INFO 0x0019\r
-#define PAL_MC_RESUME 0x001a\r
-\r
-\r
-.text\r
-.proc AsmPalCall\r
-.type AsmPalCall, @function\r
-\r
-AsmPalCall::\r
- alloc loc1 = ar.pfs,5,8,4,0\r
- mov loc0 = b0\r
- mov loc3 = b5\r
- mov loc4 = r2\r
- mov loc7 = r1\r
- mov r2 = psr;;\r
- mov r28 = in1\r
- mov loc5 = r2;;\r
-\r
- movl loc6 = 0x100;;\r
- cmp.ge p6,p7 = r28,loc6;;\r
-\r
-(p6) movl loc6 = 0x1FF;;\r
-(p7) br.dpnt.few PalCallStatic;; // 0 ~ 255 make a static Pal Call\r
-(p6) cmp.le p6,p7 = r28,loc6;;\r
-(p6) br.dpnt.few PalCallStacked;; // 256 ~ 511 make a stacked Pal Call\r
-(p7) movl loc6 = 0x300;;\r
-(p7) cmp.ge p6,p7 = r28,loc6;;\r
-(p7) br.dpnt.few PalCallStatic;; // 512 ~ 767 make a static Pal Call\r
-(p6) movl loc6 = 0x3FF;;\r
-(p6) cmp.le p6,p7 = r28,loc6;;\r
-(p6) br.dpnt.few PalCallStacked;; // 768 ~ 1023 make a stacked Pal Call\r
-\r
-(p7) mov r8 = 0xFFFFFFFFFFFFFFFF;; // > 1024 return invalid\r
-(p7) br.dpnt.few ComeBackFromPALCall;;\r
-\r
-PalCallStatic:\r
- movl loc6 = PAL_MC_CLEAR_LOG;;\r
- cmp.eq p6,p7 = r28,loc6;;\r
-\r
-(p7) movl loc6 = PAL_MC_DYNAMIC_STATE;;\r
-(p7) cmp.eq p6,p7 = r28,loc6;;\r
-\r
-(p7) movl loc6 = PAL_MC_ERROR_INFO;;\r
-(p7) cmp.eq p6,p7 = r28,loc6;;\r
-\r
-(p7) movl loc6 = PAL_MC_RESUME;;\r
-(p7) cmp.eq p6,p7 = r28,loc6 ;;\r
-\r
- mov loc6 = 0x1;;\r
-(p7) dep r2 = loc6,r2,13,1;; // psr.ic = 1\r
-\r
-// p6 will be true, if it is one of the MCHK calls. There has been lots of debate\r
-// on psr.ic for these values. For now, do not do any thing to psr.ic\r
-\r
- dep r2 = r0,r2,14,1;; // psr.i = 0\r
-\r
- mov psr.l = r2\r
- srlz.d // Needs data serailization.\r
- srlz.i // Needs instruction serailization.\r
-\r
-StaticGetPALLocalIP:\r
- mov loc2 = ip;;\r
- add loc2 = ComeBackFromPALCall - StaticGetPALLocalIP,loc2;;\r
- mov b0 = loc2 // return address after Pal call\r
-\r
- mov r29 = in2\r
- mov r30 = in3\r
- mov r31 = in4\r
- mov b5 = in0;; // get the PalProcEntrypt from input\r
- br.sptk b5;; // Take the plunge.\r
-\r
-PalCallStacked:\r
- dep r2 = r0,r2,14,1;; // psr.i = 0\r
- mov psr.l = r2;;\r
- srlz.d // Needs data serailization.\r
- srlz.i // Needs instruction serailization.\r
-\r
-StackedGetPALLocalIP:\r
- mov out0 = in1\r
- mov out1 = in2\r
- mov out2 = in3\r
- mov out3 = in4\r
- mov b5 = in0 ;; // get the PalProcEntrypt from input\r
- br.call.dpnt b0 = b5 ;; // Take the plunge.\r
-\r
-ComeBackFromPALCall:\r
- mov psr.l = loc5 ;;\r
- srlz.d // Needs data serailization.\r
- srlz.i // Needs instruction serailization.\r
-\r
- mov b5 = loc3\r
- mov r2 = loc4\r
- mov r1 = loc7\r
-\r
- mov b0 = loc0\r
- mov ar.pfs = loc1;;\r
- br.ret.dpnt b0;;\r
-\r
-.endp AsmPalCall\r
-\r
+++ /dev/null
-/** @file\r
- Base Library CPU functions for Itanium\r
-\r
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-\r
-#include "BaseLibInternals.h"\r
-\r
-/**\r
- Generates a breakpoint on the CPU.\r
-\r
- Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
- that code can resume normal execution after the breakpoint.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-CpuBreakpoint (\r
- VOID\r
- )\r
-{\r
- __break (0);\r
-}\r
-\r
-/**\r
- Used to serialize load and store operations.\r
-\r
- All loads and stores that proceed calls to this function are guaranteed to be\r
- globally visible when this function returns.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-MemoryFence (\r
- VOID\r
- )\r
-{\r
- __mfa ();\r
-}\r
-\r
-/**\r
- Disables CPU interrupts.\r
-\r
- Disables CPU interrupts.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-DisableInterrupts (\r
- VOID\r
- )\r
-{\r
- _disable ();\r
-}\r
-\r
-/**\r
- Enables CPU interrupts.\r
-\r
- Enables CPU interrupts.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-EnableInterrupts (\r
- VOID\r
- )\r
-{\r
- _enable ();\r
-}\r
-\r
-/**\r
- Enables CPU interrupts for the smallest window required to capture any\r
- pending interrupts.\r
-\r
- Enables CPU interrupts for the smallest window required to capture any\r
- pending interrupts.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-EnableDisableInterrupts (\r
- VOID\r
- )\r
-{\r
- EnableInterrupts ();\r
- DisableInterrupts ();\r
-}\r
+++ /dev/null
-/** @file\r
- Base Library CPU functions for Itanium\r
-\r
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-\r
-#include "BaseLibInternals.h"\r
-\r
-#pragma intrinsic (_enable)\r
-#pragma intrinsic (_disable)\r
-#pragma intrinsic (__break)\r
-#pragma intrinsic (__mfa)\r
-\r
-/**\r
- Generates a breakpoint on the CPU.\r
-\r
- Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
- that code can resume normal execution after the breakpoint.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-CpuBreakpoint (\r
- VOID\r
- )\r
-{\r
- __break (0);\r
-}\r
-\r
-/**\r
- Used to serialize load and store operations.\r
-\r
- All loads and stores that proceed calls to this function are guaranteed to be\r
- globally visible when this function returns.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-MemoryFence (\r
- VOID\r
- )\r
-{\r
- __mfa ();\r
-}\r
-\r
-/**\r
- Disables CPU interrupts.\r
-\r
- Disables CPU interrupts.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-DisableInterrupts (\r
- VOID\r
- )\r
-{\r
- _disable ();\r
-}\r
-\r
-/**\r
- Enables CPU interrupts.\r
-\r
- Enables CPU interrupts.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-EnableInterrupts (\r
- VOID\r
- )\r
-{\r
- _enable ();\r
-}\r
-\r
-/**\r
- Enables CPU interrupts for the smallest window required to capture any\r
- pending interrupts.\r
-\r
- Enables CPU interrupts for the smallest window required to capture any\r
- pending interrupts.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-EnableDisableInterrupts (\r
- VOID\r
- )\r
-{\r
- EnableInterrupts ();\r
- DisableInterrupts ();\r
-}\r
-\r
+++ /dev/null
-/// @file\r
-/// CpuPause() function for Itanium-based architecture.\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: CpuPause.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc CpuPause\r
-.type CpuPause, @function\r
-CpuPause::\r
- hint.i @pause\r
- br.ret.sptk.many b0\r
-.endp\r
+++ /dev/null
-/// @file\r
-/// IPF specific AsmFc() and AsmFci () functions\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: ExecFc.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmFc\r
-//\r
-// This routine is used to execute a FC instruction on the specific address.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The specific address need to execute FC instruction.\r
-//\r
-// Return Value: The specific address have been execute FC instruction.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmFc, @function\r
-.proc AsmFc\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmFc::\r
- fc in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmFc\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmFci\r
-//\r
-// This routine is used to execute a FC.i instruction on the specific address.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The specific address need to execute FC.i instruction.\r
-//\r
-// Return Value: The specific address have been execute FC.i instruction.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmFci, @function\r
-.proc AsmFci\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmFci::\r
- fc.i in0\r
- mov r8 = in0;;\r
- br.ret.dpnt b0;;\r
-.endp AsmFci\r
+++ /dev/null
-/** @file\r
- AsmFlushCacheRange() function for IPF.\r
-\r
- Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-\r
-#include "BaseLibInternals.h"\r
-\r
-/**\r
- Flush a range of cache lines in the cache coherency domain of the calling\r
- CPU.\r
-\r
- Flushes the cache lines specified by Address and Length. If Address is not aligned\r
- on a cache line boundary, then entire cache line containing Address is flushed.\r
- If Address + Length is not aligned on a cache line boundary, then the entire cache\r
- line containing Address + Length - 1 is flushed. This function may choose to flush\r
- the entire cache if that is more efficient than flushing the specified range. If\r
- Length is 0, the no cache lines are flushed. Address is returned.\r
- This function is only available on IPF.\r
-\r
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
-\r
- @param Address The base address of the instruction lines to invalidate. If\r
- the CPU is in a physical addressing mode, then Address is a\r
- physical address. If the CPU is in a virtual addressing mode,\r
- then Address is a virtual address.\r
-\r
- @param Length The number of bytes to invalidate from the instruction cache.\r
-\r
- @return Address.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-AsmFlushCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
- )\r
-{\r
- ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
- return InternalFlushCacheRange (Address, Length);\r
-}\r
+++ /dev/null
-/// @file\r
-/// Retrieve of the interrupt state of the running processor for the Itanium\r
-/// architecture.\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: GetInterruptState.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc GetInterruptState\r
-.type GetInterruptState, @function\r
-GetInterruptState::\r
- mov r8 = psr\r
- extr.u r8 = r8, 14, 1\r
- br.ret.sptk.many b0\r
-.endp GetInterruptState\r
+++ /dev/null
-/** @file\r
-\r
- Register Definition for IPF.\r
-\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php.\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-#ifndef _IA64GEN_H_\r
-#define _IA64GEN_H_\r
-\r
-#define TT_UNAT 0\r
-#define C_PSR 0\r
-#define J_UNAT 0\r
-#define T_TYPE 0\r
-#define T_IPSR 0x8\r
-#define T_ISR 0x10\r
-#define T_IIP 0x18\r
-#define T_IFA 0x20\r
-#define T_IIPA 0x28\r
-#define T_IFS 0x30\r
-#define T_IIM 0x38\r
-#define T_RSC 0x40\r
-#define T_BSP 0x48\r
-#define T_BSPSTORE 0x50\r
-#define T_RNAT 0x58\r
-#define T_PFS 0x60\r
-#define T_KBSPSTORE 0x68\r
-#define T_UNAT 0x70\r
-#define T_CCV 0x78\r
-#define T_DCR 0x80\r
-#define T_PREDS 0x88\r
-#define T_NATS 0x90\r
-#define T_R1 0x98\r
-#define T_GP 0x98\r
-#define T_R2 0xa0\r
-#define T_R3 0xa8\r
-#define T_R4 0xb0\r
-#define T_R5 0xb8\r
-#define T_R6 0xc0\r
-#define T_R7 0xc8\r
-#define T_R8 0xd0\r
-#define T_R9 0xd8\r
-#define T_R10 0xe0\r
-#define T_R11 0xe8\r
-#define T_R12 0xf0\r
-#define T_SP 0xf0\r
-#define T_R13 0xf8\r
-#define T_R14 0x100\r
-#define T_R15 0x108\r
-#define T_R16 0x110\r
-#define T_R17 0x118\r
-#define T_R18 0x120\r
-#define T_R19 0x128\r
-#define T_R20 0x130\r
-#define T_R21 0x138\r
-#define T_R22 0x140\r
-#define T_R23 0x148\r
-#define T_R24 0x150\r
-#define T_R25 0x158\r
-#define T_R26 0x160\r
-#define T_R27 0x168\r
-#define T_R28 0x170\r
-#define T_R29 0x178\r
-#define T_R30 0x180\r
-#define T_R31 0x188\r
-#define T_F2 0x1f0\r
-#define T_F3 0x200\r
-#define T_F4 0x210\r
-#define T_F5 0x220\r
-#define T_F6 0x230\r
-#define T_F7 0x240\r
-#define T_F8 0x250\r
-#define T_F9 0x260\r
-#define T_F10 0x270\r
-#define T_F11 0x280\r
-#define T_F12 0x290\r
-#define T_F13 0x2a0\r
-#define T_F14 0x2b0\r
-#define T_F15 0x2c0\r
-#define T_F16 0x2d0\r
-#define T_F17 0x2e0\r
-#define T_F18 0x2f0\r
-#define T_F19 0x300\r
-#define T_F20 0x310\r
-#define T_F21 0x320\r
-#define T_F22 0x330\r
-#define T_F23 0x340\r
-#define T_F24 0x350\r
-#define T_F25 0x360\r
-#define T_F26 0x370\r
-#define T_F27 0x380\r
-#define T_F28 0x390\r
-#define T_F29 0x3a0\r
-#define T_F30 0x3b0\r
-#define T_F31 0x3c0\r
-#define T_FPSR 0x1e0\r
-#define T_B0 0x190\r
-#define T_B1 0x198\r
-#define T_B2 0x1a0\r
-#define T_B3 0x1a8\r
-#define T_B4 0x1b0\r
-#define T_B5 0x1b8\r
-#define T_B6 0x1c0\r
-#define T_B7 0x1c8\r
-#define T_EC 0x1d0\r
-#define T_LC 0x1d8\r
-#define J_NATS 0x8\r
-#define J_PFS 0x10\r
-#define J_BSP 0x18\r
-#define J_RNAT 0x20\r
-#define J_PREDS 0x28\r
-#define J_LC 0x30\r
-#define J_R4 0x38\r
-#define J_R5 0x40\r
-#define J_R6 0x48\r
-#define J_R7 0x50\r
-#define J_SP 0x58\r
-#define J_F2 0x60\r
-#define J_F3 0x70\r
-#define J_F4 0x80\r
-#define J_F5 0x90\r
-#define J_F16 0xa0\r
-#define J_F17 0xb0\r
-#define J_F18 0xc0\r
-#define J_F19 0xd0\r
-#define J_F20 0xe0\r
-#define J_F21 0xf0\r
-#define J_F22 0x100\r
-#define J_F23 0x110\r
-#define J_F24 0x120\r
-#define J_F25 0x130\r
-#define J_F26 0x140\r
-#define J_F27 0x150\r
-#define J_F28 0x160\r
-#define J_F29 0x170\r
-#define J_F30 0x180\r
-#define J_F31 0x190\r
-#define J_FPSR 0x1a0\r
-#define J_B0 0x1a8\r
-#define J_B1 0x1b0\r
-#define J_B2 0x1b8\r
-#define J_B3 0x1c0\r
-#define J_B4 0x1c8\r
-#define J_B5 0x1d0\r
-#define TRAP_FRAME_LENGTH 0x3d0\r
-#define C_UNAT 0x28\r
-#define C_NATS 0x30\r
-#define C_PFS 0x8\r
-#define C_BSPSTORE 0x10\r
-#define C_RNAT 0x18\r
-#define C_RSC 0x20\r
-#define C_PREDS 0x38\r
-#define C_LC 0x40\r
-#define C_DCR 0x48\r
-#define C_R1 0x50\r
-#define C_GP 0x50\r
-#define C_R4 0x58\r
-#define C_R5 0x60\r
-#define C_R6 0x68\r
-#define C_R7 0x70\r
-#define C_SP 0x78\r
-#define C_R13 0x80\r
-#define C_F2 0x90\r
-#define C_F3 0xa0\r
-#define C_F4 0xb0\r
-#define C_F5 0xc0\r
-#define C_F16 0xd0\r
-#define C_F17 0xe0\r
-#define C_F18 0xf0\r
-#define C_F19 0x100\r
-#define C_F20 0x110\r
-#define C_F21 0x120\r
-#define C_F22 0x130\r
-#define C_F23 0x140\r
-#define C_F24 0x150\r
-#define C_F25 0x160\r
-#define C_F26 0x170\r
-#define C_F27 0x180\r
-#define C_F28 0x190\r
-#define C_F29 0x1a0\r
-#define C_F30 0x1b0\r
-#define C_F31 0x1c0\r
-#define C_FPSR 0x1d0\r
-#define C_B0 0x1d8\r
-#define C_B1 0x1e0\r
-#define C_B2 0x1e8\r
-#define C_B3 0x1f0\r
-#define C_B4 0x1f8\r
-#define C_B5 0x200\r
-#define TT_R2 0x8\r
-#define TT_R3 0x10\r
-#define TT_R8 0x18\r
-#define TT_R9 0x20\r
-#define TT_R10 0x28\r
-#define TT_R11 0x30\r
-#define TT_R14 0x38\r
-\r
-#endif _IA64GEN_H\r
+++ /dev/null
-//++\r
-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
-// This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php. \r
-// \r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-// \r
-// Module Name:\r
-// InternalFlushCacheRange.s \r
-//\r
-// Abstract:\r
-// Assemble routine to flush cache lines \r
-//\r
-// Revision History:\r
-//\r
-//--\r
-.file "IpfCpuCache.s"\r
-\r
-#include <IpfMacro.i>\r
-\r
-//\r
-// Internal worker function to invalidate a range of instruction cache lines\r
-// in the cache coherency domain of the calling CPU.\r
-//\r
-// Internal worker function to invalidate the instruction cache lines specified\r
-// by Address and Length. If Address is not aligned on a cache line boundary,\r
-// then entire instruction cache line containing Address is invalidated. If\r
-// Address + Length is not aligned on a cache line boundary, then the entire\r
-// instruction cache line containing Address + Length -1 is invalidated. This\r
-// function may choose to invalidate the entire instruction cache if that is more\r
-// efficient than invalidating the specified range. If Length is 0, the no instruction\r
-// cache lines are invalidated. Address is returned.\r
-// This function is only available on IPF.\r
-//\r
-// @param Address The base address of the instruction cache lines to\r
-// invalidate. If the CPU is in a physical addressing mode, then\r
-// Address is a physical address. If the CPU is in a virtual\r
-// addressing mode, then Address is a virtual address.\r
-//\r
-// @param Length The number of bytes to invalidate from the instruction cache.\r
-//\r
-// @return Address\r
-// \r
-// VOID *\r
-// EFIAPI\r
-// InternalFlushCacheRange (\r
-// IN VOID *Address,\r
-// IN UINTN Length\r
-// );\r
-//\r
-PROCEDURE_ENTRY (InternalFlushCacheRange)\r
-\r
- NESTED_SETUP (5,8,0,0)\r
- \r
- mov loc2 = ar.lc\r
- \r
- mov loc3 = in0 // Start address.\r
- mov loc4 = in1;; // Length in bytes.\r
- \r
- cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache\r
- (p6) br.spnt.many DoneFlushingC;; \r
- \r
- add loc4 = loc4,loc3 \r
- mov loc5 = 1;;\r
- sub loc4 = loc4, loc5 ;; // the End address to flush\r
- \r
- dep loc3 = r0,loc3,0,5 \r
- dep loc4 = r0,loc4,0,5;; \r
- shr loc3 = loc3,5 \r
- shr loc4 = loc4,5;; // 32 byte cache line\r
- \r
- sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but \r
- // the br.cloop will first execute one time \r
- mov loc3 = in0 \r
- mov loc5 = 32 \r
- mov ar.lc = loc4;;\r
-\r
-StillFlushingC:\r
- fc loc3;; \r
- sync.i;;\r
- srlz.i;;\r
- add loc3 = loc5,loc3;;\r
- br.cloop.sptk.few StillFlushingC;;\r
-\r
-DoneFlushingC: \r
- mov ar.lc = loc2 \r
- mov r8 = in0 // return *Address\r
- NESTED_RETURN\r
-\r
-PROCEDURE_EXIT (InternalFlushCacheRange)\r
-\r
+++ /dev/null
-/** @file\r
- SwitchStack() function for IPF.\r
-\r
- Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "BaseLibInternals.h"\r
-\r
-/**\r
- Transfers control to a function starting with a new stack.\r
-\r
- Transfers control to the function specified by EntryPoint using the\r
- new stack specified by NewStack and passing in the parameters specified\r
- by Context1 and Context2. Context1 and Context2 are optional and may\r
- be NULL. The function EntryPoint must never return.\r
- Marker will be ignored on IA-32, x64, and EBC.\r
- IPF CPUs expect one additional parameter of type VOID * that specifies\r
- the new backing store pointer.\r
-\r
- If EntryPoint is NULL, then ASSERT().\r
- If NewStack is NULL, then ASSERT().\r
-\r
- @param EntryPoint A pointer to function to call with the new stack.\r
- @param Context1 A pointer to the context to pass into the EntryPoint\r
- function.\r
- @param Context2 A pointer to the context to pass into the EntryPoint\r
- function.\r
- @param NewStack A pointer to the new stack to use for the EntryPoint\r
- function.\r
- @param Marker VA_LIST marker for the variable argument list.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-InternalSwitchStack (\r
- IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
- IN VOID *Context1, OPTIONAL\r
- IN VOID *Context2, OPTIONAL\r
- IN VOID *NewStack,\r
- IN VA_LIST Marker\r
- )\r
-{\r
- VOID *NewBsp;\r
-\r
- //\r
- // Get new backing store pointer from variable list\r
- //\r
- NewBsp = VA_ARG (Marker, VOID *);\r
-\r
- //\r
- // New backing store pointer should be aligned with CPU_STACK_ALIGNMENT\r
- //\r
- ASSERT (((UINTN)NewBsp & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
-\r
- AsmSwitchStackAndBackingStore (EntryPoint, Context1, Context2, NewStack, NewBsp);\r
-}\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of longjmp for the Itanium-based architecture.\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: longjmp.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc InternalLongJump\r
-.type InternalLongJump, @function\r
-.regstk 2, 0, 0, 0\r
-InternalLongJump::\r
- add r10 = 0x10*20 + 8*14, in0\r
- movl r2 = ~((((1 << 14) - 1) << 16) | 3)\r
-\r
- ld8.nt1 r14 = [r10], -8*2 // BSP, skip PFS\r
- mov r15 = ar.bspstore // BSPSTORE\r
-\r
- ld8.nt1 r17 = [r10], -8 // UNAT after spill\r
- mov r16 = ar.rsc // RSC\r
- cmp.leu p6 = r14, r15\r
-\r
- ld8.nt1 r18 = [r10], -8 // UNAT\r
- ld8.nt1 r25 = [r10], -8 // b5\r
- and r2 = r16, r2\r
-\r
- ldf.fill.nt1 f2 = [in0], 0x10\r
- ld8.nt1 r24 = [r10], -8 // b4\r
- mov b5 = r25\r
-\r
- mov ar.rsc = r2\r
- ld8.nt1 r23 = [r10], -8 // b3\r
- mov b4 = r24\r
-\r
- ldf.fill.nt1 f3 = [in0], 0x10\r
- mov ar.unat = r17\r
-(p6) br.spnt.many _skip_flushrs\r
-\r
- flushrs\r
- mov r15 = ar.bsp // New BSPSTORE\r
-\r
-_skip_flushrs:\r
- mov r31 = ar.rnat // RNAT\r
- loadrs\r
-\r
- ldf.fill.nt1 f4 = [in0], 0x10\r
- ld8.nt1 r22 = [r10], -8\r
- dep r2 = -1, r14, 3, 6\r
-\r
- ldf.fill.nt1 f5 = [in0], 0x10\r
- ld8.nt1 r21 = [r10], -8\r
- cmp.ltu p6 = r2, r15\r
-\r
- ld8.nt1 r20 = [r10], -0x10 // skip sp\r
-(p6) ld8.nta r31 = [r2]\r
- mov b3 = r23\r
-\r
- ldf.fill.nt1 f16 = [in0], 0x10\r
- ld8.fill.nt1 r7 = [r10], -8\r
- mov b2 = r22\r
-\r
- ldf.fill.nt1 f17 = [in0], 0x10\r
- ld8.fill.nt1 r6 = [r10], -8\r
- mov b1 = r21\r
-\r
- ldf.fill.nt1 f18 = [in0], 0x10\r
- ld8.fill.nt1 r5 = [r10], -8\r
- mov b0 = r20\r
-\r
- ldf.fill.nt1 f19 = [in0], 0x10\r
- ld8.fill.nt1 r4 = [r10], 8*13\r
-\r
- ldf.fill.nt1 f20 = [in0], 0x10\r
- ld8.nt1 r19 = [r10], 0x10 // PFS\r
-\r
- ldf.fill.nt1 f21 = [in0], 0x10\r
- ld8.nt1 r26 = [r10], 8 // Predicate\r
- mov ar.pfs = r19\r
-\r
- ldf.fill.nt1 f22 = [in0], 0x10\r
- ld8.nt1 r27 = [r10], 8 // LC\r
- mov pr = r26, -1\r
-\r
- ldf.fill.nt1 f23 = [in0], 0x10\r
- ld8.nt1 r28 = [r10], -17*8 - 0x10\r
- mov ar.lc = r27\r
-\r
- ldf.fill.nt1 f24 = [in0], 0x10\r
- ldf.fill.nt1 f25 = [in0], 0x10\r
- mov r8 = in1\r
-\r
- ldf.fill.nt1 f26 = [in0], 0x10\r
- ldf.fill.nt1 f31 = [r10], -0x10\r
-\r
- ldf.fill.nt1 f27 = [in0], 0x10\r
- ldf.fill.nt1 f30 = [r10], -0x10\r
-\r
- ldf.fill.nt1 f28 = [in0]\r
- ldf.fill.nt1 f29 = [r10], 0x10*3 + 8*4\r
-\r
- ld8.fill.nt1 sp = [r10]\r
- mov ar.unat = r18\r
-\r
- mov ar.bspstore = r14\r
- mov ar.rnat = r31\r
-\r
- invala\r
- mov ar.rsc = r16\r
- br.ret.sptk b0\r
-.endp\r
+++ /dev/null
-/// @file\r
-/// IPF specific application register reading functions\r
-///\r
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-///\r
-///\r
-\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadApplicationRegister\r
-//\r
-// Reads a 64-bit application register.\r
-//\r
-// Reads and returns the application register specified by Index.\r
-// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The index of the application register to read.\r
-//\r
-// Return Value: The application register specified by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadApplicationRegister, @function\r
-.proc AsmReadApplicationRegister\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadApplicationRegister::\r
- //\r
- // ARs are defined in the ranges 0-44 and 64-66 (with some holes).\r
- // Compact this list by subtracting 16 from the top range.\r
- // 0-44, 64-66 -> 0-44, 48-50\r
- //\r
- mov r15=2\r
- mov r14=pr // save predicates\r
- cmp.leu p6,p7=64,in0 // p6 = AR# >= 64\r
- ;;\r
- (p7) cmp.leu p7,p0=48,in0 // p7 = 32 <= AR# < 64\r
- (p6) add in0=-16,in0 // if (AR >= 64) AR# -= 16\r
- ;;\r
- (p7) mov r15=0 // if bad range (48-63)\r
- ;;\r
- mov ret0=-1 // in case of illegal AR #\r
- shl r15=r15,in0 // r15 = 0x2 << AR#\r
- ;;\r
- mov pr=r15,-1\r
- ;;\r
- //\r
- // At this point the predicates contain a bit field of the\r
- // AR desired. (The bit is the AR+1, since pr0 is always 1.)\r
- //\r
- .pred.rel "mutex",p1,p2,p3,p4,p5,p6,p7,p8,p17,p18,p19,p20,p22,p25,\\r
- p26,p27,p28,p29,p30,p31,p33,p37,p41,p45,p49,p50,p51\r
- (p1) mov ret0=ar.k0 // ar0\r
- (p2) mov ret0=ar.k1 // ar1\r
- (p3) mov ret0=ar.k2 // ar2\r
- (p4) mov ret0=ar.k3 // ar3\r
- (p5) mov ret0=ar.k4 // ar4\r
- (p6) mov ret0=ar.k5 // ar5\r
- (p7) mov ret0=ar.k6 // ar6\r
- (p8) mov ret0=ar.k7 // ar7\r
-\r
- (p17) mov ret0=ar.rsc // ar16\r
- (p18) mov ret0=ar.bsp // ar17\r
- (p19) mov ret0=ar.bspstore // ar18\r
- (p20) mov ret0=ar.rnat // ar19\r
-\r
- (p22) mov ret0=ar.fcr // ar21 [iA32]\r
-\r
- (p25) mov ret0=ar.eflag // ar24 [iA32]\r
- (p26) mov ret0=ar.csd // ar25 [iA32]\r
- (p27) mov ret0=ar.ssd // ar26 [iA32]\r
- (p28) mov ret0=ar.cflg // ar27 [iA32]\r
- (p29) mov ret0=ar.fsr // ar28 [iA32]\r
- (p30) mov ret0=ar.fir // ar29 [iA32]\r
- (p31) mov ret0=ar.fdr // ar30 [iA32]\r
-\r
- (p33) mov ret0=ar.ccv // ar32\r
-\r
- (p37) mov ret0=ar.unat // ar36\r
-\r
- (p41) mov ret0=ar.fpsr // ar40\r
-\r
- (p45) mov ret0=ar.itc // ar44\r
-\r
- //\r
- // This is the translated (-16) range.\r
- //\r
- (p49) mov ret0=ar.pfs // ar64\r
- (p50) mov ret0=ar.lc // ar65\r
- (p51) mov ret0=ar.ec // ar66\r
-\r
- // Restore predicates and return.\r
-\r
- mov pr=r14,-1\r
- br.ret.sptk b0\r
- .endp\r
+++ /dev/null
-/// @file\r
-/// IPF specific AsmReadCpuid()function\r
-///\r
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: ReadCpuid.s\r
-///\r
-///\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadCpuid\r
-//\r
-// This routine is used to Reads the current value of Processor Identifier Register (CPUID).\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The 8-bit Processor Identifier Register index to read.\r
-//\r
-// Return Value: The current value of Processor Identifier Register specified by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadCpuid, @function\r
-.proc AsmReadCpuid\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadCpuid::\r
- mov r8 = cpuid[in0];;\r
- br.ret.dpnt b0;;\r
-.endp AsmReadCpuid\r
-\r
+++ /dev/null
-/// @file\r
-/// IPF specific control register reading functions\r
-///\r
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-///\r
-///\r
-\r
-\r
-\r
-//---------------------------------------------------------------------------------\r
-//++\r
-// AsmReadControlRegister\r
-//\r
-// Reads a 64-bit control register.\r
-//\r
-// Reads and returns the control register specified by Index.\r
-// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.\r
-//\r
-// Arguments :\r
-//\r
-// On Entry : The index of the control register to read.\r
-//\r
-// Return Value: The control register specified by Index.\r
-//\r
-//--\r
-//----------------------------------------------------------------------------------\r
-.text\r
-.type AsmReadControlRegister, @function\r
-.proc AsmReadControlRegister\r
-.regstk 1, 0, 0, 0\r
-\r
-AsmReadControlRegister::\r
- //\r
- // CRs are defined in the ranges 0-25 and 64-81 (with some holes).\r
- // Compact this list by subtracting 32 from the top range.\r
- // 0-25, 64-81 -> 0-25, 32-49\r
- //\r
- mov r15=2\r
- mov r14=pr // save predicates\r
- cmp.leu p6,p7=64,in0 // p6 = CR# >= 64\r
- ;;\r
- (p7) cmp.leu p7,p0=32,in0 // p7 = 32 <= CR# < 64\r
- (p6) add in0=-32,in0 // if (CR >= 64) CR# -= 32\r
- ;;\r
- (p7) mov r15=0 // if bad range (32-63)\r
- ;;\r
- mov ret0=-1 // in case of illegal CR #\r
- shl r15=r15,in0 // r15 = 0x2 << CR#\r
- ;;\r
- mov pr=r15,-1\r
- ;;\r
-\r
- //\r
- // At this point the predicates contain a bit field of the\r
- // CR desired. (The bit is the CR+1, since pr0 is always 1.)\r
- //\r
- .pred.rel "mutex",p1,p2,p3,p9,p17,p18,p20,p21,p22,p23,p24,p25,p26,\\r
- p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p49,p50\r
- (p1) mov ret0=cr.dcr // cr0\r
- (p2) mov ret0=cr.itm // cr1\r
- (p3) mov ret0=cr.iva // cr2\r
- (p9) mov ret0=cr.pta // cr8\r
- (p17) mov ret0=cr.ipsr // cr16\r
- (p18) mov ret0=cr.isr // cr17\r
- (p20) mov ret0=cr.iip // cr19\r
- (p21) mov ret0=cr.ifa // cr20\r
- (p22) mov ret0=cr.itir // cr21\r
- (p23) mov ret0=cr.iipa // cr22\r
- (p24) mov ret0=cr.ifs // cr23\r
- (p25) mov ret0=cr.iim // cr24\r
- (p26) mov ret0=cr.iha // cr25\r
-\r
- // This is the translated (-32) range.\r
-\r
- (p33) mov ret0=cr.lid // cr64\r
- (p34) mov ret0=cr.ivr // cr65\r
- (p35) mov ret0=cr.tpr // cr66\r
- (p36) mov ret0=cr.eoi // cr67\r
- (p37) mov ret0=cr.irr0 // cr68\r
- (p38) mov ret0=cr.irr1 // cr69\r
- (p39) mov ret0=cr.irr2 // cr70\r
- (p40) mov ret0=cr.irr3 // cr71\r
- (p41) mov ret0=cr.itv // cr72\r
- (p42) mov ret0=cr.pmv // cr73\r
- (p43) mov ret0=cr.cmcv // cr74\r
- (p49) mov ret0=cr.lrr0 // cr80\r
- (p50) mov ret0=cr.lrr1 // cr81\r
- \r
- //\r
- // Restore predicates and return.\r
- //\r
- mov pr=r14,-1\r
- br.ret.sptk b0\r
- .endp\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of longjmp for the Itanium-based architecture.\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: longjmp.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-ASM_GLOBAL InternalAssertJumpBuffer\r
-.type InternalAssertJumpBuffer, @function\r
-\r
-.proc SetJump\r
-.type SetJump, @function\r
-SetJump::\r
- alloc loc0 = ar.pfs, 1, 2, 1, 0\r
- mov loc1 = b0\r
- mov out0 = in0\r
-\r
- brl.call.sptk.many b0 = InternalAssertJumpBuffer\r
-\r
- mov r14 = ar.unat\r
- mov r15 = ar.bsp\r
- add r10 = 0x10*20, in0\r
-\r
- stf.spill.nta [in0] = f2, 0x10\r
- st8.spill.nta [r10] = r4, 8\r
- mov r21 = b1\r
-\r
- stf.spill.nta [in0] = f3, 0x10\r
- st8.spill.nta [r10] = r5, 8\r
- mov r22 = b2\r
-\r
- stf.spill.nta [in0] = f4, 0x10\r
- st8.spill.nta [r10] = r6, 8\r
- mov r23 = b3\r
-\r
- stf.spill.nta [in0] = f5, 0x10\r
- st8.spill.nta [r10] = r7, 8\r
- mov r24 = b4\r
-\r
- stf.spill.nta [in0] = f16, 0x10\r
- st8.spill.nta [r10] = sp, 8\r
- mov r25 = b5\r
-\r
- stf.spill.nta [in0] = f17, 0x10\r
- st8.nta [r10] = loc1, 8\r
- mov r16 = pr\r
-\r
- stf.spill.nta [in0] = f18, 0x10\r
- st8.nta [r10] = r21, 8\r
- mov r17 = ar.lc\r
-\r
- stf.spill.nta [in0] = f19, 0x10\r
- st8.nta [r10] = r22, 8\r
-\r
- stf.spill.nta [in0] = f20, 0x10\r
- st8.nta [r10] = r23, 8\r
-\r
- stf.spill.nta [in0] = f21, 0x10\r
- st8.nta [r10] = r24, 8\r
-\r
- stf.spill.nta [in0] = f22, 0x10\r
- st8.nta [r10] = r25, 8\r
-\r
- stf.spill.nta [in0] = f23, 0x10\r
- mov r18 = ar.unat\r
-\r
- stf.spill.nta [in0] = f24, 0x10\r
- st8.nta [r10] = r14, 8 // UNAT\r
-\r
- stf.spill.nta [in0] = f25, 0x10\r
- st8.nta [r10] = r18, 8 // UNAT after spill\r
-\r
- stf.spill.nta [in0] = f26, 0x10\r
- st8.nta [r10] = loc0, 8 // PFS\r
-\r
- stf.spill.nta [in0] = f27, 0x10\r
- st8.nta [r10] = r15, 8 // BSP\r
- mov r8 = 0\r
-\r
- stf.spill.nta [in0] = f28, 0x10\r
- mov r19 = ar.fpsr\r
-\r
- stf.spill.nta [in0] = f29, 0x10\r
- st8.nta [r10] = r16, 8 // PR\r
- mov ar.pfs = loc0\r
-\r
- stf.spill.nta [in0] = f30, 0x10\r
- st8.nta [r10] = r17, 8 // LC\r
- mov b0 = loc1\r
-\r
- stf.spill.nta [in0] = f31, 0x10\r
- st8.nta [r10] = r19 // FPSR\r
-\r
- mov ar.unat = r14\r
- br.ret.sptk b0\r
-.endp SetJump\r
+++ /dev/null
-/// @file\r
-/// IPF specific SwitchStack() function\r
-///\r
-/// Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: SwitchStack.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc AsmSwitchStackAndBackingStore\r
-.type AsmSwitchStackAndBackingStore, @function\r
-.regstk 5, 0, 0, 0\r
-AsmSwitchStackAndBackingStore::\r
- mov r14 = ar.rsc\r
- movl r2 = ~((((1 << 14) - 1) << 16) | 3)\r
-\r
- mov r17 = in1\r
- mov r18 = in2\r
- and r2 = r14, r2\r
- \r
- flushrs\r
- \r
- mov ar.rsc = r2\r
- mov sp = in3\r
- mov r19 = in4\r
-\r
- ld8.nt1 r16 = [in0], 8\r
- ld8.nta gp = [in0]\r
- mov r3 = -1\r
-\r
- loadrs\r
- mov ar.bspstore = r19\r
- mov b7 = r16\r
-\r
- alloc r2 = ar.pfs, 0, 0, 2, 0\r
- mov out0 = r17\r
- mov out1 = r18\r
-\r
- mov ar.rnat = r3\r
- mov ar.rsc = r14\r
- br.call.sptk.many b0 = b7\r
-.endp AsmSwitchStackAndBackingStore\r
+++ /dev/null
-/** @file\r
- Unaligned access functions of BaseLib for IPF.\r
-\r
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "BaseLibInternals.h"\r
-\r
-/**\r
- Reads a 16-bit value from memory that may be unaligned.\r
-\r
- This function returns the 16-bit value pointed to by Buffer. The function\r
- guarantees that the read operation does not produce an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 16-bit value that may be unaligned.\r
-\r
- @return The 16-bit value read from Buffer.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-ReadUnaligned16 (\r
- IN CONST UINT16 *Buffer\r
- )\r
-{\r
- ASSERT (Buffer != NULL);\r
-\r
- return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));\r
-}\r
-\r
-/**\r
- Writes a 16-bit value to memory that may be unaligned.\r
-\r
- This function writes the 16-bit value specified by Value to Buffer. Value is\r
- returned. The function guarantees that the write operation does not produce\r
- an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 16-bit value that may be unaligned.\r
- @param Value The 16-bit value to write to Buffer.\r
-\r
- @return The 16-bit value to write to Buffer.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-WriteUnaligned16 (\r
- OUT UINT16 *Buffer,\r
- IN UINT16 Value\r
- )\r
-{\r
- ASSERT (Buffer != NULL);\r
-\r
- ((UINT8*)Buffer)[0] = (UINT8)Value;\r
- ((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);\r
-\r
- return Value;\r
-}\r
-\r
-/**\r
- Reads a 24-bit value from memory that may be unaligned.\r
-\r
- This function returns the 24-bit value pointed to by Buffer. The function\r
- guarantees that the read operation does not produce an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 24-bit value that may be unaligned.\r
-\r
- @return The 24-bit value read from Buffer.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-ReadUnaligned24 (\r
- IN CONST UINT32 *Buffer\r
- )\r
-{\r
- ASSERT (Buffer != NULL);\r
-\r
- return (UINT32)(\r
- ReadUnaligned16 ((UINT16*)Buffer) |\r
- (((UINT8*)Buffer)[2] << 16)\r
- );\r
-}\r
-\r
-/**\r
- Writes a 24-bit value to memory that may be unaligned.\r
-\r
- This function writes the 24-bit value specified by Value to Buffer. Value is\r
- returned. The function guarantees that the write operation does not produce\r
- an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 24-bit value that may be unaligned.\r
- @param Value The 24-bit value to write to Buffer.\r
-\r
- @return The 24-bit value to write to Buffer.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-WriteUnaligned24 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
- )\r
-{\r
- ASSERT (Buffer != NULL);\r
-\r
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
- *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);\r
- return Value;\r
-}\r
-\r
-/**\r
- Reads a 32-bit value from memory that may be unaligned.\r
-\r
- This function returns the 32-bit value pointed to by Buffer. The function\r
- guarantees that the read operation does not produce an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 32-bit value that may be unaligned.\r
-\r
- @return The 32-bit value read from Buffer.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-ReadUnaligned32 (\r
- IN CONST UINT32 *Buffer\r
- )\r
-{\r
- UINT16 LowerBytes;\r
- UINT16 HigherBytes;\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);\r
- HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);\r
-\r
- return (UINT32) (LowerBytes | (HigherBytes << 16));\r
-}\r
-\r
-/**\r
- Writes a 32-bit value to memory that may be unaligned.\r
-\r
- This function writes the 32-bit value specified by Value to Buffer. Value is\r
- returned. The function guarantees that the write operation does not produce\r
- an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 32-bit value that may be unaligned.\r
- @param Value The 32-bit value to write to Buffer.\r
-\r
- @return The 32-bit value to write to Buffer.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-WriteUnaligned32 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
- )\r
-{\r
- ASSERT (Buffer != NULL);\r
-\r
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
- WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));\r
- return Value;\r
-}\r
-\r
-/**\r
- Reads a 64-bit value from memory that may be unaligned.\r
-\r
- This function returns the 64-bit value pointed to by Buffer. The function\r
- guarantees that the read operation does not produce an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 64-bit value that may be unaligned.\r
-\r
- @return The 64-bit value read from Buffer.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-ReadUnaligned64 (\r
- IN CONST UINT64 *Buffer\r
- )\r
-{\r
- UINT32 LowerBytes;\r
- UINT32 HigherBytes;\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);\r
- HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);\r
-\r
- return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));\r
-}\r
-\r
-/**\r
- Writes a 64-bit value to memory that may be unaligned.\r
-\r
- This function writes the 64-bit value specified by Value to Buffer. Value is\r
- returned. The function guarantees that the write operation does not produce\r
- an alignment fault.\r
-\r
- If the Buffer is NULL, then ASSERT().\r
-\r
- @param Buffer The pointer to a 64-bit value that may be unaligned.\r
- @param Value The 64-bit value to write to Buffer.\r
-\r
- @return The 64-bit value to write to Buffer.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-WriteUnaligned64 (\r
- OUT UINT64 *Buffer,\r
- IN UINT64 Value\r
- )\r
-{\r
- ASSERT (Buffer != NULL);\r
-\r
- WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);\r
- WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));\r
- return Value;\r
-}\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources]\r
#\r
# The implementation is also useful as a fast priority queue.\r
#\r
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
# Copyright (C) 2014, Red Hat, Inc.\r
#\r
# This program and the accompanying materials are licensed and made available\r
LIBRARY_CLASS = OrderedCollectionLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-## @file\r
-# Null instance of PAL Library with empty functions.\r
-#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = BasePalLibNull\r
- MODULE_UNI_FILE = BasePalLibNull.uni\r
- FILE_GUID = 632D5625-B73D-43b8-AF30-8D225D96168E\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PalLib\r
-\r
-\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- PalCall.c\r
-\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-\r
-[LibraryClasses]\r
- DebugLib\r
-\r
+++ /dev/null
-// /** @file\r
-// Null instance of PAL Library with empty functions.\r
-//\r
-// Null instance of PAL Library with empty functions.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Null instance of PAL Library with empty functions"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "Null instance of PAL Library with empty functions."\r
-\r
+++ /dev/null
-/** @file\r
-\r
- Template and Sample instance of PalCallLib.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/PalLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-/**\r
- Makes a PAL procedure call.\r
-\r
- This is a wrapper function to make a PAL procedure call. Based on the Index value,\r
- this API will make static or stacked PAL call. Architected procedures may be designated\r
- as required or optional. If a PAL procedure is specified as optional, a unique return\r
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.\r
- This indicates that the procedure is not present in this PAL implementation. It is the\r
- caller's responsibility to check for this return code after calling any optional PAL\r
- procedure. No parameter checking is performed on the 4 input parameters, but there are\r
- some common rules that the caller should follow when making a PAL call. Any address\r
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses\r
- may cause undefined results. For those parameters defined as reserved or some fields\r
- defined as reserved must be zero filled or the invalid argument return value may be\r
- returned or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
-\r
- @param Index The PAL procedure Index number.\r
- @param Arg2 The 2nd parameter for PAL procedure calls.\r
- @param Arg3 The 3rd parameter for PAL procedure calls.\r
- @param Arg4 The 4th parameter for PAL procedure calls.\r
-\r
- @return The structure returned from the PAL Call procedure, including the status and return value.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-EFIAPI\r
-PalCall (\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- )\r
-{\r
- PAL_CALL_RETURN Ret;\r
-\r
- Ret.Status = (UINT64) -1;\r
- ASSERT (!RETURN_ERROR (RETURN_UNSUPPORTED));\r
- return Ret;\r
-}\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
LIBRARY_CLASS = PciCf8Lib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
LIBRARY_CLASS = PciExpressLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
LIBRARY_CLASS = PciLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources]\r
#\r
# Default PCI Segment Information Library that shouldn't be used by real platform.\r
#\r
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# PCI Segment Library that layers on top of the PCI Library which only\r
# supports segment 0 PCI configuration access.\r
#\r
-# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources]\r
[Sources.IA32, Sources.X64, Sources.EBC, Sources.AARCH64]\r
PeCoffLoaderEx.c\r
\r
-[Sources.IPF]\r
- Ipf/PeCoffLoaderEx.c\r
-\r
[Sources.ARM]\r
Arm/PeCoffLoaderEx.c\r
\r
+++ /dev/null
-/** @file\r
- Fixes Intel Itanium(TM) specific relocation types.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "BasePeCoffLibInternals.h"\r
-\r
-\r
-\r
-#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \\r
- Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)\r
-\r
-#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \\r
- *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \\r
- ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)\r
-\r
-#define IMM64_IMM7B_INST_WORD_X 3\r
-#define IMM64_IMM7B_SIZE_X 7\r
-#define IMM64_IMM7B_INST_WORD_POS_X 4\r
-#define IMM64_IMM7B_VAL_POS_X 0\r
-\r
-#define IMM64_IMM9D_INST_WORD_X 3\r
-#define IMM64_IMM9D_SIZE_X 9\r
-#define IMM64_IMM9D_INST_WORD_POS_X 18\r
-#define IMM64_IMM9D_VAL_POS_X 7\r
-\r
-#define IMM64_IMM5C_INST_WORD_X 3\r
-#define IMM64_IMM5C_SIZE_X 5\r
-#define IMM64_IMM5C_INST_WORD_POS_X 13\r
-#define IMM64_IMM5C_VAL_POS_X 16\r
-\r
-#define IMM64_IC_INST_WORD_X 3\r
-#define IMM64_IC_SIZE_X 1\r
-#define IMM64_IC_INST_WORD_POS_X 12\r
-#define IMM64_IC_VAL_POS_X 21\r
-\r
-#define IMM64_IMM41A_INST_WORD_X 1\r
-#define IMM64_IMM41A_SIZE_X 10\r
-#define IMM64_IMM41A_INST_WORD_POS_X 14\r
-#define IMM64_IMM41A_VAL_POS_X 22\r
-\r
-#define IMM64_IMM41B_INST_WORD_X 1\r
-#define IMM64_IMM41B_SIZE_X 8\r
-#define IMM64_IMM41B_INST_WORD_POS_X 24\r
-#define IMM64_IMM41B_VAL_POS_X 32\r
-\r
-#define IMM64_IMM41C_INST_WORD_X 2\r
-#define IMM64_IMM41C_SIZE_X 23\r
-#define IMM64_IMM41C_INST_WORD_POS_X 0\r
-#define IMM64_IMM41C_VAL_POS_X 40\r
-\r
-#define IMM64_SIGN_INST_WORD_X 3\r
-#define IMM64_SIGN_SIZE_X 1\r
-#define IMM64_SIGN_INST_WORD_POS_X 27\r
-#define IMM64_SIGN_VAL_POS_X 63\r
-\r
-/**\r
- Performs an Itanium-based specific relocation fixup.\r
-\r
- @param Reloc The pointer to the relocation record.\r
- @param Fixup The pointer to the address to fix up.\r
- @param FixupData The pointer to a buffer to log the fixups.\r
- @param Adjust The offset to adjust the fixup.\r
-\r
- @retval RETURN_SUCCESS Succeed to fix the relocation entry.\r
- @retval RETURN_UNSUPPOTED Unrecoganized relocation entry.\r
-\r
-**/\r
-RETURN_STATUS\r
-PeCoffLoaderRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
- )\r
-{\r
- UINT64 *Fixup64;\r
- UINT64 FixupVal;\r
-\r
- switch ((*Reloc) >> 12) {\r
- case EFI_IMAGE_REL_BASED_IA64_IMM64:\r
-\r
- //\r
- // Align it to bundle address before fixing up the\r
- // 64-bit immediate value of the movl instruction.\r
- //\r
-\r
- Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));\r
- FixupVal = (UINT64)0;\r
-\r
- //\r
- // Extract the lower 32 bits of IMM64 from bundle\r
- //\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,\r
- IMM64_IMM7B_SIZE_X,\r
- IMM64_IMM7B_INST_WORD_POS_X,\r
- IMM64_IMM7B_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,\r
- IMM64_IMM9D_SIZE_X,\r
- IMM64_IMM9D_INST_WORD_POS_X,\r
- IMM64_IMM9D_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,\r
- IMM64_IMM5C_SIZE_X,\r
- IMM64_IMM5C_INST_WORD_POS_X,\r
- IMM64_IMM5C_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IC_INST_WORD_X,\r
- IMM64_IC_SIZE_X,\r
- IMM64_IC_INST_WORD_POS_X,\r
- IMM64_IC_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64(FixupVal,\r
- (UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X,\r
- IMM64_IMM41A_SIZE_X,\r
- IMM64_IMM41A_INST_WORD_POS_X,\r
- IMM64_IMM41A_VAL_POS_X\r
- );\r
-\r
- //\r
- // Update 64-bit address\r
- //\r
- FixupVal += Adjust;\r
-\r
- //\r
- // Insert IMM64 into bundle\r
- //\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),\r
- IMM64_IMM7B_SIZE_X,\r
- IMM64_IMM7B_INST_WORD_POS_X,\r
- IMM64_IMM7B_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),\r
- IMM64_IMM9D_SIZE_X,\r
- IMM64_IMM9D_INST_WORD_POS_X,\r
- IMM64_IMM9D_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),\r
- IMM64_IMM5C_SIZE_X,\r
- IMM64_IMM5C_INST_WORD_POS_X,\r
- IMM64_IMM5C_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),\r
- IMM64_IC_SIZE_X,\r
- IMM64_IC_INST_WORD_POS_X,\r
- IMM64_IC_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X),\r
- IMM64_IMM41A_SIZE_X,\r
- IMM64_IMM41A_INST_WORD_POS_X,\r
- IMM64_IMM41A_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM41B_INST_WORD_X),\r
- IMM64_IMM41B_SIZE_X,\r
- IMM64_IMM41B_INST_WORD_POS_X,\r
- IMM64_IMM41B_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_IMM41C_INST_WORD_X),\r
- IMM64_IMM41C_SIZE_X,\r
- IMM64_IMM41C_INST_WORD_POS_X,\r
- IMM64_IMM41C_VAL_POS_X\r
- );\r
-\r
- INS_IMM64(FixupVal,\r
- ((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),\r
- IMM64_SIGN_SIZE_X,\r
- IMM64_SIGN_INST_WORD_POS_X,\r
- IMM64_SIGN_VAL_POS_X\r
- );\r
-\r
- Fixup64 = (UINT64 *) Fixup;\r
- if (*FixupData != NULL) {\r
- *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));\r
- *(UINT64 *)(*FixupData) = *Fixup64;\r
- *FixupData = *FixupData + sizeof(UINT64);\r
- }\r
- break;\r
-\r
- default:\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Returns TRUE if the machine type of PE/COFF image is supported. Supported\r
- does not mean the image can be executed it means the PE/COFF loader supports\r
- loading and relocating of the image type. It's up to the caller to support\r
- the entry point.\r
-\r
- The itanium version PE/COFF loader/relocater supports itanium and EBC image.\r
-\r
- @param Machine Machine type from the PE Header.\r
-\r
- @return TRUE if this PE/COFF loader can load the image\r
- @return FALSE unrecoganized machine type of image.\r
-\r
-**/\r
-BOOLEAN\r
-PeCoffLoaderImageFormatSupported (\r
- IN UINT16 Machine\r
- )\r
-{\r
- if ((Machine == IMAGE_FILE_MACHINE_IA64) || (Machine == IMAGE_FILE_MACHINE_EBC)) {\r
- return TRUE;\r
- }\r
-\r
- return FALSE;\r
-}\r
-\r
-\r
-/**\r
- ImageRead function that operates on a memory buffer whos base is passed into\r
- FileHandle.\r
-\r
- @param Reloc Ponter to baes of the input stream\r
- @param Fixup Offset to the start of the buffer\r
- @param FixupData The number of bytes to copy into the buffer\r
- @param Adjust Location to place results of read\r
-\r
- @retval RETURN_SUCCESS Data is read from FileOffset from the Handle into\r
- the buffer.\r
- @retval RETURN_UNSUPPORTED Un-recoganized relocation entry\r
- type.\r
-**/\r
-RETURN_STATUS\r
-PeHotRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
- )\r
-{\r
- UINT64 *Fixup64;\r
- UINT64 FixupVal;\r
-\r
- switch ((*Reloc) >> 12) {\r
- case EFI_IMAGE_REL_BASED_DIR64:\r
- Fixup64 = (UINT64 *) Fixup;\r
- *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));\r
- if (*(UINT64 *) (*FixupData) == *Fixup64) {\r
- *Fixup64 = *Fixup64 + (UINT64) Adjust;\r
- }\r
-\r
- *FixupData = *FixupData + sizeof (UINT64);\r
- break;\r
-\r
- case EFI_IMAGE_REL_BASED_IA64_IMM64:\r
- Fixup64 = (UINT64 *) Fixup;\r
- *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));\r
- if (*(UINT64 *) (*FixupData) == *Fixup64) {\r
- //\r
- // Align it to bundle address before fixing up the\r
- // 64-bit immediate value of the movl instruction.\r
- //\r
- //\r
- Fixup = (CHAR8 *) ((UINT64) Fixup & (UINT64)~(15));\r
- FixupVal = (UINT64) 0;\r
-\r
- //\r
- // Extract the lower 32 bits of IMM64 from bundle\r
- //\r
- EXT_IMM64 (\r
- FixupVal,\r
- (UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X,\r
- IMM64_IMM7B_SIZE_X,\r
- IMM64_IMM7B_INST_WORD_POS_X,\r
- IMM64_IMM7B_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64 (\r
- FixupVal,\r
- (UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X,\r
- IMM64_IMM9D_SIZE_X,\r
- IMM64_IMM9D_INST_WORD_POS_X,\r
- IMM64_IMM9D_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64 (\r
- FixupVal,\r
- (UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X,\r
- IMM64_IMM5C_SIZE_X,\r
- IMM64_IMM5C_INST_WORD_POS_X,\r
- IMM64_IMM5C_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64 (\r
- FixupVal,\r
- (UINT32 *) Fixup + IMM64_IC_INST_WORD_X,\r
- IMM64_IC_SIZE_X,\r
- IMM64_IC_INST_WORD_POS_X,\r
- IMM64_IC_VAL_POS_X\r
- );\r
-\r
- EXT_IMM64 (\r
- FixupVal,\r
- (UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X,\r
- IMM64_IMM41A_SIZE_X,\r
- IMM64_IMM41A_INST_WORD_POS_X,\r
- IMM64_IMM41A_VAL_POS_X\r
- );\r
-\r
- //\r
- // Update 64-bit address\r
- //\r
- FixupVal += Adjust;\r
-\r
- //\r
- // Insert IMM64 into bundle\r
- //\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X),\r
- IMM64_IMM7B_SIZE_X,\r
- IMM64_IMM7B_INST_WORD_POS_X,\r
- IMM64_IMM7B_VAL_POS_X\r
- );\r
-\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X),\r
- IMM64_IMM9D_SIZE_X,\r
- IMM64_IMM9D_INST_WORD_POS_X,\r
- IMM64_IMM9D_VAL_POS_X\r
- );\r
-\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X),\r
- IMM64_IMM5C_SIZE_X,\r
- IMM64_IMM5C_INST_WORD_POS_X,\r
- IMM64_IMM5C_VAL_POS_X\r
- );\r
-\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_IC_INST_WORD_X),\r
- IMM64_IC_SIZE_X,\r
- IMM64_IC_INST_WORD_POS_X,\r
- IMM64_IC_VAL_POS_X\r
- );\r
-\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X),\r
- IMM64_IMM41A_SIZE_X,\r
- IMM64_IMM41A_INST_WORD_POS_X,\r
- IMM64_IMM41A_VAL_POS_X\r
- );\r
-\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_IMM41B_INST_WORD_X),\r
- IMM64_IMM41B_SIZE_X,\r
- IMM64_IMM41B_INST_WORD_POS_X,\r
- IMM64_IMM41B_VAL_POS_X\r
- );\r
-\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_IMM41C_INST_WORD_X),\r
- IMM64_IMM41C_SIZE_X,\r
- IMM64_IMM41C_INST_WORD_POS_X,\r
- IMM64_IMM41C_VAL_POS_X\r
- );\r
-\r
- INS_IMM64 (\r
- FixupVal,\r
- ((UINT32 *) Fixup + IMM64_SIGN_INST_WORD_X),\r
- IMM64_SIGN_SIZE_X,\r
- IMM64_SIGN_INST_WORD_POS_X,\r
- IMM64_SIGN_VAL_POS_X\r
- );\r
-\r
- *(UINT64 *) (*FixupData) = *Fixup64;\r
- }\r
-\r
- *FixupData = *FixupData + sizeof (UINT64);\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "PeHotRelocateEx:unknown fixed type\n"));\r
- return RETURN_UNSUPPORTED;\r
- }\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-\r
-\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
\r
## @file\r
# Report Status Code Library with empty functions.\r
#\r
-# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# resume. All the library interfaces simply return EFI_SUCCESS without\r
# performing any operation.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials are\r
# licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# S3 PCI Segment Services that perform PCI Configuration cycles and\r
# also enable the PCI operation to be replayed during an S3 resume.\r
#\r
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials are\r
# licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# This library provides helper functions to prevent integer overflow during\r
# type conversion, addition, subtraction, and multiplication.\r
#\r
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
# Copyright (c) 2017, Microsoft Corporation\r
#\r
# All rights reserved.\r
[Sources.Ia32, Sources.ARM]\r
SafeIntLib32.c\r
\r
-[Sources.X64, Sources.IPF, Sources.AARCH64]\r
+[Sources.X64, Sources.AARCH64]\r
SafeIntLib64.c\r
\r
[Sources.EBC]\r
## @file\r
# Null instance of Serial Port Library with empty functions.\r
#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
## @file\r
# Null implementation of the SMBUS Library.\r
#\r
-# Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
LIBRARY_CLASS = SmbusLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
LIBRARY_CLASS = SynchronizationLib\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
[Sources]\r
BaseSynchronizationLibInternals.h\r
X64/GccInline.c | GCC\r
SynchronizationGcc.c | GCC\r
\r
-[Sources.IPF]\r
- Ipf/Synchronization.c\r
- Ipf/InterlockedCompareExchange64.s\r
- Ipf/InterlockedCompareExchange32.s\r
- Ipf/InterlockedCompareExchange16.s\r
-\r
- Ipf/InternalGetSpinLockProperties.c | MSFT\r
- Ipf/InternalGetSpinLockProperties.c | GCC\r
-\r
- Synchronization.c | INTEL\r
- SynchronizationMsc.c | MSFT\r
- SynchronizationGcc.c | GCC\r
-\r
[Sources.EBC]\r
Synchronization.c\r
Ebc/Synchronization.c\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of InterlockedCompareExchange16 on Itanium-\r
-/// based architecture.\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: InterlockedCompareExchange16.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc InternalSyncCompareExchange16\r
-.type InternalSyncCompareExchange16, @function\r
-InternalSyncCompareExchange16::\r
- zxt2 r33 = r33\r
- mov ar.ccv = r33\r
- cmpxchg2.rel r8 = [r32], r34\r
- mf\r
- br.ret.sptk.many b0\r
-.endp InternalSyncCompareExchange16\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of InterlockedCompareExchange32 on Itanium-\r
-/// based architecture.\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: InterlockedCompareExchange32.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc InternalSyncCompareExchange32\r
-.type InternalSyncCompareExchange32, @function\r
-InternalSyncCompareExchange32::\r
- zxt4 r33 = r33\r
- mov ar.ccv = r33\r
- cmpxchg4.rel r8 = [r32], r34\r
- mf\r
- br.ret.sptk.many b0\r
-.endp InternalSyncCompareExchange32\r
+++ /dev/null
-/// @file\r
-/// Contains an implementation of InterlockedCompareExchange64 on Itanium-\r
-/// based architecture.\r
-///\r
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-/// Module Name: InterlockedCompareExchange64.s\r
-///\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-.proc InternalSyncCompareExchange64\r
-.type InternalSyncCompareExchange64, @function\r
-InternalSyncCompareExchange64::\r
- mov ar.ccv = r33\r
- cmpxchg8.rel r8 = [r32], r34\r
- mf\r
- br.ret.sptk.many b0\r
-.endp InternalSyncCompareExchange64\r
+++ /dev/null
-/** @file\r
- Internal function to get spin lock alignment.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-/**\r
- Internal function to retrieve the architecture specific spin lock alignment\r
- requirements for optimal spin lock performance.\r
-\r
- @return The architecture specific spin lock alignment.\r
-\r
-**/\r
-UINTN\r
-InternalGetSpinLockProperties (\r
- VOID\r
- )\r
-{\r
- return 32;\r
-}\r
-\r
+++ /dev/null
-/** @file\r
- Implementation of synchronization functions on Itanium.\r
-\r
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "BaseSynchronizationLibInternals.h"\r
-\r
-/**\r
- Performs an atomic increment of an 32-bit unsigned integer.\r
-\r
- Performs an atomic increment of the 32-bit unsigned integer specified by\r
- Value and returns the incremented value. The increment operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- @param Value A pointer to the 32-bit value to increment.\r
-\r
- @return The incremented value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InternalSyncIncrement (\r
- IN volatile UINT32 *Value\r
- )\r
-{\r
- UINT32 OriginalValue;\r
-\r
- do {\r
- OriginalValue = *Value;\r
- } while (OriginalValue != InternalSyncCompareExchange32 (\r
- Value,\r
- OriginalValue,\r
- OriginalValue + 1\r
- ));\r
- return OriginalValue + 1;\r
-}\r
-\r
-/**\r
- Performs an atomic decrement of an 32-bit unsigned integer.\r
-\r
- Performs an atomic decrement of the 32-bit unsigned integer specified by\r
- Value and returns the decrement value. The decrement operation must be\r
- performed using MP safe mechanisms. The state of the return value is not\r
- guaranteed to be MP safe.\r
-\r
- @param Value A pointer to the 32-bit value to decrement.\r
-\r
- @return The decrement value.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-InternalSyncDecrement (\r
- IN volatile UINT32 *Value\r
- )\r
-{\r
- UINT32 OriginalValue;\r
-\r
- do {\r
- OriginalValue = *Value;\r
- } while (OriginalValue != InternalSyncCompareExchange32 (\r
- Value,\r
- OriginalValue,\r
- OriginalValue - 1\r
- ));\r
- return OriginalValue - 1;\r
-}\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
+++ /dev/null
-## @file\r
-# The library implements the Extended SAL Library Class for boot service only modules.\r
-#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxeExtendedSalLib\r
- MODULE_UNI_FILE = DxeExtendedSalLib.uni\r
- FILE_GUID = 8FDED21D-7AB5-4c26-8CF7-20EC4DB9861D\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ExtendedSalLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
- CONSTRUCTOR = DxeExtendedSalLibConstruct\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources.IPF]\r
- ExtendedSalLib.c\r
- Ipf/AsmExtendedSalLib.s\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- UefiBootServicesTableLib\r
-\r
-[Protocols]\r
- gEfiExtendedSalBootServiceProtocolGuid ## CONSUMES\r
-\r
-[Depex.common.DXE_DRIVER]\r
- gEfiExtendedSalBootServiceProtocolGuid\r
-\r
+++ /dev/null
-// /** @file\r
-// The library implements the Extended SAL Library Class for boot service only modules.\r
-//\r
-// This library implements the Extended SAL Library Class for boot service only modules.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Implements the Extended SAL Library Class for boot service only modules"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "This library implements the Extended SAL Library Class for boot service only modules."\r
-\r
+++ /dev/null
-/** @file\r
- The library implements the Extended SAL Library Class for boot service only modules.\r
-\r
- Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/ExtendedSalBootService.h>\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-\r
-#include <Library/ExtendedSalLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-/**\r
- Stores the physical plabel of ESAL entrypoint.\r
-\r
- This assembly function stores the physical plabel of ESAL entrypoint\r
- where GetEsalEntryPoint() can easily retrieve.\r
-\r
- @param EntryPoint Physical address of ESAL entrypoint\r
- @param Gp Physical GP of ESAL entrypoint\r
-\r
- @return r8 = EFI_SAL_SUCCESS\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-SetEsalPhysicalEntryPoint (\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Gp\r
- );\r
-\r
-/**\r
- Retrieves plabel of ESAL entrypoint.\r
-\r
- This function retrives plabel of ESAL entrypoint stored by\r
- SetEsalPhysicalEntryPoint().\r
-\r
- @return r8 = EFI_SAL_SUCCESS\r
- r9 = Physical Plabel\r
- r10 = Virtual Plabel\r
- r11 = PSR\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-GetEsalEntryPoint (\r
- VOID\r
- );\r
-\r
-EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *mEsalBootService = NULL;\r
-EFI_PLABEL mPlabel;\r
-\r
-/**\r
- Constructor function to get Extended SAL Boot Service Protocol, and initializes\r
- physical plabel of ESAL entrypoint.\r
-\r
- This function first locates Extended SAL Boot Service Protocol and caches it in global variable.\r
- Then it initializes the physical plable of ESAL entrypoint, and stores\r
- it where GetEsalEntryPoint() can easily retrieve.\r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS Plable of ESAL entrypoint successfully stored.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-DxeExtendedSalLibConstruct (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_PLABEL *Plabel;\r
- EFI_STATUS Status;\r
-\r
- //\r
- // The protocol contains a function pointer, which is an indirect procedure call.\r
- // An indirect procedure call goes through a plabel, and pointer to a function is\r
- // a pointer to a plabel. To implement indirect procedure calls that can work in\r
- // both physical and virtual mode, two plabels are required (one physical and one\r
- // virtual). So lets grap the physical PLABEL for the EsalEntryPoint and store it\r
- // away. We cache it in a module global, so we can register the vitrual version.\r
- //\r
- Status = gBS->LocateProtocol (&gEfiExtendedSalBootServiceProtocolGuid, NULL, (VOID **) &mEsalBootService);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Plabel = (EFI_PLABEL *) (UINTN) mEsalBootService->ExtendedSalProc;\r
- mPlabel.EntryPoint = Plabel->EntryPoint;\r
- mPlabel.GP = Plabel->GP;\r
- //\r
- // Stores the physical plabel of ESAL entrypoint where GetEsalEntryPoint() can easily retrieve.\r
- //\r
- SetEsalPhysicalEntryPoint (mPlabel.EntryPoint, mPlabel.GP);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Registers function of ESAL class and it's associated global.\r
-\r
- This function registers function of ESAL class, together with its associated global.\r
- It is worker function for RegisterEsalClass().\r
- It is only for boot time.\r
-\r
- @param FunctionId ID of function to register\r
- @param ClassGuidLo GUID of ESAL class, lower 64-bits\r
- @param ClassGuidHi GUID of ESAL class, upper 64-bits\r
- @param Function Function to register with ClassGuid/FunctionId pair\r
- @param ModuleGlobal Module global for the function.\r
-\r
- @return Status returned by RegisterExtendedSalProc() of Extended SAL Boot Service Protocol\r
-\r
-**/\r
-EFI_STATUS\r
-RegisterEsalFunction (\r
- IN UINT64 FunctionId,\r
- IN UINT64 ClassGuidLo,\r
- IN UINT64 ClassGuidHi,\r
- IN SAL_INTERNAL_EXTENDED_SAL_PROC Function,\r
- IN VOID *ModuleGlobal\r
- )\r
-{\r
- return mEsalBootService->RegisterExtendedSalProc (\r
- mEsalBootService,\r
- ClassGuidLo,\r
- ClassGuidHi,\r
- FunctionId,\r
- Function,\r
- ModuleGlobal\r
- );\r
-}\r
-\r
-/**\r
- Registers ESAL Class and it's associated global.\r
-\r
- This function registers one or more Extended SAL services in a given\r
- class along with the associated global context.\r
- This function is only available prior to ExitBootServices().\r
-\r
- @param ClassGuidLo GUID of function class, lower 64-bits\r
- @param ClassGuidHi GUID of function class, upper 64-bits\r
- @param ModuleGlobal Module global for the class.\r
- @param ... List of Function/FunctionId pairs, ended by NULL\r
-\r
- @retval EFI_SUCCESS The Extended SAL services were registered.\r
- @retval EFI_UNSUPPORTED This function was called after ExitBootServices().\r
- @retval EFI_OUT_OF_RESOURCES There are not enough resources available to register one or more of the specified services.\r
- @retval Other ClassGuid could not be installed onto a new handle.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RegisterEsalClass (\r
- IN CONST UINT64 ClassGuidLo,\r
- IN CONST UINT64 ClassGuidHi,\r
- IN VOID *ModuleGlobal, OPTIONAL\r
- ...\r
- )\r
-{\r
- VA_LIST Args;\r
- EFI_STATUS Status;\r
- SAL_INTERNAL_EXTENDED_SAL_PROC Function;\r
- UINT64 FunctionId;\r
- EFI_HANDLE NewHandle;\r
- EFI_GUID ClassGuid;\r
-\r
- VA_START (Args, ModuleGlobal);\r
-\r
- //\r
- // Register all functions of the class to register.\r
- //\r
- Status = EFI_SUCCESS;\r
- while (!EFI_ERROR (Status)) {\r
- Function = (SAL_INTERNAL_EXTENDED_SAL_PROC) VA_ARG (Args, SAL_INTERNAL_EXTENDED_SAL_PROC);\r
- //\r
- // NULL serves as the end mark of function list\r
- //\r
- if (Function == NULL) {\r
- break;\r
- }\r
-\r
- FunctionId = VA_ARG (Args, UINT64);\r
-\r
- Status = RegisterEsalFunction (FunctionId, ClassGuidLo, ClassGuidHi, Function, ModuleGlobal);\r
- }\r
-\r
- VA_END (Args);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- NewHandle = NULL;\r
- *((UINT64 *)(&ClassGuid) + 0) = ClassGuidLo;\r
- *((UINT64 *)(&ClassGuid) + 1) = ClassGuidHi;\r
- return gBS->InstallProtocolInterface (\r
- &NewHandle,\r
- &ClassGuid,\r
- EFI_NATIVE_INTERFACE,\r
- NULL\r
- );\r
-}\r
-\r
-/**\r
- Calls an Extended SAL Class service that was previously registered with RegisterEsalClass().\r
-\r
- This function gets the entrypoint of Extended SAL, and calls an Extended SAL Class service\r
- that was previously registered with RegisterEsalClass() through this entrypoint.\r
-\r
- @param ClassGuidLo GUID of function, lower 64-bits\r
- @param ClassGuidHi GUID of function, upper 64-bits\r
- @param FunctionId Function in ClassGuid to call\r
- @param Arg2 Argument 2 ClassGuid/FunctionId defined\r
- @param Arg3 Argument 3 ClassGuid/FunctionId defined\r
- @param Arg4 Argument 4 ClassGuid/FunctionId defined\r
- @param Arg5 Argument 5 ClassGuid/FunctionId defined\r
- @param Arg6 Argument 6 ClassGuid/FunctionId defined\r
- @param Arg7 Argument 7 ClassGuid/FunctionId defined\r
- @param Arg8 Argument 8 ClassGuid/FunctionId defined\r
-\r
- @retval EFI_SAL_SUCCESS ESAL procedure successfully called.\r
- @retval EFI_SAL_ERROR The address of ExtendedSalProc() can not be correctly\r
- initialized.\r
- @retval Other Status returned from ExtendedSalProc() service of\r
- EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalCall (\r
- IN UINT64 ClassGuidLo,\r
- IN UINT64 ClassGuidHi,\r
- IN UINT64 FunctionId,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4,\r
- IN UINT64 Arg5,\r
- IN UINT64 Arg6,\r
- IN UINT64 Arg7,\r
- IN UINT64 Arg8\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
- EXTENDED_SAL_PROC EsalProc;\r
-\r
- //\r
- // Get the entrypoint of Extended SAL\r
- //\r
- ReturnReg = GetEsalEntryPoint ();\r
- if (*(UINT64 *)ReturnReg.r9 == 0 && *(UINT64 *)(ReturnReg.r9 + 8) == 0) {\r
- //\r
- // The ESAL Entry Point could not be initialized\r
- //\r
- ReturnReg.Status = EFI_SAL_ERROR;\r
- return ReturnReg;\r
- }\r
-\r
- //\r
- // Test PSR.it which is BIT36\r
- //\r
- if ((ReturnReg.r11 & BIT36) != 0) {\r
- //\r
- // Virtual mode plabel to entry point\r
- //\r
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r10;\r
- } else {\r
- //\r
- // Physical mode plabel to entry point\r
- //\r
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r9;\r
- }\r
-\r
- return EsalProc (\r
- ClassGuidLo,\r
- ClassGuidHi,\r
- FunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalStallFunctionId service of Extended SAL Stall Services Class.\r
-\r
- This function is a wrapper for the EsalStallFunctionId service of Extended SAL\r
- Stall Services Class. See EsalStallFunctionId of Extended SAL Specification.\r
-\r
- @param Microseconds The number of microseconds to delay.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.\r
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalStall (\r
- IN UINTN Microseconds\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,\r
- StallFunctionId,\r
- Microseconds,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.\r
-\r
- This function is a wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL\r
- PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extended SAL Specification.\r
-\r
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.\r
- If FALSE, then PalEntryPoint is a virtual address.\r
- @param PalEntryPoint The PAL Entry Point being set.\r
-\r
- @retval EFI_SAL_SUCCESS The PAL Entry Point was set.\r
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before\r
- virtual mappings for the specified Extended SAL\r
- Procedure are available.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalSetNewPalEntry (\r
- IN BOOLEAN PhysicalAddress,\r
- IN UINT64 PalEntryPoint\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,\r
- SetNewPalEntryFunctionId,\r
- PhysicalAddress,\r
- PalEntryPoint,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.\r
-\r
- This function is a wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL\r
- PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extended SAL Specification.\r
-\r
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.\r
- If FALSE, then PalEntryPoint is a virtual address.\r
-\r
- @retval EFI_SAL_SUCCESS The PAL Entry Point was retrieved and returned in\r
- SAL_RETURN_REGS.r9.\r
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before\r
- virtual mappings for the specified Extended SAL\r
- Procedure are available.\r
- @return r9 PAL entry point retrieved.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetNewPalEntry (\r
- IN BOOLEAN PhysicalAddress\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,\r
- GetNewPalEntryFunctionId,\r
- PhysicalAddress,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL MCA Log Services Class.\r
-\r
- This function is a wrapper for the EsalGetStateBufferFunctionId service of Extended SAL\r
- MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL Specification.\r
-\r
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.\r
- @param McaBuffer A pointer to the base address of the returned buffer.\r
- Copied from SAL_RETURN_REGS.r9.\r
- @param BufferSize A pointer to the size, in bytes, of the returned buffer.\r
- Copied from SAL_RETURN_REGS.r10.\r
-\r
- @retval EFI_SAL_SUCCESS The memory buffer to store error records was returned in r9 and r10.\r
- @retval EFI_OUT_OF_RESOURCES A memory buffer for string error records in not available\r
- @return r9 Base address of the returned buffer\r
- @return r10 Size of the returned buffer in bytes\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetStateBuffer (\r
- IN UINT64 McaType,\r
- OUT UINT8 **McaBuffer,\r
- OUT UINTN *BufferSize\r
- )\r
-{\r
- SAL_RETURN_REGS Regs;\r
-\r
- Regs = EsalCall (\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,\r
- EsalGetStateBufferFunctionId,\r
- McaType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-\r
- *McaBuffer = (UINT8 *) Regs.r9;\r
- *BufferSize = Regs.r10;\r
-\r
- return Regs;\r
-}\r
-\r
-/**\r
- Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL MCA Log Services Class.\r
-\r
- This function is a wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL\r
- MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SAL Specification.\r
-\r
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.\r
-\r
- @retval EFI_SUCCESS The memory buffer containing the error record was written to nonvolatile storage.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalSaveStateBuffer (\r
- IN UINT64 McaType\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,\r
- EsalSaveStateBufferFunctionId,\r
- McaType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalGetVectorsFunctionId service of Extended SAL\r
- Base Services Class. See EsalGetVectorsFunctionId of Extended SAL Specification.\r
-\r
- @param VectorType The vector type to retrieve.\r
- 0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.\r
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered\r
- with the SAL Procedure SAL_SET_VECTORS.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetVectors (\r
- IN UINT64 VectorType\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalGetVectorsFunctionId,\r
- VectorType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL\r
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.\r
-\r
- @param ParamInfoType The parameter type to retrieve.\r
- 1 - rendezvous interrupt\r
- 2 - wake up\r
- 3 - Corrected Platform Error Vector.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.\r
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered\r
- with the SAL Procedure SAL_MC_SET_PARAMS.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcGetParams (\r
- IN UINT64 ParamInfoType\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalMcGetParamsFunctionId,\r
- ParamInfoType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL\r
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered\r
- with the SAL Procedure SAL_MC_SET_PARAMS.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcGetMcParams (\r
- VOID\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalMcGetMcParamsFunctionId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL\r
- Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL Specification.\r
-\r
- @param CpuIndex The index of the CPU of set of enabled CPUs to check.\r
-\r
- @retval EFI_SAL_SUCCESS The checkin status of the requested CPU was returned.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetMcCheckinFlags (\r
- IN UINT64 CpuIndex\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalGetMcCheckinFlagsFunctionId,\r
- CpuIndex,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalAddCpuDataFunctionId service of Extended SAL\r
- MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being added.\r
- @param Enabled The enable flag for the CPU being added.\r
- TRUE means the CPU is enabled.\r
- FALSE means the CPU is disabled.\r
- @param PalCompatibility The PAL Compatibility value for the CPU being added.\r
-\r
- @retval EFI_SAL_SUCCESS The CPU was added to the database.\r
- @retval EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource available to add the CPU.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalAddCpuData (\r
- IN UINT64 CpuGlobalId,\r
- IN BOOLEAN Enabled,\r
- IN UINT64 PalCompatibility\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- AddCpuDataFunctionId,\r
- CpuGlobalId,\r
- Enabled,\r
- PalCompatibility,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL\r
- MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being removed.\r
-\r
- @retval EFI_SAL_SUCCESS The CPU was removed from the database.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalRemoveCpuData (\r
- IN UINT64 CpuGlobalId\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- RemoveCpuDataFunctionId,\r
- CpuGlobalId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL\r
- MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being modified.\r
- @param Enabled The enable flag for the CPU being modified.\r
- TRUE means the CPU is enabled.\r
- FALSE means the CPU is disabled.\r
- @param PalCompatibility The PAL Compatibility value for the CPU being modified.\r
-\r
- @retval EFI_SAL_SUCCESS The CPU database was updated.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalModifyCpuData (\r
- IN UINT64 CpuGlobalId,\r
- IN BOOLEAN Enabled,\r
- IN UINT64 PalCompatibility\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- ModifyCpuDataFunctionId,\r
- CpuGlobalId,\r
- Enabled,\r
- PalCompatibility,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL\r
- MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being looked up.\r
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.\r
- If FALSE, then the index of set of all CPUs of database is returned.\r
-\r
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetCpuDataById (\r
- IN UINT64 CpuGlobalId,\r
- IN BOOLEAN IndexByEnabledCpu\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- GetCpuDataByIDFunctionId,\r
- CpuGlobalId,\r
- IndexByEnabledCpu,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL\r
- MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL Specification.\r
-\r
- @param Index The Global ID for the CPU being modified.\r
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.\r
- If FALSE, then the index of set of all CPUs of database is returned.\r
-\r
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetCpuDataByIndex (\r
- IN UINT64 Index,\r
- IN BOOLEAN IndexByEnabledCpu\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- GetCpuDataByIndexFunctionId,\r
- Index,\r
- IndexByEnabledCpu,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalWhoAmIFunctionId service of Extended SAL\r
- MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specification.\r
-\r
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.\r
- If FALSE, then the index of set of all CPUs of database is returned.\r
-\r
- @retval EFI_SAL_SUCCESS The Global ID for the calling CPU was returned.\r
- @retval EFI_SAL_NO_INFORMATION The calling CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalWhoAmI (\r
- IN BOOLEAN IndexByEnabledCpu\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- CurrentProcInfoFunctionId,\r
- IndexByEnabledCpu,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalNumProcessors service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalNumProcessors service of Extended SAL\r
- MP Services Class. See EsalNumProcessors of Extended SAL Specification.\r
-\r
- @retval EFI_SAL_SUCCESS The information on the number of CPUs in the platform\r
- was returned.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalNumProcessors (\r
- VOID\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- NumProcessorsFunctionId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalSetMinStateFnctionId service of Extended SAL\r
- MP Services Class. See EsalSetMinStateFnctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being set.\r
- @param MinStatePointer The physical address of the MINSTATE buffer for the CPU\r
- specified by CpuGlobalId.\r
-\r
- @retval EFI_SAL_SUCCESS The MINSTATE pointer was set for the specified CPU.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalSetMinState (\r
- IN UINT64 CpuGlobalId,\r
- IN EFI_PHYSICAL_ADDRESS MinStatePointer\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- SetMinStateFunctionId,\r
- CpuGlobalId,\r
- MinStatePointer,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalGetMinStateFunctionId service of Extended SAL\r
- MP Services Class. See EsalGetMinStateFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being retrieved.\r
-\r
- @retval EFI_SAL_SUCCESS The MINSTATE pointer for the specified CPU was retrieved.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetMinState (\r
- IN UINT64 CpuGlobalId\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- GetMinStateFunctionId,\r
- CpuGlobalId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL MCA Services Class.\r
-\r
- This function is a wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL\r
- MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being retrieved.\r
- @param StateBufferPointer A pointer to the returned MCA state buffer.\r
- @param RequiredStateBufferSize A pointer to the size, in bytes, of the returned MCA state buffer.\r
-\r
- @retval EFI_SUCCESS MINSTATE successfully got and size calculated.\r
- @retval EFI_SAL_NO_INFORMATION Fail to get MINSTATE.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcaGetStateInfo (\r
- IN UINT64 CpuGlobalId,\r
- OUT EFI_PHYSICAL_ADDRESS *StateBufferPointer,\r
- OUT UINT64 *RequiredStateBufferSize\r
- )\r
-{\r
- SAL_RETURN_REGS Regs;\r
-\r
- Regs = EsalCall (\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,\r
- McaGetStateInfoFunctionId,\r
- CpuGlobalId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-\r
- *StateBufferPointer = (EFI_PHYSICAL_ADDRESS) Regs.r9;\r
- *RequiredStateBufferSize = (UINT64) Regs.r10;\r
-\r
- return Regs;\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL MCA Services Class.\r
-\r
- This function is a wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL\r
- MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being set.\r
- @param StateBufferPointer A pointer to the MCA state buffer.\r
-\r
- @retval EFI_SAL_NO_INFORMATION Cannot get the processor info with the CpuId\r
- @retval EFI_SUCCESS Save the processor's state info successfully\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcaRegisterCpu (\r
- IN UINT64 CpuGlobalId,\r
- IN EFI_PHYSICAL_ADDRESS StateBufferPointer\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,\r
- McaRegisterCpuFunctionId,\r
- CpuGlobalId,\r
- StateBufferPointer,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
+++ /dev/null
-/// @file\r
-/// Assembly procedures to get and set ESAL entry point.\r
-///\r
-/// Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-#include "IpfMacro.i"\r
-\r
-//\r
-// Exports\r
-//\r
-ASM_GLOBAL GetEsalEntryPoint\r
-\r
-//-----------------------------------------------------------------------------\r
-//++\r
-// GetEsalEntryPoint\r
-//\r
-// Return Esal global and PSR register.\r
-//\r
-// On Entry :\r
-//\r
-//\r
-// Return Value:\r
-// r8 = EFI_SAL_SUCCESS\r
-// r9 = Physical Plabel\r
-// r10 = Virtual Plabel\r
-// r11 = psr\r
-// \r
-// As per static calling conventions. \r
-// \r
-//--\r
-//---------------------------------------------------------------------------\r
-PROCEDURE_ENTRY (GetEsalEntryPoint)\r
-\r
- NESTED_SETUP (0,8,0,0)\r
-\r
-EsalCalcStart:\r
- mov r8 = ip;;\r
- add r8 = (EsalEntryPoint - EsalCalcStart), r8;;\r
- mov r9 = r8;;\r
- add r10 = 0x10, r8;;\r
- mov r11 = psr;;\r
- mov r8 = r0;;\r
-\r
- NESTED_RETURN\r
-\r
-PROCEDURE_EXIT (GetEsalEntryPoint)\r
-\r
-//-----------------------------------------------------------------------------\r
-//++\r
-// SetEsalPhysicalEntryPoint\r
-//\r
-// Set the dispatcher entry point\r
-//\r
-// On Entry:\r
-// in0 = Physical address of Esal Dispatcher\r
-// in1 = Physical GP\r
-//\r
-// Return Value: \r
-// r8 = EFI_SAL_SUCCESS\r
-// \r
-// As per static calling conventions. \r
-// \r
-//--\r
-//---------------------------------------------------------------------------\r
-PROCEDURE_ENTRY (SetEsalPhysicalEntryPoint)\r
-\r
- NESTED_SETUP (2,8,0,0)\r
-\r
-EsalCalcStart1:\r
- mov r8 = ip;;\r
- add r8 = (EsalEntryPoint - EsalCalcStart1), r8;;\r
- st8 [r8] = in0;;\r
- add r8 = 0x08, r8;;\r
- st8 [r8] = in1;;\r
- mov r8 = r0;;\r
-\r
- NESTED_RETURN\r
-\r
-PROCEDURE_EXIT (SetEsalPhysicalEntryPoint)\r
-\r
-.align 32\r
-EsalEntryPoint: \r
- data8 0 // Physical Entry\r
- data8 0 // GP\r
- data8 0 // Virtual Entry\r
- data8 0 // GP\r
FILE_GUID = f773469b-e265-4b0c-b0a6-2f971fbfe72b\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
CONSTRUCTOR = DxeExtractGuidedSectionLibConstructor\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
FILE_GUID = f12b59c9-76d0-4661-ad7c-f04d1bef0558\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
CONSTRUCTOR = HobLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
## @file\r
# DXE instance of Hsti Library.\r
#\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 7DE1C620-F587-4116-A36D-40F3467B9A0C\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
[Sources]\r
HstiAip.c\r
FILE_GUID = 33D33BF3-349E-4768-9459-836A9F7558FB\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_SAL_DRIVER\r
+ LIBRARY_CLASS = IoLib|DXE_DRIVER\r
CONSTRUCTOR = IoLibConstructor\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-## @file\r
-# I/O Library instance that layers on top of Itanium ESAL services.\r
-#\r
-# I/O Library implementation that uses Itanium ESAL services for I/O\r
-# and MMIO operations.\r
-#\r
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-# This program and the accompanying materials are licensed and made available\r
-# under the terms and conditions of the BSD License which accompanies this\r
-# distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxeIoLibEsal\r
- MODULE_UNI_FILE = DxeIoLibEsal.uni\r
- FILE_GUID = 0D8E6E4E-B029-475f-9122-60A3FEDBA8C0\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- IoHighLevel.c\r
- IoLib.c\r
- IoLibMmioBuffer.c\r
- DxeIoLibEsalInternal.h\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- ExtendedSalLib\r
- BaseLib\r
- DebugLib\r
-\r
-[Depex]\r
- gEfiExtendedSalBaseIoServicesProtocolGuid\r
-\r
+++ /dev/null
-// /** @file\r
-// I/O Library instance that layers on top of Itanium ESAL services.\r
-//\r
-// I/O Library implementation that uses Itanium ESAL services for I/O\r
-// and MMIO operations.\r
-//\r
-// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials are licensed and made available\r
-// under the terms and conditions of the BSD License which accompanies this\r
-// distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "I/O Library instance that layers on top of Itanium ESAL services"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "I/O Library implementation that uses Itanium ESAL services for I/O and MMIO operations."\r
-\r
+++ /dev/null
-/** @file\r
- Internal include file for the I/O Library using ESAL services.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials are licensed and made available\r
- under the terms and conditions of the BSD License which accompanies this\r
- distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __DXE_IO_LIB_ESAL_INTERNAL_H_\r
-#define __DXE_IO_LIB_ESAL_INTERNAL_H_\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/CpuIo2.h>\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/ExtendedSalLib.h>\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- High-level Io/Mmio functions.\r
-\r
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "DxeIoLibEsalInternal.h"\r
-\r
-/**\r
- Reads an 8-bit I/O port, performs a bitwise OR, and writes the\r
- result back to the 8-bit I/O port.\r
-\r
- Reads the 8-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 8-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoOr8 (\r
- IN UINTN Port,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));\r
-}\r
-\r
-/**\r
- Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back\r
- to the 8-bit I/O port.\r
-\r
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 8-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoAnd8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));\r
-}\r
-\r
-/**\r
- Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 8-bit I/O port.\r
-\r
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, performs a bitwise OR\r
- between the result of the AND operation and the value specified by OrData,\r
- and writes the result to the 8-bit I/O port specified by Port. The value\r
- written to the I/O port is returned. This function must guarantee that all\r
- I/O read and write operations are serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of an I/O register.\r
-\r
- Reads the bit field in an 8-bit I/O register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoBitFieldRead8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to an I/O register.\r
-\r
- Writes Value to the bit field of the I/O register. The bit field is specified\r
- by the StartBit and the EndBit. All other bits in the destination I/O\r
- register are preserved. The value written to the I/O port is returned. Extra\r
- left bits in Value are stripped.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoBitFieldWrite8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- return IoWrite8 (\r
- Port,\r
- BitFieldWrite8 (IoRead8 (Port), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the\r
- result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 8-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized. Extra left bits in OrData are stripped.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoBitFieldOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return IoWrite8 (\r
- Port,\r
- BitFieldOr8 (IoRead8 (Port), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the\r
- result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 8-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized. Extra left bits in AndData are stripped.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoBitFieldAnd8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return IoWrite8 (\r
- Port,\r
- BitFieldAnd8 (IoRead8 (Port), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
-\r
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed\r
- by a bitwise OR between the read result and the value specified by\r
- AndData, and writes the result to the 8-bit I/O port specified by Port. The\r
- value written to the I/O port is returned. This function must guarantee that\r
- all I/O read and write operations are serialized. Extra left bits in both\r
- AndData and OrData are stripped.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoBitFieldAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return IoWrite8 (\r
- Port,\r
- BitFieldAndThenOr8 (IoRead8 (Port), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 16-bit I/O port, performs a bitwise OR, and writes the\r
- result back to the 16-bit I/O port.\r
-\r
- Reads the 16-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 16-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoOr16 (\r
- IN UINTN Port,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));\r
-}\r
-\r
-/**\r
- Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back\r
- to the 16-bit I/O port.\r
-\r
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 16-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoAnd16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));\r
-}\r
-\r
-/**\r
- Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 16-bit I/O port.\r
-\r
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, performs a bitwise OR\r
- between the result of the AND operation and the value specified by OrData,\r
- and writes the result to the 16-bit I/O port specified by Port. The value\r
- written to the I/O port is returned. This function must guarantee that all\r
- I/O read and write operations are serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of an I/O register.\r
-\r
- Reads the bit field in a 16-bit I/O register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoBitFieldRead16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to an I/O register.\r
-\r
- Writes Value to the bit field of the I/O register. The bit field is specified\r
- by the StartBit and the EndBit. All other bits in the destination I/O\r
- register are preserved. The value written to the I/O port is returned. Extra\r
- left bits in Value are stripped.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoBitFieldWrite16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- return IoWrite16 (\r
- Port,\r
- BitFieldWrite16 (IoRead16 (Port), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the\r
- result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 16-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized. Extra left bits in OrData are stripped.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoBitFieldOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return IoWrite16 (\r
- Port,\r
- BitFieldOr16 (IoRead16 (Port), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the\r
- result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 16-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized. Extra left bits in AndData are stripped.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoBitFieldAnd16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return IoWrite16 (\r
- Port,\r
- BitFieldAnd16 (IoRead16 (Port), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 16-bit port.\r
-\r
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed\r
- by a bitwise OR between the read result and the value specified by\r
- AndData, and writes the result to the 16-bit I/O port specified by Port. The\r
- value written to the I/O port is returned. This function must guarantee that\r
- all I/O read and write operations are serialized. Extra left bits in both\r
- AndData and OrData are stripped.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoBitFieldAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return IoWrite16 (\r
- Port,\r
- BitFieldAndThenOr16 (IoRead16 (Port), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 32-bit I/O port, performs a bitwise OR, and writes the\r
- result back to the 32-bit I/O port.\r
-\r
- Reads the 32-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 32-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoOr32 (\r
- IN UINTN Port,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return IoWrite32 (Port, IoRead32 (Port) | OrData);\r
-}\r
-\r
-/**\r
- Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back\r
- to the 32-bit I/O port.\r
-\r
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 32-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoAnd32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return IoWrite32 (Port, IoRead32 (Port) & AndData);\r
-}\r
-\r
-/**\r
- Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 32-bit I/O port.\r
-\r
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, performs a bitwise OR\r
- between the result of the AND operation and the value specified by OrData,\r
- and writes the result to the 32-bit I/O port specified by Port. The value\r
- written to the I/O port is returned. This function must guarantee that all\r
- I/O read and write operations are serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of an I/O register.\r
-\r
- Reads the bit field in a 32-bit I/O register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoBitFieldRead32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to an I/O register.\r
-\r
- Writes Value to the bit field of the I/O register. The bit field is specified\r
- by the StartBit and the EndBit. All other bits in the destination I/O\r
- register are preserved. The value written to the I/O port is returned. Extra\r
- left bits in Value are stripped.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoBitFieldWrite32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- return IoWrite32 (\r
- Port,\r
- BitFieldWrite32 (IoRead32 (Port), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the\r
- result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 32-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized. Extra left bits in OrData are stripped.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoBitFieldOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return IoWrite32 (\r
- Port,\r
- BitFieldOr32 (IoRead32 (Port), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the\r
- result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 32-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized. Extra left bits in AndData are stripped.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoBitFieldAnd32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return IoWrite32 (\r
- Port,\r
- BitFieldAnd32 (IoRead32 (Port), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 32-bit port.\r
-\r
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed\r
- by a bitwise OR between the read result and the value specified by\r
- AndData, and writes the result to the 32-bit I/O port specified by Port. The\r
- value written to the I/O port is returned. This function must guarantee that\r
- all I/O read and write operations are serialized. Extra left bits in both\r
- AndData and OrData are stripped.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoBitFieldAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return IoWrite32 (\r
- Port,\r
- BitFieldAndThenOr32 (IoRead32 (Port), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 64-bit I/O port, performs a bitwise OR, and writes the\r
- result back to the 64-bit I/O port.\r
-\r
- Reads the 64-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 64-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoOr64 (\r
- IN UINTN Port,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return IoWrite64 (Port, IoRead64 (Port) | OrData);\r
-}\r
-\r
-/**\r
- Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back\r
- to the 64-bit I/O port.\r
-\r
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 64-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoAnd64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData\r
- )\r
-{\r
- return IoWrite64 (Port, IoRead64 (Port) & AndData);\r
-}\r
-\r
-/**\r
- Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 64-bit I/O port.\r
-\r
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, performs a bitwise OR\r
- between the result of the AND operation and the value specified by OrData,\r
- and writes the result to the 64-bit I/O port specified by Port. The value\r
- written to the I/O port is returned. This function must guarantee that all\r
- I/O read and write operations are serialized.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of an I/O register.\r
-\r
- Reads the bit field in a 64-bit I/O register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoBitFieldRead64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to an I/O register.\r
-\r
- Writes Value to the bit field of the I/O register. The bit field is specified\r
- by the StartBit and the EndBit. All other bits in the destination I/O\r
- register are preserved. The value written to the I/O port is returned. Extra\r
- left bits in Value are stripped.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoBitFieldWrite64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
- )\r
-{\r
- return IoWrite64 (\r
- Port,\r
- BitFieldWrite64 (IoRead64 (Port), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the\r
- result back to the bit field in the 64-bit port.\r
-\r
- Reads the 64-bit I/O port specified by Port, performs a bitwise OR\r
- between the read result and the value specified by OrData, and writes the\r
- result to the 64-bit I/O port specified by Port. The value written to the I/O\r
- port is returned. This function must guarantee that all I/O read and write\r
- operations are serialized. Extra left bits in OrData are stripped.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param OrData The value to OR with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoBitFieldOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return IoWrite64 (\r
- Port,\r
- BitFieldOr64 (IoRead64 (Port), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the\r
- result back to the bit field in the 64-bit port.\r
-\r
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
- the read result and the value specified by AndData, and writes the result to\r
- the 64-bit I/O port specified by Port. The value written to the I/O port is\r
- returned. This function must guarantee that all I/O read and write operations\r
- are serialized. Extra left bits in AndData are stripped.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param AndData The value to AND with the value read from the I/O port.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoBitFieldAnd64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
- )\r
-{\r
- return IoWrite64 (\r
- Port,\r
- BitFieldAnd64 (IoRead64 (Port), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 64-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 64-bit port.\r
-\r
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed\r
- by a bitwise OR between the read result and the value specified by\r
- AndData, and writes the result to the 64-bit I/O port specified by Port. The\r
- value written to the I/O port is returned. This function must guarantee that\r
- all I/O read and write operations are serialized. Extra left bits in both\r
- AndData and OrData are stripped.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param AndData The value to AND with the value read from the I/O port.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoBitFieldAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return IoWrite64 (\r
- Port,\r
- BitFieldAndThenOr64 (IoRead64 (Port), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads an 8-bit MMIO register, performs a bitwise OR, and writes the\r
- result back to the 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 8-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param OrData The value to OR with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result\r
- back to the 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 8-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, performs a\r
- bitwise OR between the result of the AND operation and the value specified by\r
- OrData, and writes the result to the 8-bit MMIO register specified by\r
- Address. The value written to the MMIO register is returned. This function\r
- must guarantee that all MMIO read and write operations are serialized.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
-\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a MMIO register.\r
-\r
- Reads the bit field in an 8-bit MMIO register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address MMIO register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a MMIO register.\r
-\r
- Writes Value to the bit field of the MMIO register. The bit field is\r
- specified by the StartBit and the EndBit. All other bits in the destination\r
- MMIO register are preserved. The new value of the 8-bit register is returned.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- return MmioWrite8 (\r
- Address,\r
- BitFieldWrite8 (MmioRead8 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and\r
- writes the result back to the bit field in the 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 8-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized. Extra left bits in OrData\r
- are stripped.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return MmioWrite8 (\r
- Address,\r
- BitFieldOr8 (MmioRead8 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and\r
- writes the result back to the bit field in the 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 8-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized. Extra left bits in AndData are\r
- stripped.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return MmioWrite8 (\r
- Address,\r
- BitFieldAnd8 (MmioRead8 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed\r
- by a bitwise OR, and writes the result back to the bit field in the\r
- 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
- followed by a bitwise OR between the read result and the value\r
- specified by AndData, and writes the result to the 8-bit MMIO register\r
- specified by Address. The value written to the MMIO register is returned.\r
- This function must guarantee that all MMIO read and write operations are\r
- serialized. Extra left bits in both AndData and OrData are stripped.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return MmioWrite8 (\r
- Address,\r
- BitFieldAndThenOr8 (MmioRead8 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 16-bit MMIO register, performs a bitwise OR, and writes the\r
- result back to the 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 16-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param OrData The value to OR with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result\r
- back to the 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 16-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, performs a\r
- bitwise OR between the result of the AND operation and the value specified by\r
- OrData, and writes the result to the 16-bit MMIO register specified by\r
- Address. The value written to the MMIO register is returned. This function\r
- must guarantee that all MMIO read and write operations are serialized.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
-\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a MMIO register.\r
-\r
- Reads the bit field in a 16-bit MMIO register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address MMIO register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a MMIO register.\r
-\r
- Writes Value to the bit field of the MMIO register. The bit field is\r
- specified by the StartBit and the EndBit. All other bits in the destination\r
- MMIO register are preserved. The new value of the 16-bit register is returned.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- return MmioWrite16 (\r
- Address,\r
- BitFieldWrite16 (MmioRead16 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 16-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized. Extra left bits in OrData\r
- are stripped.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return MmioWrite16 (\r
- Address,\r
- BitFieldOr16 (MmioRead16 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and\r
- writes the result back to the bit field in the 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 16-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized. Extra left bits in AndData are\r
- stripped.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return MmioWrite16 (\r
- Address,\r
- BitFieldAnd16 (MmioRead16 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed\r
- by a bitwise OR, and writes the result back to the bit field in the\r
- 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
- followed by a bitwise OR between the read result and the value\r
- specified by AndData, and writes the result to the 16-bit MMIO register\r
- specified by Address. The value written to the MMIO register is returned.\r
- This function must guarantee that all MMIO read and write operations are\r
- serialized. Extra left bits in both AndData and OrData are stripped.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return MmioWrite16 (\r
- Address,\r
- BitFieldAndThenOr16 (MmioRead16 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 32-bit MMIO register, performs a bitwise OR, and writes the\r
- result back to the 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 32-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param OrData The value to OR with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return MmioWrite32 (Address, MmioRead32 (Address) | OrData);\r
-}\r
-\r
-/**\r
- Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result\r
- back to the 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 32-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return MmioWrite32 (Address, MmioRead32 (Address) & AndData);\r
-}\r
-\r
-/**\r
- Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, performs a\r
- bitwise OR between the result of the AND operation and the value specified by\r
- OrData, and writes the result to the 32-bit MMIO register specified by\r
- Address. The value written to the MMIO register is returned. This function\r
- must guarantee that all MMIO read and write operations are serialized.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
-\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a MMIO register.\r
-\r
- Reads the bit field in a 32-bit MMIO register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address MMIO register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a MMIO register.\r
-\r
- Writes Value to the bit field of the MMIO register. The bit field is\r
- specified by the StartBit and the EndBit. All other bits in the destination\r
- MMIO register are preserved. The new value of the 32-bit register is returned.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- return MmioWrite32 (\r
- Address,\r
- BitFieldWrite32 (MmioRead32 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and\r
- writes the result back to the bit field in the 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 32-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized. Extra left bits in OrData\r
- are stripped.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return MmioWrite32 (\r
- Address,\r
- BitFieldOr32 (MmioRead32 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and\r
- writes the result back to the bit field in the 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 32-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized. Extra left bits in AndData are\r
- stripped.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return MmioWrite32 (\r
- Address,\r
- BitFieldAnd32 (MmioRead32 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed\r
- by a bitwise OR, and writes the result back to the bit field in the\r
- 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
- followed by a bitwise OR between the read result and the value\r
- specified by AndData, and writes the result to the 32-bit MMIO register\r
- specified by Address. The value written to the MMIO register is returned.\r
- This function must guarantee that all MMIO read and write operations are\r
- serialized. Extra left bits in both AndData and OrData are stripped.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return MmioWrite32 (\r
- Address,\r
- BitFieldAndThenOr32 (MmioRead32 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 64-bit MMIO register, performs a bitwise OR, and writes the\r
- result back to the 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 64-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param OrData The value to OR with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioOr64 (\r
- IN UINTN Address,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return MmioWrite64 (Address, MmioRead64 (Address) | OrData);\r
-}\r
-\r
-/**\r
- Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result\r
- back to the 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 64-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
- )\r
-{\r
- return MmioWrite64 (Address, MmioRead64 (Address) & AndData);\r
-}\r
-\r
-/**\r
- Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise\r
- inclusive OR, and writes the result back to the 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, performs a\r
- bitwise OR between the result of the AND operation and the value specified by\r
- OrData, and writes the result to the 64-bit MMIO register specified by\r
- Address. The value written to the MMIO register is returned. This function\r
- must guarantee that all MMIO read and write operations are serialized.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
-\r
-\r
- @param Address The MMIO register to write.\r
- @param AndData The value to AND with the value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a MMIO register.\r
-\r
- Reads the bit field in a 64-bit MMIO register. The bit field is specified by\r
- the StartBit and the EndBit. The value of the bit field is returned.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address MMIO register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioBitFieldRead64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a MMIO register.\r
-\r
- Writes Value to the bit field of the MMIO register. The bit field is\r
- specified by the StartBit and the EndBit. All other bits in the destination\r
- MMIO register are preserved. The new value of the 64-bit register is returned.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioBitFieldWrite64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
- )\r
-{\r
- return MmioWrite64 (\r
- Address,\r
- BitFieldWrite64 (MmioRead64 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and\r
- writes the result back to the bit field in the 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address, performs a bitwise\r
- inclusive OR between the read result and the value specified by OrData, and\r
- writes the result to the 64-bit MMIO register specified by Address. The value\r
- written to the MMIO register is returned. This function must guarantee that\r
- all MMIO read and write operations are serialized. Extra left bits in OrData\r
- are stripped.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param OrData The value to OR with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioBitFieldOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return MmioWrite64 (\r
- Address,\r
- BitFieldOr64 (MmioRead64 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and\r
- writes the result back to the bit field in the 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
- between the read result and the value specified by AndData, and writes the\r
- result to the 64-bit MMIO register specified by Address. The value written to\r
- the MMIO register is returned. This function must guarantee that all MMIO\r
- read and write operations are serialized. Extra left bits in AndData are\r
- stripped.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param AndData The value to AND with value read from the MMIO register.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
- )\r
-{\r
- return MmioWrite64 (\r
- Address,\r
- BitFieldAnd64 (MmioRead64 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed\r
- by a bitwise OR, and writes the result back to the bit field in the\r
- 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
- followed by a bitwise OR between the read result and the value\r
- specified by AndData, and writes the result to the 64-bit MMIO register\r
- specified by Address. The value written to the MMIO register is returned.\r
- This function must guarantee that all MMIO read and write operations are\r
- serialized. Extra left bits in both AndData and OrData are stripped.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
- If StartBit is greater than 63, then ASSERT().\r
- If EndBit is greater than 63, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address MMIO register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..63.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..63.\r
- @param AndData The value to AND with value read from the MMIO register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioBitFieldAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
- )\r
-{\r
- return MmioWrite64 (\r
- Address,\r
- BitFieldAndThenOr64 (MmioRead64 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
+++ /dev/null
-/** @file\r
- I/O Library basic function implementation and worker functions.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "DxeIoLibEsalInternal.h"\r
-\r
-/**\r
- Reads registers in the EFI CPU I/O space.\r
-\r
- Reads the I/O port specified by Port with registers width specified by Width.\r
- The read value is returned.\r
-\r
- This function must guarantee that all I/O read and write operations are serialized.\r
- If such operations are not supported, then ASSERT().\r
-\r
- @param Port The base address of the I/O operation.\r
- The caller is responsible for aligning the Address if required.\r
- @param Width The width of the I/O operation.\r
-\r
- @return Data read from registers in the EFI CPU I/O space.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoReadWorker (\r
- IN UINTN Port,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
- UINT64 Data;\r
-\r
- Data = 0;\r
-\r
- ReturnReg = EsalCall (\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,\r
- IoReadFunctionId,\r
- (UINT64)Width,\r
- Port,\r
- 1,\r
- (UINT64)&Data,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);\r
- return Data;\r
-}\r
-\r
-/**\r
- Writes registers in the EFI CPU I/O space.\r
-\r
- Writes the I/O port specified by Port with registers width and value specified by Width\r
- and Data respectively. Data is returned.\r
-\r
- This function must guarantee that all I/O read and write operations are serialized.\r
- If such operations are not supported, then ASSERT().\r
-\r
- @param Port The base address of the I/O operation.\r
- The caller is responsible for aligning the Address if required.\r
- @param Width The width of the I/O operation.\r
- @param Data The value to write to the I/O port.\r
-\r
- @return The parameter of Data.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoWriteWorker (\r
- IN UINTN Port,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Data\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
-\r
- ReturnReg = EsalCall (\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,\r
- IoWriteFunctionId,\r
- (UINT64)Width,\r
- Port,\r
- 1,\r
- (UINT64)&Data,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);\r
- return Data;\r
-}\r
-\r
-/**\r
- Reads registers in the EFI CPU I/O space.\r
-\r
- Reads the I/O port specified by Port with registers width specified by Width.\r
- The port is read Count times, and the read data is stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are serialized.\r
- If such operations are not supported, then ASSERT().\r
-\r
- @param Port The base address of the I/O operation.\r
- The caller is responsible for aligning the Address if required.\r
- @param Width The width of the I/O operation.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifoWorker (\r
- IN UINTN Port,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
-\r
- ReturnReg = EsalCall (\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,\r
- IoReadFunctionId,\r
- (UINT64)Width,\r
- Port,\r
- Count,\r
- (UINT64)Buffer,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);\r
-}\r
-\r
-/**\r
- Writes registers in the EFI CPU I/O space.\r
-\r
- Writes the I/O port specified by Port with registers width specified by Width.\r
- The port is written Count times, and the write data is retrieved from the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are serialized.\r
- If such operations are not supported, then ASSERT().\r
-\r
- @param Port The base address of the I/O operation.\r
- The caller is responsible for aligning the Address if required.\r
- @param Width The width of the I/O operation.\r
- @param Count The number of times to write I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifoWorker (\r
- IN UINTN Port,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
-\r
- ReturnReg = EsalCall (\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,\r
- IoWriteFunctionId,\r
- (UINT64)Width,\r
- Port,\r
- Count,\r
- (UINT64)Buffer,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);\r
-}\r
-\r
-/**\r
- Reads memory-mapped registers in the EFI system memory space.\r
-\r
- Reads the MMIO registers specified by Address with registers width specified by Width.\r
- The read value is returned. If such operations are not supported, then ASSERT().\r
- This function must guarantee that all MMIO read and write operations are serialized.\r
-\r
- @param Address The MMIO register to read.\r
- The caller is responsible for aligning the Address if required.\r
- @param Width The width of the I/O operation.\r
-\r
- @return Data read from registers in the EFI system memory space.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioReadWorker (\r
- IN UINTN Address,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
- UINT64 Data;\r
-\r
- Data = 0;\r
-\r
- ReturnReg = EsalCall (\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,\r
- MemReadFunctionId,\r
- (UINT64)Width,\r
- Address,\r
- 1,\r
- (UINT64)&Data,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);\r
- return Data;\r
-}\r
-\r
-/**\r
- Writes memory-mapped registers in the EFI system memory space.\r
-\r
- Writes the MMIO registers specified by Address with registers width and value specified by Width\r
- and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r
- This function must guarantee that all MMIO read and write operations are serialized.\r
-\r
- @param Address The MMIO register to read.\r
- The caller is responsible for aligning the Address if required.\r
- @param Width The width of the I/O operation.\r
- @param Data The value to write to memory-mapped registers\r
-\r
- @return Data read from registers in the EFI system memory space.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioWriteWorker (\r
- IN UINTN Address,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Data\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
-\r
- ReturnReg = EsalCall (\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,\r
- MemWriteFunctionId,\r
- (UINT64)Width,\r
- Address,\r
- 1,\r
- (UINT64)&Data,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);\r
- return Data;\r
-}\r
-\r
-/**\r
- Reads an 8-bit I/O port.\r
-\r
- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoRead8 (\r
- IN UINTN Port\r
- )\r
-{\r
- return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);\r
-}\r
-\r
-/**\r
- Writes an 8-bit I/O port.\r
-\r
- Writes the 8-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
- )\r
-{\r
- return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);\r
-}\r
-\r
-/**\r
- Reads a 16-bit I/O port.\r
-\r
- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoRead16 (\r
- IN UINTN Port\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 16-bit boundary.\r
- //\r
- ASSERT ((Port & 1) == 0);\r
- return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);\r
-}\r
-\r
-/**\r
- Writes a 16-bit I/O port.\r
-\r
- Writes the 16-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 16-bit boundary.\r
- //\r
- ASSERT ((Port & 1) == 0);\r
- return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);\r
-}\r
-\r
-/**\r
- Reads a 32-bit I/O port.\r
-\r
- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoRead32 (\r
- IN UINTN Port\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 32-bit boundary.\r
- //\r
- ASSERT ((Port & 3) == 0);\r
- return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);\r
-}\r
-\r
-/**\r
- Writes a 32-bit I/O port.\r
-\r
- Writes the 32-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 32-bit boundary.\r
- //\r
- ASSERT ((Port & 3) == 0);\r
- return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);\r
-}\r
-\r
-/**\r
- Reads a 64-bit I/O port.\r
-\r
- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoRead64 (\r
- IN UINTN Port\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 64-bit boundary.\r
- //\r
- ASSERT ((Port & 7) == 0);\r
- return IoReadWorker (Port, EfiCpuIoWidthUint64);\r
-}\r
-\r
-/**\r
- Writes a 64-bit I/O port.\r
-\r
- Writes the 64-bit I/O port specified by Port with the value specified by Value\r
- and returns Value. This function must guarantee that all I/O read and write\r
- operations are serialized.\r
-\r
- If 64-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Value The value to write to the I/O port.\r
-\r
- @return The value written the I/O port.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 64-bit boundary.\r
- //\r
- ASSERT ((Port & 7) == 0);\r
- return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);\r
-}\r
-\r
-/**\r
- Reads an 8-bit I/O port fifo into a block of memory.\r
-\r
- Reads the 8-bit I/O fifo port specified by Port.\r
- The port is read Count times, and the read data is\r
- stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);\r
-}\r
-\r
-/**\r
- Writes a block of memory into an 8-bit I/O port fifo.\r
-\r
- Writes the 8-bit I/O fifo port specified by Port.\r
- The port is written Count times, and the write data is\r
- retrieved from the provided Buffer.\r
-\r
- This function must guarantee that all I/O write and write operations are\r
- serialized.\r
-\r
- If 8-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Count The number of times to write I/O port.\r
- @param Buffer The buffer to retrieve the write data from.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);\r
-}\r
-\r
-/**\r
- Reads a 16-bit I/O port fifo into a block of memory.\r
-\r
- Reads the 16-bit I/O fifo port specified by Port.\r
- The port is read Count times, and the read data is\r
- stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 16-bit boundary.\r
- //\r
- ASSERT ((Port & 1) == 0);\r
- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);\r
-}\r
-\r
-/**\r
- Writes a block of memory into a 16-bit I/O port fifo.\r
-\r
- Writes the 16-bit I/O fifo port specified by Port.\r
- The port is written Count times, and the write data is\r
- retrieved from the provided Buffer.\r
-\r
- This function must guarantee that all I/O write and write operations are\r
- serialized.\r
-\r
- If 16-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Count The number of times to write I/O port.\r
- @param Buffer The buffer to retrieve the write data from.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 16-bit boundary.\r
- //\r
- ASSERT ((Port & 1) == 0);\r
- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);\r
-}\r
-\r
-/**\r
- Reads a 32-bit I/O port fifo into a block of memory.\r
-\r
- Reads the 32-bit I/O fifo port specified by Port.\r
- The port is read Count times, and the read data is\r
- stored in the provided Buffer.\r
-\r
- This function must guarantee that all I/O read and write operations are\r
- serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to read.\r
- @param Count The number of times to read I/O port.\r
- @param Buffer The buffer to store the read data into.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 32-bit boundary.\r
- //\r
- ASSERT ((Port & 3) == 0);\r
- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);\r
-}\r
-\r
-/**\r
- Writes a block of memory into a 32-bit I/O port fifo.\r
-\r
- Writes the 32-bit I/O fifo port specified by Port.\r
- The port is written Count times, and the write data is\r
- retrieved from the provided Buffer.\r
-\r
- This function must guarantee that all I/O write and write operations are\r
- serialized.\r
-\r
- If 32-bit I/O port operations are not supported, then ASSERT().\r
-\r
- @param Port The I/O port to write.\r
- @param Count The number of times to write I/O port.\r
- @param Buffer The buffer to retrieve the write data from.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- )\r
-{\r
- //\r
- // Make sure Port is aligned on a 32-bit boundary.\r
- //\r
- ASSERT ((Port & 3) == 0);\r
- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);\r
-}\r
-\r
-/**\r
- Reads an 8-bit MMIO register.\r
-\r
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioRead8 (\r
- IN UINTN Address\r
- )\r
-{\r
- return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);\r
-}\r
-\r
-/**\r
- Writes an 8-bit MMIO register.\r
-\r
- Writes the 8-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 8-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
- )\r
-{\r
- return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);\r
-}\r
-\r
-/**\r
- Reads a 16-bit MMIO register.\r
-\r
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioRead16 (\r
- IN UINTN Address\r
- )\r
-{\r
- //\r
- // Make sure Address is aligned on a 16-bit boundary.\r
- //\r
- ASSERT ((Address & 1) == 0);\r
- return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);\r
-}\r
-\r
-/**\r
- Writes a 16-bit MMIO register.\r
-\r
- Writes the 16-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 16-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
- )\r
-{\r
- //\r
- // Make sure Address is aligned on a 16-bit boundary.\r
- //\r
- ASSERT ((Address & 1) == 0);\r
- return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);\r
-}\r
-\r
-/**\r
- Reads a 32-bit MMIO register.\r
-\r
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioRead32 (\r
- IN UINTN Address\r
- )\r
-{\r
- //\r
- // Make sure Address is aligned on a 32-bit boundary.\r
- //\r
- ASSERT ((Address & 3) == 0);\r
- return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);\r
-}\r
-\r
-/**\r
- Writes a 32-bit MMIO register.\r
-\r
- Writes the 32-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 32-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
- )\r
-{\r
- //\r
- // Make sure Address is aligned on a 32-bit boundary.\r
- //\r
- ASSERT ((Address & 3) == 0);\r
- return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);\r
-}\r
-\r
-/**\r
- Reads a 64-bit MMIO register.\r
-\r
- Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
- returned. This function must guarantee that all MMIO read and write\r
- operations are serialized.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to read.\r
-\r
- @return The value read.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioRead64 (\r
- IN UINTN Address\r
- )\r
-{\r
- //\r
- // Make sure Address is aligned on a 64-bit boundary.\r
- //\r
- ASSERT ((Address & 7) == 0);\r
- return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);\r
-}\r
-\r
-/**\r
- Writes a 64-bit MMIO register.\r
-\r
- Writes the 64-bit MMIO register specified by Address with the value specified\r
- by Value and returns Value. This function must guarantee that all MMIO read\r
- and write operations are serialized.\r
-\r
- If 64-bit MMIO register operations are not supported, then ASSERT().\r
-\r
- @param Address The MMIO register to write.\r
- @param Value The value to write to the MMIO register.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
- )\r
-{\r
- //\r
- // Make sure Address is aligned on a 64-bit boundary.\r
- //\r
- ASSERT ((Address & 7) == 0);\r
- return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);\r
-}\r
+++ /dev/null
-/** @file\r
- I/O Library MMIO Buffer Functions.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "DxeIoLibEsalInternal.h"\r
-\r
-/**\r
- Copy data from MMIO region to system memory by using 8-bit access.\r
-\r
- Copy data from MMIO region specified by starting address StartAddress\r
- to system memory specified by Buffer by using 8-bit access. The total\r
- number of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
-\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied from.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer receiving the data read.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT8 *\r
-EFIAPI\r
-MmioReadBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer\r
- )\r
-{\r
- UINT8 *ReturnBuffer;\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ReturnBuffer = Buffer;\r
-\r
- while (Length-- > 0) {\r
- *(Buffer++) = MmioRead8 (StartAddress++);\r
- }\r
-\r
- return ReturnBuffer;\r
-}\r
-\r
-/**\r
- Copy data from MMIO region to system memory by using 16-bit access.\r
-\r
- Copy data from MMIO region specified by starting address StartAddress\r
- to system memory specified by Buffer by using 16-bit access. The total\r
- number of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If StartAddress is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
-\r
- If Length is not aligned on a 16-bit boundary, then ASSERT().\r
- If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied from.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer receiving the data read.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT16 *\r
-EFIAPI\r
-MmioReadBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT16 *Buffer\r
- )\r
-{\r
- UINT16 *ReturnBuffer;\r
-\r
- ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
-\r
- ReturnBuffer = Buffer;\r
-\r
- while (Length > 0) {\r
- *(Buffer++) = MmioRead16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
- }\r
-\r
- return ReturnBuffer;\r
-}\r
-\r
-/**\r
- Copy data from MMIO region to system memory by using 32-bit access.\r
-\r
- Copy data from MMIO region specified by starting address StartAddress\r
- to system memory specified by Buffer by using 32-bit access. The total\r
- number of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If StartAddress is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
-\r
- If Length is not aligned on a 32-bit boundary, then ASSERT().\r
- If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied from.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer receiving the data read.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT32 *\r
-EFIAPI\r
-MmioReadBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT32 *Buffer\r
- )\r
-{\r
- UINT32 *ReturnBuffer;\r
-\r
- ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
-\r
- ReturnBuffer = Buffer;\r
-\r
- while (Length > 0) {\r
- *(Buffer++) = MmioRead32 (StartAddress);\r
- StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
- }\r
-\r
- return ReturnBuffer;\r
-}\r
-\r
-/**\r
- Copy data from MMIO region to system memory by using 64-bit access.\r
-\r
- Copy data from MMIO region specified by starting address StartAddress\r
- to system memory specified by Buffer by using 64-bit access. The total\r
- number of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If StartAddress is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
-\r
- If Length is not aligned on a 64-bit boundary, then ASSERT().\r
- If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied from.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer receiving the data read.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT64 *\r
-EFIAPI\r
-MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
- )\r
-{\r
- UINT64 *ReturnBuffer;\r
-\r
- ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
-\r
- ReturnBuffer = Buffer;\r
-\r
- while (Length > 0) {\r
- *(Buffer++) = MmioRead64 (StartAddress);\r
- StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
- }\r
-\r
- return ReturnBuffer;\r
-}\r
-\r
-\r
-/**\r
- Copy data from system memory to MMIO region by using 8-bit access.\r
-\r
- Copy data from system memory specified by Buffer to MMIO region specified\r
- by starting address StartAddress by using 8-bit access. The total number\r
- of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
-\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied to.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer containing the data to write.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT8 *\r
-EFIAPI\r
-MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
- )\r
-{\r
- VOID* ReturnBuffer;\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ReturnBuffer = (UINT8 *) Buffer;\r
-\r
- while (Length-- > 0) {\r
- MmioWrite8 (StartAddress++, *(Buffer++));\r
- }\r
-\r
- return ReturnBuffer;\r
-\r
-}\r
-\r
-/**\r
- Copy data from system memory to MMIO region by using 16-bit access.\r
-\r
- Copy data from system memory specified by Buffer to MMIO region specified\r
- by starting address StartAddress by using 16-bit access. The total number\r
- of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If StartAddress is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
-\r
- If Length is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied to.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer containing the data to write.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT16 *\r
-EFIAPI\r
-MmioWriteBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT16 *Buffer\r
- )\r
-{\r
- UINT16 *ReturnBuffer;\r
-\r
- ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
-\r
- ReturnBuffer = (UINT16 *) Buffer;\r
-\r
- while (Length > 0) {\r
- MmioWrite16 (StartAddress, *(Buffer++));\r
-\r
- StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
- }\r
-\r
- return ReturnBuffer;\r
-}\r
-\r
-\r
-/**\r
- Copy data from system memory to MMIO region by using 32-bit access.\r
-\r
- Copy data from system memory specified by Buffer to MMIO region specified\r
- by starting address StartAddress by using 32-bit access. The total number\r
- of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If StartAddress is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
-\r
- If Length is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied to.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer containing the data to write.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT32 *\r
-EFIAPI\r
-MmioWriteBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT32 *Buffer\r
- )\r
-{\r
- UINT32 *ReturnBuffer;\r
-\r
- ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
-\r
- ReturnBuffer = (UINT32 *) Buffer;\r
-\r
- while (Length > 0) {\r
- MmioWrite32 (StartAddress, *(Buffer++));\r
-\r
- StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
- }\r
-\r
- return ReturnBuffer;\r
-}\r
-\r
-/**\r
- Copy data from system memory to MMIO region by using 64-bit access.\r
-\r
- Copy data from system memory specified by Buffer to MMIO region specified\r
- by starting address StartAddress by using 64-bit access. The total number\r
- of byte to be copied is specified by Length. Buffer is returned.\r
-\r
- If StartAddress is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().\r
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
-\r
- If Length is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
-\r
- @param StartAddress Starting address for the MMIO region to be copied to.\r
- @param Length Size in bytes of the copy.\r
- @param Buffer Pointer to a system memory buffer containing the data to write.\r
-\r
- @return Buffer\r
-\r
-**/\r
-UINT64 *\r
-EFIAPI\r
-MmioWriteBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT64 *Buffer\r
- )\r
-{\r
- UINT64 *ReturnBuffer;\r
-\r
- ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
-\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
-\r
- ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
-\r
- ReturnBuffer = (UINT64 *) Buffer;\r
-\r
- while (Length > 0) {\r
- MmioWrite64 (StartAddress, *(Buffer++));\r
-\r
- StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
- }\r
-\r
- return ReturnBuffer;\r
-}\r
-\r
+++ /dev/null
-/** @file\r
- PAL Library Class implementation built upon Extended SAL Procedures.\r
-\r
- Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-\r
-#include <Library/PalLib.h>\r
-#include <Library/ExtendedSalLib.h>\r
-\r
-/**\r
- Makes a PAL procedure call.\r
-\r
- This is a wrapper function to make a PAL procedure call. Based on the Index value,\r
- this API will make static or stacked PAL call. Architected procedures may be designated\r
- as required or optional. If a PAL procedure is specified as optional, a unique return\r
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.\r
- This indicates that the procedure is not present in this PAL implementation. It is the\r
- caller's responsibility to check for this return code after calling any optional PAL\r
- procedure. No parameter checking is performed on the 4 input parameters, but there are\r
- some common rules that the caller should follow when making a PAL call. Any address\r
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses\r
- may cause undefined results. For those parameters defined as reserved or some fields\r
- defined as reserved must be zero filled or the invalid argument return value may be\r
- returned or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
-\r
- @param Index - The PAL procedure Index number.\r
- @param Arg2 - The 2nd parameter for PAL procedure calls.\r
- @param Arg3 - The 3rd parameter for PAL procedure calls.\r
- @param Arg4 - The 4th parameter for PAL procedure calls.\r
-\r
- @return structure returned from the PAL Call procedure, including the status and return value.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-EFIAPI\r
-PalCall (\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- )\r
-{\r
- SAL_RETURN_REGS SalReturn;\r
- PAL_CALL_RETURN *PalReturn;\r
-\r
- SalReturn = EsalCall (\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,\r
- PalProcFunctionId,\r
- Index,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- PalReturn = (PAL_CALL_RETURN *) (UINTN) (&SalReturn);\r
- return *PalReturn;\r
-}\r
+++ /dev/null
-## @file\r
-# Instance of PAL Library Class using Extended SAL functions\r
-#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxePalLibEsal\r
- MODULE_UNI_FILE = DxePalLibEsal.uni\r
- FILE_GUID = 8BA65DE3-39E1-4afd-A8FE-7DD0BAFEFCC0\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PalLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources.IPF]\r
- DxePalLibEsal.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- ExtendedSalLib\r
-\r
-[Depex.common.DXE_DRIVER, Depex.common.DXE_RUNTIME_DRIVER, Depex.common.DXE_SAL_DRIVER, Depex.common.DXE_SMM_DRIVER]\r
- gEfiExtendedSalPalServicesProtocolGuid\r
-\r
+++ /dev/null
-// /** @file\r
-// Instance of PAL Library Class using Extended SAL functions\r
-//\r
-// An instance of PAL Library Class using Extended SAL functions.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "An instance of PAL Library Class using Extended SAL functions."\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "An instance of PAL Library Class using Extended SAL functions."\r
-\r
FILE_GUID = af97eb89-4cc6-45f8-a514-ca025b346480\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-## @file\r
-# PCI Library that uses ESAL services to perform PCI Configuration cycles.\r
-#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxePciLibEsal\r
- MODULE_UNI_FILE = DxePciLibEsal.uni\r
- FILE_GUID = E3441740-3B41-4c90-9C9D-964056C7417D\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- PciLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- ExtendedSalLib\r
- DebugLib\r
- BaseLib\r
-\r
+++ /dev/null
-// /** @file\r
-// PCI Library that uses ESAL services to perform PCI Configuration cycles.\r
-//\r
-// The PCI Library that uses ESAL services to perform PCI Configuration cycles.\r
-//\r
-// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Uses ESAL services to perform PCI Configuration cycles"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "The PCI Library that uses ESAL services to perform PCI Configuration cycles."\r
-\r
+++ /dev/null
-/** @file\r
- DXE PCI Library instance layered on top of ESAL services.\r
-\r
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-\r
-#include <Library/PciLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/ExtendedSalLib.h>\r
-\r
-/**\r
- Assert the validity of a PCI address. A valid PCI address should contain 1's\r
- only in the low 28 bits.\r
-\r
- @param A The address to validate.\r
- @param M Additional bits to assert to be zero.\r
-\r
-**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
- ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
-\r
-/**\r
- Converts a PCI Library Address to a ESAL PCI Service Address.\r
- Based on SAL Spec 3.2, there are two SAL PCI Address:\r
-\r
- If address type = 0\r
- Bits 0..7 - Register address\r
- Bits 8..10 - Function number\r
- Bits 11..15 - Device number\r
- Bits 16..23 - Bus number\r
- Bits 24..31 - PCI segment group\r
- Bits 32..63 - Reserved (0)\r
-\r
- If address type = 1\r
- Bits 0..7 - Register address\r
- Bits 8..11 - Extended Register address\r
- Bits 12..14 - Function number\r
- Bits 15..19 - Device number\r
- Bits 20..27 - Bus number\r
- Bits 28..43 - PCI segment group\r
- Bits 44..63 - Reserved (0)\r
-\r
- @param A The PCI Library Address to convert.\r
-\r
-**/\r
-#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) ((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))\r
-#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (Address)\r
-\r
-/**\r
- Check a PCI Library Address is a PCI Compatible Address or not.\r
-**/\r
-#define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)\r
-\r
-/**\r
- Internal worker function to read a PCI configuration register.\r
-\r
- This function wraps EsalPciConfigRead function of Extended SAL PCI\r
- Services Class.\r
- It reads and returns the PCI configuration register specified by Address,\r
- the width of data is specified by Width.\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Width Width of data to read\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-DxePciLibEsalReadWorker (\r
- IN UINTN Address,\r
- IN UINTN Width\r
- )\r
-{\r
- SAL_RETURN_REGS Return;\r
-\r
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r
- Return = EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigReadFunctionId,\r
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r
- Width,\r
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- } else {\r
- Return = EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigReadFunctionId,\r
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r
- Width,\r
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- }\r
-\r
- return (UINT32) Return.r9;\r
-}\r
-\r
-/**\r
- Internal worker function to writes a PCI configuration register.\r
-\r
- This function wraps EsalPciConfigWrite function of Extended SAL PCI\r
- Services Class.\r
- It writes the PCI configuration register specified by Address with the\r
- value specified by Data. The width of data is specified by Width.\r
- Data is returned.\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Width Width of data to write\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-DxePciLibEsalWriteWorker (\r
- IN UINTN Address,\r
- IN UINTN Width,\r
- IN UINT32 Data\r
- )\r
-{\r
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r
- EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigWriteFunctionId,\r
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r
- Width,\r
- Data,\r
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- } else {\r
- EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigWriteFunctionId,\r
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r
- Width,\r
- Data,\r
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- }\r
-\r
- return Data;\r
-}\r
-\r
-/**\r
- Register a PCI device so PCI configuration registers may be accessed after\r
- SetVirtualAddressMap().\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
- after ExitBootServices().\r
- @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
- at runtime could not be mapped.\r
- @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
- complete the registration.\r
-\r
-**/\r
-RETURN_STATUS\r
-EFIAPI\r
-PciRegisterForRuntimeAccess (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Reads an 8-bit PCI configuration register.\r
-\r
- Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciRead8 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
-\r
- return (UINT8) DxePciLibEsalReadWorker (Address, 1);\r
-}\r
-\r
-/**\r
- Writes an 8-bit PCI configuration register.\r
-\r
- Writes the 8-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
-\r
- return (UINT8) DxePciLibEsalWriteWorker (Address, 1, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of an 8-bit PCI configuration register with\r
- an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise OR with another 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 8-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- return PciWrite8 (\r
- Address,\r
- BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciWrite8 (\r
- Address,\r
- BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 8-bit register.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciWrite8 (\r
- Address,\r
- BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciWrite8 (\r
- Address,\r
- BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 16-bit PCI configuration register.\r
-\r
- Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciRead16 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
-\r
- return (UINT16) DxePciLibEsalReadWorker (Address, 2);\r
-}\r
-\r
-/**\r
- Writes a 16-bit PCI configuration register.\r
-\r
- Writes the 16-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
-\r
- return (UINT16) DxePciLibEsalWriteWorker (Address, 2, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of a 16-bit PCI configuration register with\r
- a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise OR with another 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 16-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- return PciWrite16 (\r
- Address,\r
- BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciWrite16 (\r
- Address,\r
- BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciWrite16 (\r
- Address,\r
- BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciWrite16 (\r
- Address,\r
- BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 32-bit PCI configuration register.\r
-\r
- Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciRead32 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
-\r
- return DxePciLibEsalReadWorker (Address, 4);\r
-}\r
-\r
-/**\r
- Writes a 32-bit PCI configuration register.\r
-\r
- Writes the 32-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
-\r
- return DxePciLibEsalWriteWorker (Address, 4, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of a 32-bit PCI configuration register with\r
- a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciWrite32 (Address, PciRead32 (Address) | OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciWrite32 (Address, PciRead32 (Address) & AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise OR with another 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 32-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- return PciWrite32 (\r
- Address,\r
- BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciWrite32 (\r
- Address,\r
- BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 32-bit register.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciWrite32 (\r
- Address,\r
- BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciWrite32 (\r
- Address,\r
- BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a range of PCI configuration registers into a caller supplied buffer.\r
-\r
- Reads the range of PCI configuration registers specified by StartAddress and\r
- Size into the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be read. Size is\r
- returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
- and 16-bit PCI configuration read cycles may be used at the beginning and the\r
- end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
-\r
- if (Size == 0) {\r
- return Size;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Read a byte if StartAddress is byte aligned\r
- //\r
- *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Read a word if StartAddress is word aligned\r
- //\r
- *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Read as many double words as possible\r
- //\r
- *(volatile UINT32 *)Buffer = PciRead32 (StartAddress);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Read the last remaining word if exist\r
- //\r
- *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Read the last remaining byte if exist\r
- //\r
- *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
-\r
-/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI\r
- configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress and\r
- Size from the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be written. Size is\r
- returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
- and the end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
-\r
- if (Size == 0) {\r
- return 0;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Write a byte if StartAddress is byte aligned\r
- //\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Write a word if StartAddress is word aligned\r
- //\r
- PciWrite16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Write as many double words as possible\r
- //\r
- PciWrite32 (StartAddress, *(UINT32*)Buffer);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Write the last remaining word if exist\r
- //\r
- PciWrite16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Write the last remaining byte if exist\r
- //\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
+++ /dev/null
-// /** @file\r
-// PCI Segment Library that uses ESAL services to perform PCI Configuration cycles.\r
-//\r
-// The PCI Segment Library that uses ESAL services to perform PCI Configuration cycles.\r
-//\r
-// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Uses ESAL services to perform PCI Configuration cycles"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "The PCI Segment Library that uses ESAL services to perform PCI Configuration cycles."\r
-\r
+++ /dev/null
-## @file\r
-# PCI Segment Library that uses ESAL services to perform PCI Configuration cycles.\r
-#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxePciSegementLibEsal\r
- MODULE_UNI_FILE = DxePciSegementLibEsal.uni\r
- FILE_GUID = 6D497A7A-D7DA-467c-B485-B7FB3493C41F\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- PciLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- ExtendedSalLib\r
- DebugLib\r
- BaseLib\r
-\r
+++ /dev/null
-/** @file\r
- DXE PCI Segment Library instance layered on top of ESAL services.\r
-\r
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-\r
-#include <Library/PciSegmentLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/ExtendedSalLib.h>\r
-\r
-/**\r
- Assert the validity of a PCI Segment address.\r
- A valid PCI Segment address should not contain 1's in bits 31:28\r
-\r
- @param A The address to validate.\r
- @param M Additional bits to assert to be zero.\r
-\r
-**/\r
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
- ASSERT (((A) & (0xf0000000 | (M))) == 0)\r
-\r
-/**\r
- Converts a PCI Library Address to a ESAL PCI Service Address.\r
- Based on SAL Spec 3.2, there are two SAL PCI Address:\r
-\r
- If address type = 0\r
- Bits 0..7 - Register address\r
- Bits 8..10 - Function number\r
- Bits 11..15 - Device number\r
- Bits 16..23 - Bus number\r
- Bits 24..31 - PCI segment group\r
- Bits 32..63 - Reserved (0)\r
-\r
- If address type = 1\r
- Bits 0..7 - Register address\r
- Bits 8..11 - Extended Register address\r
- Bits 12..14 - Function number\r
- Bits 15..19 - Device number\r
- Bits 20..27 - Bus number\r
- Bits 28..43 - PCI segment group\r
- Bits 44..63 - Reserved (0)\r
-\r
- @param A The PCI Library Address to convert.\r
-\r
-**/\r
-#define CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) (((Address >> 8) & 0xff000000) | (((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))\r
-#define CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (((Address >> 4) & 0xffff0000000) | ((Address) & 0xfffffff))\r
-\r
-/**\r
- Check a PCI Library Address is a PCI Compatible Address or not.\r
-**/\r
-#define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)\r
-\r
-/**\r
- Internal worker function to read a PCI configuration register.\r
-\r
- This function wraps EsalPciConfigRead function of Extended SAL PCI\r
- Services Class.\r
- It reads and returns the PCI configuration register specified by Address,\r
- the width of data is specified by Width.\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Width Width of data to read\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-DxePciSegmentLibEsalReadWorker (\r
- IN UINT64 Address,\r
- IN UINTN Width\r
- )\r
-{\r
- SAL_RETURN_REGS Return;\r
-\r
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r
- Return = EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigReadFunctionId,\r
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r
- Width,\r
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- } else {\r
- Return = EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigReadFunctionId,\r
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r
- Width,\r
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- }\r
-\r
- return (UINT32) Return.r9;\r
-}\r
-\r
-/**\r
- Internal worker function to writes a PCI configuration register.\r
-\r
- This function wraps EsalPciConfigWrite function of Extended SAL PCI\r
- Services Class.\r
- It writes the PCI configuration register specified by Address with the\r
- value specified by Data. The width of data is specified by Width.\r
- Data is returned.\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Width Width of data to write\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-DxePciSegmentLibEsalWriteWorker (\r
- IN UINT64 Address,\r
- IN UINTN Width,\r
- IN UINT32 Data\r
- )\r
-{\r
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r
- EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigWriteFunctionId,\r
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r
- Width,\r
- Data,\r
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- } else {\r
- EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigWriteFunctionId,\r
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r
- Width,\r
- Data,\r
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- }\r
-\r
- return Data;\r
-}\r
-\r
-/**\r
- Reads an 8-bit PCI configuration register.\r
-\r
- Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentRead8 (\r
- IN UINT64 Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
-\r
- return (UINT8) DxePciSegmentLibEsalReadWorker (Address, 1);\r
-}\r
-\r
-/**\r
- Writes an 8-bit PCI configuration register.\r
-\r
- Writes the 8-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
-\r
- return (UINT8) DxePciSegmentLibEsalWriteWorker (Address, 1, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of an 8-bit PCI configuration register with\r
- an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise OR with another 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 8-bit register is returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 8-bit register.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- return PciSegmentWrite8 (\r
- Address,\r
- BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 16-bit PCI configuration register.\r
-\r
- Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentRead16 (\r
- IN UINT64 Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
-\r
- return (UINT16) DxePciSegmentLibEsalReadWorker (Address, 2);\r
-}\r
-\r
-/**\r
- Writes a 16-bit PCI configuration register.\r
-\r
- Writes the 16-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
-\r
- return (UINT16) DxePciSegmentLibEsalWriteWorker (Address, 2, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of a 16-bit PCI configuration register with\r
- a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise OR with another 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 16-bit register is returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- return PciSegmentWrite16 (\r
- Address,\r
- BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a 32-bit PCI configuration register.\r
-\r
- Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentRead32 (\r
- IN UINT64 Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
-\r
- return DxePciSegmentLibEsalReadWorker (Address, 4);\r
-}\r
-\r
-/**\r
- Writes a 32-bit PCI configuration register.\r
-\r
- Writes the 32-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Data\r
- )\r
-{\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
-\r
- return DxePciSegmentLibEsalWriteWorker (Address, 4, Data);\r
-}\r
-\r
-/**\r
- Performs a bitwise OR of a 32-bit PCI configuration register with\r
- a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise OR with another 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 32-bit register is returned.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 32-bit register.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise OR, and writes the result back to the bit field in the\r
- 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise OR between the read result and\r
- the value specified by AndData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- return PciSegmentWrite32 (\r
- Address,\r
- BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r
- );\r
-}\r
-\r
-/**\r
- Reads a range of PCI configuration registers into a caller supplied buffer.\r
-\r
- Reads the range of PCI configuration registers specified by StartAddress and\r
- Size into the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be read. Size is\r
- returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
- and 16-bit PCI configuration read cycles may be used at the beginning and the\r
- end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- if (Size == 0) {\r
- return Size;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Read a byte if StartAddress is byte aligned\r
- //\r
- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Read a word if StartAddress is word aligned\r
- //\r
- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Read as many double words as possible\r
- //\r
- *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Read the last remaining word if exist\r
- //\r
- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Read the last remaining byte if exist\r
- //\r
- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
-\r
-/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI\r
- configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress and\r
- Size from the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be written. Size is\r
- returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
- and the end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- if (Size == 0) {\r
- return 0;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Write a byte if StartAddress is byte aligned\r
- //\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Write a word if StartAddress is word aligned\r
- //\r
- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Write as many double words as possible\r
- //\r
- PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Write the last remaining word if exist\r
- //\r
- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Write the last remaining byte if exist\r
- //\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
# been called, to prevent touching hardware that is no longer owned by the\r
# firmware.\r
#\r
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
DESTRUCTOR = DxeRuntimeDebugLibSerialPortDestructor\r
\r
#\r
-# VALID_ARCHITECTURES = AARCH64 ARM IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = AARCH64 ARM IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-## @file\r
-# This library implements the Extended SAL Library Class for use in boot services and runtime.\r
-#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxeRuntimeExtendedSalLib\r
- MODULE_UNI_FILE = DxeRuntimeExtendedSalLib.uni\r
- FILE_GUID = AE66715B-75F5-4423-8FAD-A4AFB3C53ACF\r
- MODULE_TYPE = DXE_RUNTIME_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ExtendedSalLib|DXE_RUNTIME_DRIVER DXE_SAL_DRIVER\r
- CONSTRUCTOR = DxeRuntimeExtendedSalLibConstruct\r
- DESTRUCTOR = DxeRuntimeExtendedSalLibDeconstruct\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources.IPF]\r
- ExtendedSalLib.c\r
- Ipf/AsmExtendedSalLib.s\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- UefiBootServicesTableLib\r
- UefiRuntimeServicesTableLib\r
- DebugLib\r
-\r
-[Protocols]\r
- gEfiExtendedSalBootServiceProtocolGuid ## CONSUMES\r
-\r
-[Guids]\r
- gEfiEventVirtualAddressChangeGuid ## CONSUMES ## Event\r
-\r
-[Depex]\r
- gEfiExtendedSalBootServiceProtocolGuid\r
-\r
+++ /dev/null
-// /** @file\r
-// This library implements the Extended SAL Library Class for use in boot services and runtime.\r
-//\r
-// This library implements the Extended SAL Library Class for use in boot services and runtime.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Implements the Extended SAL Library Class for use in boot services and runtime"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "This library implements the Extended SAL Library Class for use in boot services and runtime."\r
-\r
+++ /dev/null
-/** @file\r
- This library implements the Extended SAL Library Class for use in boot services and runtime.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/ExtendedSalBootService.h>\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-#include <Guid/EventGroup.h>\r
-\r
-#include <Library/ExtendedSalLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/UefiRuntimeServicesTableLib.h>\r
-#include <Library/UefiRuntimeLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-/**\r
- Stores the virtual plabel of ESAL entrypoint.\r
-\r
- This assembly function stores the virtual plabel of ESAL entrypoint\r
- where GetEsalEntryPoint() can easily retrieve.\r
-\r
- @param EntryPoint Virtual address of ESAL entrypoint\r
- @param Gp Virtual GP of ESAL entrypoint\r
-\r
- @return r8 = EFI_SAL_SUCCESS\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-SetEsalVirtualEntryPoint (\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Gp\r
- );\r
-\r
-/**\r
- Stores the physical plabel of ESAL entrypoint.\r
-\r
- This assembly function stores the physical plabel of ESAL entrypoint\r
- where GetEsalEntryPoint() can easily retrieve.\r
-\r
- @param EntryPoint Physical address of ESAL entrypoint\r
- @param Gp Physical GP of ESAL entrypoint\r
-\r
- @return r8 = EFI_SAL_SUCCESS\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-SetEsalPhysicalEntryPoint (\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Gp\r
- );\r
-\r
-/**\r
- Retrieves plabel of ESAL entrypoint.\r
-\r
- This function retrives plabel of ESAL entrypoint stored by\r
- SetEsalPhysicalEntryPoint().\r
-\r
- @return r8 = EFI_SAL_SUCCESS\r
- r9 = Physical Plabel\r
- r10 = Virtual Plabel\r
- r11 = PSR\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-GetEsalEntryPoint (\r
- VOID\r
- );\r
-\r
-EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *mEsalBootService = NULL;\r
-EFI_PLABEL mPlabel;\r
-EFI_EVENT mEfiVirtualNotifyEvent;\r
-\r
-/**\r
- Notification function of EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE to set virtual plabel of\r
- ESAL entrypoint.\r
-\r
- This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.\r
- It converts physical plabel of ESAL entrypoint to virtual plabel and stores it where\r
- GetEsalEntryPoint() can easily retrieve.\r
-\r
- @param Event Event whose notification function is being invoked.\r
- @param Context Pointer to the notification function's context\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-ExtendedSalVirtualNotifyEvent (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- )\r
-{\r
- UINT64 PhysicalEntryPoint;\r
-\r
- PhysicalEntryPoint = mPlabel.EntryPoint;\r
-\r
- gRT->ConvertPointer (0x0, (VOID **) &mPlabel.EntryPoint);\r
-\r
- mPlabel.GP += mPlabel.EntryPoint - PhysicalEntryPoint;\r
-\r
- SetEsalVirtualEntryPoint (mPlabel.EntryPoint, mPlabel.GP);\r
-}\r
-\r
-/**\r
- Gets Extended SAL Boot Service Protocol, and initializes physical plabel of\r
- ESAL entrypoint.\r
-\r
- This function first locates Extended SAL Boot Service Protocol and caches it in global variable.\r
- Then it initializes the physical plable of ESAL entrypoint, and stores\r
- it where GetEsalEntryPoint() can easily retrieve.\r
-\r
- @retval EFI_SUCCESS Plable of ESAL entrypoint successfully stored.\r
-\r
-**/\r
-EFI_STATUS\r
-DxeSalLibInitialize (\r
- VOID\r
- )\r
-{\r
- EFI_PLABEL *Plabel;\r
- EFI_STATUS Status;\r
-\r
- //\r
- // The protocol contains a function pointer, which is an indirect procedure call.\r
- // An indirect procedure call goes through a plabel, and pointer to a function is\r
- // a pointer to a plabel. To implement indirect procedure calls that can work in\r
- // both physical and virtual mode, two plabels are required (one physical and one\r
- // virtual). So lets grap the physical PLABEL for the EsalEntryPoint and store it\r
- // away. We cache it in a module global, so we can register the vitrual version.\r
- //\r
- Status = gBS->LocateProtocol (&gEfiExtendedSalBootServiceProtocolGuid, NULL, (VOID **) &mEsalBootService);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- Plabel = (EFI_PLABEL *) (UINTN) mEsalBootService->ExtendedSalProc;\r
- mPlabel.EntryPoint = Plabel->EntryPoint;\r
- mPlabel.GP = Plabel->GP;\r
- //\r
- // Stores the physical plabel of ESAL entrypoint where GetEsalEntryPoint() can easily retrieve.\r
- //\r
- SetEsalPhysicalEntryPoint (mPlabel.EntryPoint, mPlabel.GP);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Constructor function to initializes physical plabel of ESAL entrypoint and register an event\r
- for initialization of virtual plabel of ESAL entrypoint.\r
-\r
- This is the library constructor function to call a function to initialize physical plabel of ESAL entrypoint\r
- and to register notification function for\r
- EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, which sets virtual plabel of ESAL entrypoint.\r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS Notification function successfully registered.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-DxeRuntimeExtendedSalLibConstruct (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- //\r
- // Register notify function for EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE\r
- //\r
- ASSERT (gBS != NULL);\r
-\r
- DxeSalLibInitialize ();\r
-\r
- Status = gBS->CreateEventEx (\r
- EVT_NOTIFY_SIGNAL,\r
- TPL_NOTIFY,\r
- ExtendedSalVirtualNotifyEvent,\r
- NULL,\r
- &gEfiEventVirtualAddressChangeGuid,\r
- &mEfiVirtualNotifyEvent\r
- );\r
-\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Destructor function to close the event created by the library constructor\r
-\r
- This is the library destructor function to close the event with type of\r
- EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, which is created by the library constructor.\r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS Event successfully closed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-DxeRuntimeExtendedSalLibDeconstruct (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- //\r
- // Close SetVirtualAddressMap () notify function\r
- //\r
- ASSERT (gBS != NULL);\r
- Status = gBS->CloseEvent (mEfiVirtualNotifyEvent);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Registers function of ESAL class and it's associated global.\r
-\r
- This function registers function of ESAL class, together with its associated global.\r
- It is worker function for RegisterEsalClass().\r
- It is only for boot time.\r
-\r
- @param FunctionId ID of function to register\r
- @param ClassGuidLo GUID of ESAL class, lower 64-bits\r
- @param ClassGuidHi GUID of ESAL class, upper 64-bits\r
- @param Function Function to register with ClassGuid/FunctionId pair\r
- @param ModuleGlobal Module global for the function.\r
-\r
- @return Status returned by RegisterExtendedSalProc() of Extended SAL Boot Service Protocol\r
-\r
-**/\r
-EFI_STATUS\r
-RegisterEsalFunction (\r
- IN UINT64 FunctionId,\r
- IN UINT64 ClassGuidLo,\r
- IN UINT64 ClassGuidHi,\r
- IN SAL_INTERNAL_EXTENDED_SAL_PROC Function,\r
- IN VOID *ModuleGlobal\r
- )\r
-{\r
- return mEsalBootService->RegisterExtendedSalProc (\r
- mEsalBootService,\r
- ClassGuidLo,\r
- ClassGuidHi,\r
- FunctionId,\r
- Function,\r
- ModuleGlobal\r
- );\r
-}\r
-\r
-/**\r
- Registers ESAL Class and it's associated global.\r
-\r
- This function registers one or more Extended SAL services in a given\r
- class along with the associated global context.\r
- This function is only available prior to ExitBootServices().\r
-\r
- @param ClassGuidLo GUID of function class, lower 64-bits\r
- @param ClassGuidHi GUID of function class, upper 64-bits\r
- @param ModuleGlobal Module global for the class.\r
- @param ... List of Function/FunctionId pairs, ended by NULL\r
-\r
- @retval EFI_SUCCESS The Extended SAL services were registered.\r
- @retval EFI_UNSUPPORTED This function was called after ExitBootServices().\r
- @retval EFI_OUT_OF_RESOURCES There are not enough resources available to register one or more of the specified services.\r
- @retval Other ClassGuid could not be installed onto a new handle.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RegisterEsalClass (\r
- IN CONST UINT64 ClassGuidLo,\r
- IN CONST UINT64 ClassGuidHi,\r
- IN VOID *ModuleGlobal, OPTIONAL\r
- ...\r
- )\r
-{\r
- VA_LIST Args;\r
- EFI_STATUS Status;\r
- SAL_INTERNAL_EXTENDED_SAL_PROC Function;\r
- UINT64 FunctionId;\r
- EFI_HANDLE NewHandle;\r
- EFI_GUID ClassGuid;\r
-\r
- VA_START (Args, ModuleGlobal);\r
-\r
- //\r
- // Register all functions of the class to register.\r
- //\r
- Status = EFI_SUCCESS;\r
- while (!EFI_ERROR (Status)) {\r
- Function = (SAL_INTERNAL_EXTENDED_SAL_PROC) VA_ARG (Args, SAL_INTERNAL_EXTENDED_SAL_PROC);\r
- //\r
- // NULL serves as the end mark of function list\r
- //\r
- if (Function == NULL) {\r
- break;\r
- }\r
-\r
- FunctionId = VA_ARG (Args, UINT64);\r
-\r
- Status = RegisterEsalFunction (FunctionId, ClassGuidLo, ClassGuidHi, Function, ModuleGlobal);\r
- }\r
-\r
- VA_END (Args);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- NewHandle = NULL;\r
- *((UINT64 *)(&ClassGuid) + 0) = ClassGuidLo;\r
- *((UINT64 *)(&ClassGuid) + 1) = ClassGuidHi;\r
- return gBS->InstallProtocolInterface (\r
- &NewHandle,\r
- &ClassGuid,\r
- EFI_NATIVE_INTERFACE,\r
- NULL\r
- );\r
-}\r
-\r
-/**\r
- Calls an Extended SAL Class service that was previously registered with RegisterEsalClass().\r
-\r
- This function gets the entrypoint of Extended SAL, and calls an Extended SAL Class service\r
- that was previously registered with RegisterEsalClass() through this entrypoint.\r
-\r
- @param ClassGuidLo GUID of function, lower 64-bits\r
- @param ClassGuidHi GUID of function, upper 64-bits\r
- @param FunctionId Function in ClassGuid to call\r
- @param Arg2 Argument 2 ClassGuid/FunctionId defined\r
- @param Arg3 Argument 3 ClassGuid/FunctionId defined\r
- @param Arg4 Argument 4 ClassGuid/FunctionId defined\r
- @param Arg5 Argument 5 ClassGuid/FunctionId defined\r
- @param Arg6 Argument 6 ClassGuid/FunctionId defined\r
- @param Arg7 Argument 7 ClassGuid/FunctionId defined\r
- @param Arg8 Argument 8 ClassGuid/FunctionId defined\r
-\r
- @retval EFI_SAL_SUCCESS ESAL procedure successfully called.\r
- @retval EFI_SAL_ERROR The address of ExtendedSalProc() can not be correctly\r
- initialized.\r
- @retval Other Status returned from ExtendedSalProc() service of\r
- EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalCall (\r
- IN UINT64 ClassGuidLo,\r
- IN UINT64 ClassGuidHi,\r
- IN UINT64 FunctionId,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4,\r
- IN UINT64 Arg5,\r
- IN UINT64 Arg6,\r
- IN UINT64 Arg7,\r
- IN UINT64 Arg8\r
- )\r
-{\r
- SAL_RETURN_REGS ReturnReg;\r
- EXTENDED_SAL_PROC EsalProc;\r
-\r
- //\r
- // Get the entrypoint of Extended SAL\r
- //\r
- ReturnReg = GetEsalEntryPoint ();\r
- if (*(UINT64 *)ReturnReg.r9 == 0 && *(UINT64 *)(ReturnReg.r9 + 8) == 0) {\r
- //\r
- // The ESAL Entry Point could not be initialized\r
- //\r
- ReturnReg.Status = EFI_SAL_ERROR;\r
- return ReturnReg;\r
- }\r
-\r
- //\r
- // Test PSR.it which is BIT36\r
- //\r
- if ((ReturnReg.r11 & BIT36) != 0) {\r
- //\r
- // Virtual mode plabel to entry point\r
- //\r
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r10;\r
- } else {\r
- //\r
- // Physical mode plabel to entry point\r
- //\r
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r9;\r
- }\r
-\r
- return EsalProc (\r
- ClassGuidLo,\r
- ClassGuidHi,\r
- FunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalStallFunctionId service of Extended SAL Stall Services Class.\r
-\r
- This function is a wrapper for the EsalStallFunctionId service of Extended SAL\r
- Stall Services Class. See EsalStallFunctionId of Extended SAL Specification.\r
-\r
- @param Microseconds The number of microseconds to delay.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.\r
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalStall (\r
- IN UINTN Microseconds\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,\r
- StallFunctionId,\r
- Microseconds,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.\r
-\r
- This function is a wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL\r
- PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extended SAL Specification.\r
-\r
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.\r
- If FALSE, then PalEntryPoint is a virtual address.\r
- @param PalEntryPoint The PAL Entry Point being set.\r
-\r
- @retval EFI_SAL_SUCCESS The PAL Entry Point was set.\r
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before\r
- virtual mappings for the specified Extended SAL\r
- Procedure are available.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalSetNewPalEntry (\r
- IN BOOLEAN PhysicalAddress,\r
- IN UINT64 PalEntryPoint\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,\r
- SetNewPalEntryFunctionId,\r
- PhysicalAddress,\r
- PalEntryPoint,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.\r
-\r
- This function is a wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL\r
- PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extended SAL Specification.\r
-\r
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.\r
- If FALSE, then PalEntryPoint is a virtual address.\r
-\r
- @retval EFI_SAL_SUCCESS The PAL Entry Point was retrieved and returned in\r
- SAL_RETURN_REGS.r9.\r
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before\r
- virtual mappings for the specified Extended SAL\r
- Procedure are available.\r
- @return r9 PAL entry point retrieved.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetNewPalEntry (\r
- IN BOOLEAN PhysicalAddress\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,\r
- GetNewPalEntryFunctionId,\r
- PhysicalAddress,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL MCA Log Services Class.\r
-\r
- This function is a wrapper for the EsalGetStateBufferFunctionId service of Extended SAL\r
- MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL Specification.\r
-\r
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.\r
- @param McaBuffer A pointer to the base address of the returned buffer.\r
- Copied from SAL_RETURN_REGS.r9.\r
- @param BufferSize A pointer to the size, in bytes, of the returned buffer.\r
- Copied from SAL_RETURN_REGS.r10.\r
-\r
- @retval EFI_SAL_SUCCESS The memory buffer to store error records was returned in r9 and r10.\r
- @retval EFI_OUT_OF_RESOURCES A memory buffer for string error records in not available\r
- @return r9 Base address of the returned buffer\r
- @return r10 Size of the returned buffer in bytes\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetStateBuffer (\r
- IN UINT64 McaType,\r
- OUT UINT8 **McaBuffer,\r
- OUT UINTN *BufferSize\r
- )\r
-{\r
- SAL_RETURN_REGS Regs;\r
-\r
- Regs = EsalCall (\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,\r
- EsalGetStateBufferFunctionId,\r
- McaType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-\r
- *McaBuffer = (UINT8 *) Regs.r9;\r
- *BufferSize = Regs.r10;\r
-\r
- return Regs;\r
-}\r
-\r
-/**\r
- Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL MCA Log Services Class.\r
-\r
- This function is a wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL\r
- MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SAL Specification.\r
-\r
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.\r
-\r
- @retval EFI_SUCCESS The memory buffer containing the error record was written to nonvolatile storage.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalSaveStateBuffer (\r
- IN UINT64 McaType\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,\r
- EsalSaveStateBufferFunctionId,\r
- McaType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalGetVectorsFunctionId service of Extended SAL\r
- Base Services Class. See EsalGetVectorsFunctionId of Extended SAL Specification.\r
-\r
- @param VectorType The vector type to retrieve.\r
- 0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.\r
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered\r
- with the SAL Procedure SAL_SET_VECTORS.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetVectors (\r
- IN UINT64 VectorType\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalGetVectorsFunctionId,\r
- VectorType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL\r
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.\r
-\r
- @param ParamInfoType The parameter type to retrieve.\r
- 1 - rendezvous interrupt\r
- 2 - wake up\r
- 3 - Corrected Platform Error Vector.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.\r
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered\r
- with the SAL Procedure SAL_MC_SET_PARAMS.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcGetParams (\r
- IN UINT64 ParamInfoType\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalMcGetParamsFunctionId,\r
- ParamInfoType,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL\r
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.\r
-\r
- @retval EFI_SAL_SUCCESS Call completed without error.\r
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered\r
- with the SAL Procedure SAL_MC_SET_PARAMS.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcGetMcParams (\r
- VOID\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalMcGetMcParamsFunctionId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL Base Services Class.\r
-\r
- This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL\r
- Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL Specification.\r
-\r
- @param CpuIndex The index of the CPU of set of enabled CPUs to check.\r
-\r
- @retval EFI_SAL_SUCCESS The checkin status of the requested CPU was returned.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetMcCheckinFlags (\r
- IN UINT64 CpuIndex\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalGetMcCheckinFlagsFunctionId,\r
- CpuIndex,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalAddCpuDataFunctionId service of Extended SAL\r
- MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being added.\r
- @param Enabled The enable flag for the CPU being added.\r
- TRUE means the CPU is enabled.\r
- FALSE means the CPU is disabled.\r
- @param PalCompatibility The PAL Compatibility value for the CPU being added.\r
-\r
- @retval EFI_SAL_SUCCESS The CPU was added to the database.\r
- @retval EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource available to add the CPU.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalAddCpuData (\r
- IN UINT64 CpuGlobalId,\r
- IN BOOLEAN Enabled,\r
- IN UINT64 PalCompatibility\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- AddCpuDataFunctionId,\r
- CpuGlobalId,\r
- Enabled,\r
- PalCompatibility,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL\r
- MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being removed.\r
-\r
- @retval EFI_SAL_SUCCESS The CPU was removed from the database.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalRemoveCpuData (\r
- IN UINT64 CpuGlobalId\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- RemoveCpuDataFunctionId,\r
- CpuGlobalId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL\r
- MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being modified.\r
- @param Enabled The enable flag for the CPU being modified.\r
- TRUE means the CPU is enabled.\r
- FALSE means the CPU is disabled.\r
- @param PalCompatibility The PAL Compatibility value for the CPU being modified.\r
-\r
- @retval EFI_SAL_SUCCESS The CPU database was updated.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalModifyCpuData (\r
- IN UINT64 CpuGlobalId,\r
- IN BOOLEAN Enabled,\r
- IN UINT64 PalCompatibility\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- ModifyCpuDataFunctionId,\r
- CpuGlobalId,\r
- Enabled,\r
- PalCompatibility,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL\r
- MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU being looked up.\r
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.\r
- If FALSE, then the index of set of all CPUs of database is returned.\r
-\r
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetCpuDataById (\r
- IN UINT64 CpuGlobalId,\r
- IN BOOLEAN IndexByEnabledCpu\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- GetCpuDataByIDFunctionId,\r
- CpuGlobalId,\r
- IndexByEnabledCpu,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL\r
- MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL Specification.\r
-\r
- @param Index The Global ID for the CPU being modified.\r
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.\r
- If FALSE, then the index of set of all CPUs of database is returned.\r
-\r
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetCpuDataByIndex (\r
- IN UINT64 Index,\r
- IN BOOLEAN IndexByEnabledCpu\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- GetCpuDataByIndexFunctionId,\r
- Index,\r
- IndexByEnabledCpu,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalWhoAmIFunctionId service of Extended SAL\r
- MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specification.\r
-\r
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.\r
- If FALSE, then the index of set of all CPUs of database is returned.\r
-\r
- @retval EFI_SAL_SUCCESS The Global ID for the calling CPU was returned.\r
- @retval EFI_SAL_NO_INFORMATION The calling CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalWhoAmI (\r
- IN BOOLEAN IndexByEnabledCpu\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- CurrentProcInfoFunctionId,\r
- IndexByEnabledCpu,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalNumProcessors service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalNumProcessors service of Extended SAL\r
- MP Services Class. See EsalNumProcessors of Extended SAL Specification.\r
-\r
- @retval EFI_SAL_SUCCESS The information on the number of CPUs in the platform\r
- was returned.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalNumProcessors (\r
- VOID\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- NumProcessorsFunctionId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalSetMinStateFnctionId service of Extended SAL\r
- MP Services Class. See EsalSetMinStateFnctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being set.\r
- @param MinStatePointer The physical address of the MINSTATE buffer for the CPU\r
- specified by CpuGlobalId.\r
-\r
- @retval EFI_SAL_SUCCESS The MINSTATE pointer was set for the specified CPU.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalSetMinState (\r
- IN UINT64 CpuGlobalId,\r
- IN EFI_PHYSICAL_ADDRESS MinStatePointer\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- SetMinStateFunctionId,\r
- CpuGlobalId,\r
- MinStatePointer,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP Services Class.\r
-\r
- This function is a wrapper for the EsalGetMinStateFunctionId service of Extended SAL\r
- MP Services Class. See EsalGetMinStateFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being retrieved.\r
-\r
- @retval EFI_SAL_SUCCESS The MINSTATE pointer for the specified CPU was retrieved.\r
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalGetMinState (\r
- IN UINT64 CpuGlobalId\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,\r
- GetMinStateFunctionId,\r
- CpuGlobalId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL MCA Services Class.\r
-\r
- This function is a wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL\r
- MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being retrieved.\r
- @param StateBufferPointer A pointer to the returned MCA state buffer.\r
- @param RequiredStateBufferSize A pointer to the size, in bytes, of the returned MCA state buffer.\r
-\r
- @retval EFI_SUCCESS MINSTATE successfully got and size calculated.\r
- @retval EFI_SAL_NO_INFORMATION Fail to get MINSTATE.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcaGetStateInfo (\r
- IN UINT64 CpuGlobalId,\r
- OUT EFI_PHYSICAL_ADDRESS *StateBufferPointer,\r
- OUT UINT64 *RequiredStateBufferSize\r
- )\r
-{\r
- SAL_RETURN_REGS Regs;\r
-\r
- Regs = EsalCall (\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,\r
- McaGetStateInfoFunctionId,\r
- CpuGlobalId,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-\r
- *StateBufferPointer = (EFI_PHYSICAL_ADDRESS) Regs.r9;\r
- *RequiredStateBufferSize = (UINT64) Regs.r10;\r
-\r
- return Regs;\r
-}\r
-\r
-/**\r
- Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL MCA Services Class.\r
-\r
- This function is a wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL\r
- MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL Specification.\r
-\r
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being set.\r
- @param StateBufferPointer A pointer to the MCA state buffer.\r
-\r
- @retval EFI_SAL_NO_INFORMATION Cannot get the processor info with the CpuId\r
- @retval EFI_SUCCESS Save the processor's state info successfully\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-EsalMcaRegisterCpu (\r
- IN UINT64 CpuGlobalId,\r
- IN EFI_PHYSICAL_ADDRESS StateBufferPointer\r
- )\r
-{\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,\r
- McaRegisterCpuFunctionId,\r
- CpuGlobalId,\r
- StateBufferPointer,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
-}\r
+++ /dev/null
-/// @file\r
-/// Assembly procedures to get and set ESAL entry point.\r
-///\r
-/// Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
-/// This program and the accompanying materials\r
-/// are licensed and made available under the terms and conditions of the BSD License\r
-/// which accompanies this distribution. The full text of the license may be found at\r
-/// http://opensource.org/licenses/bsd-license.php.\r
-///\r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-///\r
-\r
-.auto\r
-.text\r
-\r
-#include "IpfMacro.i"\r
-\r
-//\r
-// Exports\r
-//\r
-ASM_GLOBAL GetEsalEntryPoint\r
-\r
-//-----------------------------------------------------------------------------\r
-//++\r
-// GetEsalEntryPoint\r
-//\r
-// Return Esal global and PSR register.\r
-//\r
-// On Entry :\r
-//\r
-//\r
-// Return Value:\r
-// r8 = EFI_SAL_SUCCESS\r
-// r9 = Physical Plabel\r
-// r10 = Virtual Plabel\r
-// r11 = psr\r
-// \r
-// As per static calling conventions. \r
-// \r
-//--\r
-//---------------------------------------------------------------------------\r
-PROCEDURE_ENTRY (GetEsalEntryPoint)\r
-\r
- NESTED_SETUP (0,8,0,0)\r
-\r
-EsalCalcStart:\r
- mov r8 = ip;;\r
- add r8 = (EsalEntryPoint - EsalCalcStart), r8;;\r
- mov r9 = r8;;\r
- add r10 = 0x10, r8;;\r
- mov r11 = psr;;\r
- mov r8 = r0;;\r
-\r
- NESTED_RETURN\r
-\r
-PROCEDURE_EXIT (GetEsalEntryPoint)\r
-\r
-//-----------------------------------------------------------------------------\r
-//++\r
-// SetEsalPhysicalEntryPoint\r
-//\r
-// Set the dispatcher entry point\r
-//\r
-// On Entry:\r
-// in0 = Physical address of Esal Dispatcher\r
-// in1 = Physical GP\r
-//\r
-// Return Value: \r
-// r8 = EFI_SAL_SUCCESS\r
-// \r
-// As per static calling conventions. \r
-// \r
-//--\r
-//---------------------------------------------------------------------------\r
-PROCEDURE_ENTRY (SetEsalPhysicalEntryPoint)\r
-\r
- NESTED_SETUP (2,8,0,0)\r
-\r
-EsalCalcStart1:\r
- mov r8 = ip;;\r
- add r8 = (EsalEntryPoint - EsalCalcStart1), r8;;\r
- st8 [r8] = in0;;\r
- add r8 = 0x08, r8;;\r
- st8 [r8] = in1;;\r
- mov r8 = r0;;\r
-\r
- NESTED_RETURN\r
-\r
-PROCEDURE_EXIT (SetEsalPhysicalEntryPoint)\r
-\r
-//-----------------------------------------------------------------------------\r
-//++\r
-// SetEsalVirtualEntryPoint\r
-//\r
-// Register physical address of Esal globals.\r
-//\r
-// On Entry :\r
-// in0 = Virtual address of Esal Dispatcher\r
-// in1 = Virtual GP\r
-//\r
-// Return Value: \r
-// r8 = EFI_SAL_ERROR\r
-// \r
-// As per static calling conventions. \r
-// \r
-//--\r
-//---------------------------------------------------------------------------\r
-PROCEDURE_ENTRY (SetEsalVirtualEntryPoint)\r
-\r
- NESTED_SETUP (2,8,0,0)\r
-\r
-EsalCalcStart2:\r
- mov r8 = ip;;\r
- add r8 = (EsalEntryPoint - EsalCalcStart2), r8;;\r
- add r8 = 0x10, r8;;\r
- st8 [r8] = in0;;\r
- add r8 = 0x08, r8;;\r
- st8 [r8] = in1;;\r
- mov r8 = r0;;\r
-\r
- NESTED_RETURN\r
-\r
-PROCEDURE_EXIT (SetEsalVirtualEntryPoint)\r
-\r
-.align 32\r
-EsalEntryPoint: \r
- data8 0 // Physical Entry\r
- data8 0 // GP\r
- data8 0 // Virtual Entry\r
- data8 0 // GP\r
DESTRUCTOR = DxeRuntimePciExpressLibDestructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-/** @file\r
- This library implements the SAL Library Class using Extended SAL functions\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-\r
-#include <Library/SalLib.h>\r
-#include <Library/ExtendedSalLib.h>\r
-\r
-/**\r
- Makes a SAL procedure call.\r
-\r
- This is a wrapper function to make a SAL procedure call.\r
- No parameter checking is performed on the 8 input parameters,\r
- but there are some common rules that the caller should follow\r
- when making a SAL call. Any address passed to SAL as buffers\r
- for return parameters must be 8-byte aligned. Unaligned\r
- addresses may cause undefined results. For those parameters\r
- defined as reserved or some fields defined as reserved must be\r
- zero filled or the invalid argument return value may be returned\r
- or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
-\r
- @param Index The SAL procedure Index number\r
- @param Arg2 The 2nd parameter for SAL procedure calls\r
- @param Arg3 The 3rd parameter for SAL procedure calls\r
- @param Arg4 The 4th parameter for SAL procedure calls\r
- @param Arg5 The 5th parameter for SAL procedure calls\r
- @param Arg6 The 6th parameter for SAL procedure calls\r
- @param Arg7 The 7th parameter for SAL procedure calls\r
- @param Arg8 The 8th parameter for SAL procedure calls\r
-\r
- @return SAL returned registers.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-SalCall (\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4,\r
- IN UINT64 Arg5,\r
- IN UINT64 Arg6,\r
- IN UINT64 Arg7,\r
- IN UINT64 Arg8\r
- )\r
-{\r
- SAL_RETURN_REGS Regs;\r
-\r
- //\r
- // Initial all members in this structure.\r
- //\r
- Regs.r9 = 0;\r
- Regs.r10 = 0;\r
- Regs.r11 = 0;\r
- Regs.Status = EFI_SAL_INVALID_ARGUMENT;\r
-\r
- switch (Index) {\r
- case EFI_SAL_SET_VECTORS:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- SalSetVectorsFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_GET_STATE_INFO:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,\r
- SalGetStateInfoFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_GET_STATE_INFO_SIZE:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,\r
- SalGetStateInfoSizeFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_CLEAR_STATE_INFO:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,\r
- SalClearStateInfoFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_MC_RENDEZ:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- SalMcRendezFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_MC_SET_PARAMS:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- SalMcSetParamsFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_REGISTER_PHYSICAL_ADDR:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalRegisterPhysicalAddrFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_CACHE_FLUSH:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI,\r
- SalCacheFlushFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_CACHE_INIT:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI,\r
- SalCacheInitFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_PCI_CONFIG_READ:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigReadFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_PCI_CONFIG_WRITE:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r
- SalPciConfigWriteFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_FREQ_BASE:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalGetPlatformBaseFreqFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_PHYSICAL_ID_INFO:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,\r
- EsalPhysicalIdInfoFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- case EFI_SAL_UPDATE_PAL:\r
- return EsalCall (\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,\r
- EsalUpdatePalFunctionId,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
- break;\r
-\r
- default:\r
- return Regs;\r
- break;\r
- }\r
-}\r
+++ /dev/null
-## @file\r
-# This library implements the SAL Library Class using Extended SAL functions\r
-#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxeSalLibEsal\r
- MODULE_UNI_FILE = DxeSalLibEsal.uni\r
- FILE_GUID = 2B73B074-2E67-498b-82AC-CE38FB770FFC\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = SalLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources.IPF]\r
- DxeSalLibEsal.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- ExtendedSalLib\r
-\r
+++ /dev/null
-// /** @file\r
-// This library implements the SAL Library Class using Extended SAL functions\r
-//\r
-// This library implements the SAL Library Class using Extended SAL functions.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Implements the SAL Library Class using Extended SAL functions"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "This library implements the SAL Library Class using Extended SAL functions."\r
-\r
FILE_GUID = EE680C58-FFC0-4a5d-858F-66FF9C84BC9F\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64\r
#\r
\r
[Sources]\r
DxeServicesLib.c\r
\r
-[Sources.IA32, Sources.IPF, Sources.EBC, Sources.ARM, Sources.AARCH64]\r
+[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64]\r
Allocate.c\r
\r
[Sources.X64]\r
# DXE Services Table Library that retrieves a pointer to the DXE Services\r
# Table from the Configuration Table in the EFI System Table.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = baa1baa3-0a8d-402c-8042-985115fae953\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DxeServicesTableLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
+ LIBRARY_CLASS = DxeServicesTableLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
\r
CONSTRUCTOR = DxeServicesTableLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
## @file\r
# SMBUS Library that layers on top of the SMBUS Protocol.\r
#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 4F369FB1-31A7-423c-960E-B3EFD337894F\r
MODULE_TYPE = DXE_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = SmbusLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = SmbusLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
CONSTRUCTOR = SmbusLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-/** @file\r
- This library implements the Timer Library using the Extended SAL Stall Services Class.\r
-\r
- Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/ExtendedSalServiceClasses.h>\r
-\r
-#include <Library/TimerLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/ExtendedSalLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PalLib.h>\r
-\r
-/**\r
- Stalls the CPU for at least the given number of microseconds.\r
-\r
- This function wraps EsalStall function of Extended SAL Stall Services Class.\r
- It stalls the CPU for the number of microseconds specified by MicroSeconds.\r
-\r
- @param MicroSeconds The minimum number of microseconds to delay.\r
-\r
- @return MicroSeconds\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-MicroSecondDelay (\r
- IN UINTN MicroSeconds\r
- )\r
-{\r
- EsalCall (\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,\r
- StallFunctionId,\r
- MicroSeconds,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- return MicroSeconds;\r
-}\r
-\r
-/**\r
- Stalls the CPU for at least the given number of nanoseconds.\r
-\r
- This function wraps EsalStall function of Extended SAL Stall Services Class.\r
- It stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r
-\r
- @param NanoSeconds The minimum number of nanoseconds to delay.\r
-\r
- @return NanoSeconds\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-NanoSecondDelay (\r
- IN UINTN NanoSeconds\r
- )\r
-{\r
- UINT64 MicroSeconds;\r
-\r
- //\r
- // The unit of ESAL Stall service is microsecond, so we turn the time interval\r
- // from nanosecond to microsecond, using the ceiling value to ensure stalling\r
- // at least the given number of nanoseconds.\r
- //\r
- MicroSeconds = DivU64x32 (NanoSeconds + 999, 1000);\r
- EsalCall (\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,\r
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,\r
- StallFunctionId,\r
- MicroSeconds,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0,\r
- 0\r
- );\r
- return NanoSeconds;\r
-}\r
-\r
-/**\r
- Retrieves the current value of a 64-bit free running performance counter.\r
-\r
- Retrieves the current value of a 64-bit free running performance counter. The\r
- counter can either count up by 1 or count down by 1. If the physical\r
- performance counter counts by a larger increment, then the counter values\r
- must be translated. The properties of the counter can be retrieved from\r
- GetPerformanceCounterProperties().\r
-\r
- @return The current value of the free running performance counter.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-GetPerformanceCounter (\r
- VOID\r
- )\r
-{\r
- return AsmReadItc ();\r
-}\r
-\r
-/**\r
- Retrieves the 64-bit frequency in Hz and the range of performance counter\r
- values.\r
-\r
- If StartValue is not NULL, then the value that the performance counter starts\r
- with immediately after is it rolls over is returned in StartValue. If\r
- EndValue is not NULL, then the value that the performance counter end with\r
- immediately before it rolls over is returned in EndValue. The 64-bit\r
- frequency of the performance counter in Hz is always returned. If StartValue\r
- is less than EndValue, then the performance counter counts up. If StartValue\r
- is greater than EndValue, then the performance counter counts down. For\r
- example, a 64-bit free running counter that counts up would have a StartValue\r
- of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r
- that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r
-\r
- @param StartValue The value the performance counter starts with when it\r
- rolls over.\r
- @param EndValue The value that the performance counter ends with before\r
- it rolls over.\r
-\r
- @return The frequency in Hz.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-GetPerformanceCounterProperties (\r
- OUT UINT64 *StartValue, OPTIONAL\r
- OUT UINT64 *EndValue OPTIONAL\r
- )\r
-{\r
- PAL_CALL_RETURN PalRet;\r
- UINT64 BaseFrequence;\r
-\r
- //\r
- // Get processor base frequency\r
- //\r
- PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);\r
- ASSERT (PalRet.Status == 0);\r
- BaseFrequence = PalRet.r9;\r
-\r
- //\r
- // Get processor frequency ratio\r
- //\r
- PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);\r
- ASSERT (PalRet.Status == 0);\r
-\r
- //\r
- // Start value of counter is 0\r
- //\r
- if (StartValue != NULL) {\r
- *StartValue = 0;\r
- }\r
-\r
- //\r
- // End value of counter is 0xFFFFFFFFFFFFFFFF\r
- //\r
- if (EndValue != NULL) {\r
- *EndValue = (UINT64)(-1);\r
- }\r
-\r
- return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;\r
-}\r
-\r
-/**\r
- Converts elapsed ticks of performance counter to time in nanoseconds.\r
-\r
- This function converts the elapsed ticks of running performance counter to\r
- time value in unit of nanoseconds.\r
-\r
- @param Ticks The number of elapsed ticks of running performance counter.\r
-\r
- @return The elapsed time in nanoseconds.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-GetTimeInNanoSecond (\r
- IN UINT64 Ticks\r
- )\r
-{\r
- UINT64 Frequency;\r
- UINT64 NanoSeconds;\r
- UINT64 Remainder;\r
- INTN Shift;\r
-\r
- Frequency = GetPerformanceCounterProperties (NULL, NULL);\r
-\r
- //\r
- // Ticks\r
- // Time = --------- x 1,000,000,000\r
- // Frequency\r
- //\r
- NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r
-\r
- //\r
- // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r
- // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
- // i.e. highest bit set in Remainder should <= 33.\r
- //\r
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
- NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
-\r
- return NanoSeconds;\r
-}\r
+++ /dev/null
-## @file\r
-# This library implements the Timer Library using the Extended SAL Stall Services Class.\r
-#\r
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = DxeTimerLibEsal\r
- MODULE_UNI_FILE = DxeTimerLibEsal.uni\r
- FILE_GUID = F672AE85-3769-4fb8-A5A0-70B38FB0A7C4\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = TimerLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- DxeTimerLibEsal.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- DebugLib\r
- ExtendedSalLib\r
- BaseLib\r
- PalLib\r
-\r
+++ /dev/null
-// /** @file\r
-// This library implements the Timer Library using the Extended SAL Stall Services Class.\r
-//\r
-// This library implements the Timer Library using the Extended SAL Stall Services Class.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Implements the Timer Library using the Extended SAL Stall Services Class"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "This library implements the Timer Library using the Extended SAL Stall Services Class."\r
-\r
# PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to\r
# support multi-segment PCI configuration access through enhanced configuration access mechanism.\r
#\r
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to\r
# support multi-segment PCI configuration access through enhanced configuration access mechanism.\r
#\r
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
## @file\r
# Module entry point library for PEI core.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
LIBRARY_CLASS = PeiCoreEntryPoint|PEI_CORE\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
#\r
# Post Code Library that layers on top of a Report Status Code Library instance.\r
#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = e062c52d-78dc-4cc5-b246-b13497a8123c\r
MODULE_TYPE = PEIM\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PostCodeLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER PEIM PEI_CORE UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = PostCodeLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER PEIM PEI_CORE UEFI_APPLICATION UEFI_DRIVER\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
#\r
# This library provides generic extract guided section functions for PEIM and PEI_CORE module.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
# Memory Allocation Library that uses PEI Services to allocate memory.\r
# Free operations are ignored.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
# Base Memory Library implementation that uses PEI Services\r
# where possible for size reduction.\r
#\r
-# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
+++ /dev/null
-/** @file\r
- PAL Call Services Function.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-\r
-#include <PiPei.h>\r
-\r
-#include <Ppi/SecPlatformInformation.h>\r
-\r
-#include <Library/PalLib.h>\r
-#include <Library/PeiServicesTablePointerLib.h>\r
-#include <Library/PeiServicesLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-/**\r
- Makes a PAL procedure call.\r
-\r
- This is a wrapper function to make a PAL procedure call. Based on the Index value,\r
- this API will make static or stacked PAL call. Architected procedures may be designated\r
- as required or optional. If a PAL procedure is specified as optional, a unique return\r
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.\r
- This indicates that the procedure is not present in this PAL implementation. It is the\r
- caller's responsibility to check for this return code after calling any optional PAL\r
- procedure. No parameter checking is performed on the 4 input parameters, but there are\r
- some common rules that the caller should follow when making a PAL call. Any address\r
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses\r
- may cause undefined results. For those parameters defined as reserved or some fields\r
- defined as reserved must be zero filled or the invalid argument return value may be\r
- returned or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
-\r
- @param Index The PAL procedure Index number.\r
- @param Arg2 The 2nd parameter for PAL procedure calls.\r
- @param Arg3 The 3rd parameter for PAL procedure calls.\r
- @param Arg4 The 4th parameter for PAL procedure calls.\r
-\r
- @return Structure returned from the PAL Call procedure, including the status and return value.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-EFIAPI\r
-PalCall (\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- )\r
-{\r
- UINT64 PalCallAddress;\r
- PAL_CALL_RETURN ReturnVal;\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_STATUS Status;\r
- EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformPpi;\r
- EFI_SEC_PLATFORM_INFORMATION_RECORD SecPlatformInfoRecord;\r
- UINT64 RecordSize;\r
-\r
- //\r
- // Get PEI Service Table Pointer\r
- //\r
- PeiServices = GetPeiServicesTablePointer ();\r
-\r
- //\r
- // Locate SEC Platform Information PPI\r
- //\r
- Status = PeiServicesLocatePpi (\r
- &gEfiSecPlatformInformationPpiGuid,\r
- 0,\r
- NULL,\r
- (VOID **)&SecPlatformPpi\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Retrieve PAL call address from platform information reported by the PPI\r
- //\r
- RecordSize = sizeof (SecPlatformInfoRecord);\r
- SecPlatformPpi->PlatformInformation (\r
- PeiServices,\r
- &RecordSize,\r
- &SecPlatformInfoRecord\r
- );\r
- PalCallAddress = SecPlatformInfoRecord.ItaniumHealthFlags.PalCallAddress;\r
-\r
- ReturnVal = AsmPalCall (PalCallAddress, Index, Arg2, Arg3, Arg4);\r
-\r
- return ReturnVal;\r
-}\r
-\r
+++ /dev/null
-## @file\r
-# Instance of PAL Library using a PPI for PAL entrypoint.\r
-#\r
-# Instance of PAL Library that uses a PPI to retrieve the PAL\r
-# Entry Point and layers on top of AsmPalCall() in the Base Library\r
-#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PeiPalLib\r
- MODULE_UNI_FILE = PeiPalLib.uni\r
- FILE_GUID = B53DC524-6B98-4584-940B-8F1363DEF09E\r
- MODULE_TYPE = PEIM\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PalLib|PEIM SEC PEI_CORE\r
-\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- PeiPalLib.c\r
-\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- PeiServicesLib\r
- PeiServicesTablePointerLib\r
-\r
-\r
-[Ppis]\r
- gEfiSecPlatformInformationPpiGuid ## CONSUMES\r
-\r
+++ /dev/null
-// /** @file\r
-// Instance of PAL Library using a PPI for PAL entrypoint.\r
-//\r
-// Instance of PAL Library that uses a PPI to retrieve the PAL\r
-// Entry Point and layers on top of AsmPalCall() in the Base Library\r
-//\r
-// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Instance of PAL Library using a PPI for PAL entry point"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "Instance of PAL Library that uses a PPI to retrieve the PAL Entry Point and layers on top of AsmPalCall() in the Base Library."\r
-\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
# the first PPI found, so this library instance should only be used platforms\r
# with a single PCI segment.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
# EFI_PEI_PCI CFG2 PPIs are typically produced by a chipset specific PEIM.\r
# This library instance should only be used platforms with multiple PCI segments.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
#\r
# Resource Publication Library that uses PEI Services to publish system memory.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
PI_SPECIFICATION_VERSION = 0x0001000A\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
# PEI Services Table from a global variable. Not available to modules that execute from\r
# read-only memory.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
CONSTRUCTOR = PeiServicesTablePointerLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
+++ /dev/null
-/** @file\r
- PEI Services Table Pointer Library implementation for IPF that uses Kernel\r
- Register 7 to store the pointer.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiPei.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-/**\r
- Retrieves the cached value of the PEI Services Table pointer.\r
-\r
- Returns the cached value of the PEI Services Table pointer in a CPU specific manner\r
- as specified in the CPU binding section of the Platform Initialization Pre-EFI\r
- Initialization Core Interface Specification.\r
-\r
- If the cached PEI Services Table pointer is NULL, then ASSERT().\r
-\r
- @return The pointer to PeiServices.\r
-\r
-**/\r
-CONST EFI_PEI_SERVICES **\r
-EFIAPI\r
-GetPeiServicesTablePointer (\r
- VOID\r
- )\r
-{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
-\r
- PeiServices = (CONST EFI_PEI_SERVICES **)(UINTN)AsmReadKr7 ();\r
- ASSERT (PeiServices != NULL);\r
- return PeiServices;\r
-}\r
-\r
-\r
-/**\r
- Caches a pointer PEI Services Table.\r
-\r
- Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer\r
- in a CPU specific manner as specified in the CPU binding section of the Platform Initialization\r
- Pre-EFI Initialization Core Interface Specification.\r
- The function set the pointer of PEI services in KR7 register\r
- according to PI specification.\r
-\r
- If PeiServicesTablePointer is NULL, then ASSERT().\r
-\r
- @param PeiServicesTablePointer The address of PeiServices pointer.\r
-**/\r
-VOID\r
-EFIAPI\r
-SetPeiServicesTablePointer (\r
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
- )\r
-{\r
- ASSERT (PeiServicesTablePointer != NULL);\r
- AsmWriteKr7 ((UINT64)(UINTN)PeiServicesTablePointer);\r
-}\r
-\r
-/**\r
- Perform CPU specific actions required to migrate the PEI Services Table\r
- pointer from temporary RAM to permanent RAM.\r
-\r
- For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes\r
- immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
- For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes\r
- immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
- For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in\r
- a dedicated CPU register. This means that there is no memory storage\r
- associated with storing the PEI Services Table pointer, so no additional\r
- migration actions are required for Itanium or ARM CPUs.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-MigratePeiServicesTablePointer (\r
- VOID\r
- )\r
-{\r
- return;\r
-}\r
-\r
+++ /dev/null
-## @file\r
-# Instance of PEI Services Table Pointer Library using KR7 for the table pointer.\r
-#\r
-# PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI\r
-# Services Table from KR7 on IPF.\r
-#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PeiServicesTablePointerLibKr7\r
- MODULE_UNI_FILE = PeiServicesTablePointerLibKr7.uni\r
- FILE_GUID = E0E7D776-E7EB-4e5f-9AA8-54CF3AA64A43\r
- MODULE_TYPE = PEIM\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PeiServicesTablePointerLib|SEC PEIM PEI_CORE\r
-\r
-\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources.Ipf]\r
- PeiServicesTablePointer.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- DebugLib\r
- BaseLib\r
-\r
+++ /dev/null
-// /** @file\r
-// Instance of PEI Services Table Pointer Library using KR7 for the table pointer.\r
-//\r
-// PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI\r
-// Services Table from KR7 on IPF.\r
-//\r
-// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using KR7 for the table pointer"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from KR7 on IPF."\r
-\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
LIBRARY_CLASS = PeimEntryPoint|PEIM\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)\r
#\r
\r
[Sources]\r
+++ /dev/null
-/** @file\r
- Timer Library functions built upon ITC on IPF.\r
-\r
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/TimerLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/PalLib.h>\r
-\r
-\r
-/**\r
- Performs a delay measured as number of ticks.\r
-\r
- An internal function to perform a delay measured as number of ticks. It's\r
- invoked by MicroSecondDelay() and NanoSecondDelay().\r
-\r
- @param Delay The number of ticks to delay.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-InternalIpfDelay (\r
- IN INT64 Delay\r
- )\r
-{\r
- INT64 Ticks;\r
-\r
- //\r
- // The target timer count is calculated here\r
- //\r
- Ticks = (INT64)AsmReadItc () + Delay;\r
-\r
- //\r
- // Wait until time out\r
- // Delay > 2^63 could not be handled by this function\r
- // Timer wrap-arounds are handled correctly by this function\r
- //\r
- while (Ticks - (INT64)AsmReadItc() >= 0);\r
-}\r
-\r
-/**\r
- Stalls the CPU for at least the given number of microseconds.\r
-\r
- Stalls the CPU for the number of microseconds specified by MicroSeconds.\r
-\r
- @param MicroSeconds The minimum number of microseconds to delay.\r
-\r
- @return The value of MicroSeconds inputted.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-MicroSecondDelay (\r
- IN UINTN MicroSeconds\r
- )\r
-{\r
- InternalIpfDelay (\r
- GetPerformanceCounterProperties (NULL, NULL) *\r
- MicroSeconds /\r
- 1000000\r
- );\r
- return MicroSeconds;\r
-}\r
-\r
-/**\r
- Stalls the CPU for at least the given number of nanoseconds.\r
-\r
- Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r
-\r
- @param NanoSeconds The minimum number of nanoseconds to delay.\r
-\r
- @return The value of NanoSeconds inputted.\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-NanoSecondDelay (\r
- IN UINTN NanoSeconds\r
- )\r
-{\r
- InternalIpfDelay (\r
- GetPerformanceCounterProperties (NULL, NULL) *\r
- NanoSeconds /\r
- 1000000000\r
- );\r
- return NanoSeconds;\r
-}\r
-\r
-/**\r
- Retrieves the current value of a 64-bit free running performance counter.\r
-\r
- The counter can either count up by 1 or count down by 1. If the physical\r
- performance counter counts by a larger increment, then the counter values\r
- must be translated. The properties of the counter can be retrieved from\r
- GetPerformanceCounterProperties().\r
-\r
- @return The current value of the free running performance counter.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-GetPerformanceCounter (\r
- VOID\r
- )\r
-{\r
- return AsmReadItc ();\r
-}\r
-\r
-/**\r
- Retrieves the 64-bit frequency in Hz and the range of performance counter\r
- values.\r
-\r
- If StartValue is not NULL, then the value that the performance counter starts\r
- with immediately after is it rolls over is returned in StartValue. If\r
- EndValue is not NULL, then the value that the performance counter end with\r
- immediately before it rolls over is returned in EndValue. The 64-bit\r
- frequency of the performance counter in Hz is always returned. If StartValue\r
- is less than EndValue, then the performance counter counts up. If StartValue\r
- is greater than EndValue, then the performance counter counts down. For\r
- example, a 64-bit free running counter that counts up would have a StartValue\r
- of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r
- that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r
-\r
- @param StartValue The value the performance counter starts with when it\r
- rolls over.\r
- @param EndValue The value that the performance counter ends with before\r
- it rolls over.\r
-\r
- @return The frequency in Hz.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-GetPerformanceCounterProperties (\r
- OUT UINT64 *StartValue, OPTIONAL\r
- OUT UINT64 *EndValue OPTIONAL\r
- )\r
-{\r
- PAL_CALL_RETURN PalRet;\r
- UINT64 BaseFrequence;\r
-\r
- if (StartValue != NULL) {\r
- *StartValue = 0;\r
- }\r
-\r
- if (EndValue != NULL) {\r
- *EndValue = (UINT64)(-1);\r
- }\r
-\r
- PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);\r
- if (PalRet.Status != 0) {\r
- return 1000000;\r
- }\r
- BaseFrequence = PalRet.r9;\r
-\r
- PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);\r
- if (PalRet.Status != 0) {\r
- return 1000000;\r
- }\r
-\r
- return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;\r
-}\r
-\r
-/**\r
- Converts elapsed ticks of performance counter to time in nanoseconds.\r
-\r
- This function converts the elapsed ticks of running performance counter to\r
- time value in unit of nanoseconds.\r
-\r
- @param Ticks The number of elapsed ticks of running performance counter.\r
-\r
- @return The elapsed time in nanoseconds.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-GetTimeInNanoSecond (\r
- IN UINT64 Ticks\r
- )\r
-{\r
- UINT64 Frequency;\r
- UINT64 NanoSeconds;\r
- UINT64 Remainder;\r
- INTN Shift;\r
-\r
- Frequency = GetPerformanceCounterProperties (NULL, NULL);\r
-\r
- //\r
- // Ticks\r
- // Time = --------- x 1,000,000,000\r
- // Frequency\r
- //\r
- NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r
-\r
- //\r
- // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r
- // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
- // i.e. highest bit set in Remainder should <= 33.\r
- //\r
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
- NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
-\r
- return NanoSeconds;\r
-}\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF\r
+# VALID_ARCHITECTURES = IA32 X64\r
#\r
\r
[Sources.Ia32, Sources.X64]\r
X86TimerLib.c\r
\r
-[Sources.IPF]\r
- IpfTimerLib.c\r
-\r
-\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
IoLib\r
DebugLib\r
\r
-[LibraryClasses.IPF]\r
- PalLib\r
-\r
-\r
[Pcd.IA32, Pcd.X64]\r
gEfiMdePkgTokenSpaceGuid.PcdFSBClock ## CONSUMES\r
\r
## @file\r
# NULL instance of SmiHandlerProfile Library.\r
#\r
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
## @file\r
# Module entry point library for UEFI Application.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
LIBRARY_CLASS = UefiApplicationEntryPoint|UEFI_APPLICATION\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
FILE_GUID = ff5c7a2c-ab7a-4366-8616-11c6e53247b6\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
+ LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
\r
CONSTRUCTOR = UefiBootServicesTableLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
FILE_GUID = 5cddfaf3-e9a7-4d16-bdce-1e002df475bb\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
\r
FILE_GUID = 102287b4-6b12-4D41-91e1-ebee1f3aa614\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
\r
FILE_GUID = b57a1df6-ffdb-4247-a3df-3a562176751a\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
#\r
# Device Path Library that layers on top of the Memory Allocation Library.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 91c1677a-e57f-4191-8b8e-eb7711a716e0\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
+ LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
FILE_GUID = 3E1C696D-FCF0-45a7-85A7-E86C2A1C1080\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
+ LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
\r
CONSTRUCTOR = UefiDevicePathLibOptionalDevicePathProtocolConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# Device Path Library that layers on top of the UEFI 2.0 Device Path Utilities Protocol.\r
# This library is not available for EFI 1.10 modules.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 050EB8C6-C12E-4b86-892B-40985E8B3137\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
+ LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
\r
CONSTRUCTOR = DevicePathLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
## @file\r
# Module entry point library for UEFI driver, DXE driver and SMM driver.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 331deb15-454b-48d8-9b74-70d01f3f3556\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER UEFI_DRIVER SMM_CORE DXE_SMM_DRIVER\r
+ LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_DRIVER SMM_CORE DXE_SMM_DRIVER\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
## @file\r
# Provides interface to shell functionality for shell commands and applications.\r
#\r
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved. <BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
LIBRARY_CLASS = FileHandleLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER DXE_RUNTIME_DRIVER\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources.common]\r
FILE_GUID = 3a004ba5-efe0-4a61-9f1a-267a46ae5ba9\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
+ LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
CONSTRUCTOR = UefiLibConstructor\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# Memory Allocation Library that uses EFI Boot Services to allocate\r
# and free memory.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 4674739d-3195-4fb2-8094-ac1d22d00194\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
FILE_GUID = f1bbe03d-2f28-4dee-bec7-d98d7a30c36a\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = BaseMemoryLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = BaseMemoryLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-/** @file\r
- PAL Library implementation retrieving the PAL Entry Point from the SAL System Table\r
- register in the EFI System Confguration Table.\r
-\r
- Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of\r
- the BSD License which accompanies this distribution. The full\r
- text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <IndustryStandard/Sal.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#include <Guid/SalSystemTable.h>\r
-\r
-UINT64 mPalProcEntry;\r
-\r
-/**\r
- Makes a PAL procedure call.\r
-\r
- This is a wrapper function to make a PAL procedure call. Based on the Index value,\r
- this API will make static or stacked PAL call. Architected procedures may be designated\r
- as required or optional. If a PAL procedure is specified as optional, a unique return\r
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.\r
- This indicates that the procedure is not present in this PAL implementation. It is the\r
- caller's responsibility to check for this return code after calling any optional PAL\r
- procedure. No parameter checking is performed on the 4 input parameters, but there are\r
- some common rules that the caller should follow when making a PAL call. Any address\r
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses\r
- may cause undefined results. For those parameters defined as reserved or some fields\r
- defined as reserved must be zero filled or the invalid argument return value may be\r
- returned or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
-\r
- @param Index The PAL procedure Index number.\r
- @param Arg2 The 2nd parameter for PAL procedure calls.\r
- @param Arg3 The 3rd parameter for PAL procedure calls.\r
- @param Arg4 The 4th parameter for PAL procedure calls.\r
-\r
- @return Structure returned from the PAL Call procedure, including the status and return value.\r
-\r
-**/\r
-PAL_CALL_RETURN\r
-EFIAPI\r
-PalCall (\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4\r
- )\r
-{\r
- //\r
- // mPalProcEntry is initialized in library constructor as PAL entry.\r
- //\r
- return AsmPalCall (\r
- mPalProcEntry,\r
- Index,\r
- Arg2,\r
- Arg3,\r
- Arg4\r
- );\r
-\r
-}\r
-\r
-/**\r
- The constructor function of UEFI Pal Lib.\r
-\r
- The constructor function looks up the SAL System Table in the EFI System Configuration\r
- Table. Once the SAL System Table is found, the PAL Entry Point in the SAL System Table\r
- will be derived and stored into a global variable for library usage.\r
- It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System\r
- Table is not the valid data.\r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-UefiPalLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- SAL_ST_ENTRY_POINT_DESCRIPTOR *SalStEntryDes;\r
- SAL_SYSTEM_TABLE_HEADER *SalSystemTable;\r
-\r
- Status = EfiGetSystemConfigurationTable (\r
- &gEfiSalSystemTableGuid,\r
- (VOID **) &SalSystemTable\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- ASSERT (SalSystemTable != NULL);\r
-\r
- //\r
- // Check the first entry of SAL System Table,\r
- // because the SAL entry is in ascending order with the entry type,\r
- // the type 0 entry should be the first if exist.\r
- //\r
- SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);\r
-\r
- //\r
- // Assure the SAL ENTRY Type is 0\r
- //\r
- ASSERT (SalStEntryDes->Type == EFI_SAL_ST_ENTRY_POINT);\r
-\r
- mPalProcEntry = SalStEntryDes->PalProcEntry;\r
- //\r
- // Make sure the PalCallAddress has the valid value\r
- //\r
- ASSERT (mPalProcEntry != 0);\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-## @file\r
-# UEFI Instance of PAL Library Class.\r
-#\r
-# This instance of PAL library retrieves the PAL Entry Point from the SAL System Table\r
-# register in the EFI System Confguration Table.\r
-#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = UefiPalLib\r
- MODULE_UNI_FILE = UefiPalLib.uni\r
- FILE_GUID = B7F30170-9E5F-482a-B553-A145A5787003\r
- MODULE_TYPE = UEFI_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PalLib|UEFI_DRIVER UEFI_APPLICATION\r
-\r
- CONSTRUCTOR = UefiPalLibConstructor\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- UefiPalLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- UefiLib\r
- BaseLib\r
- DebugLib\r
-\r
-[Guids]\r
- gEfiSalSystemTableGuid ## CONSUMES ## SystemTable\r
-\r
+++ /dev/null
-// /** @file\r
-// UEFI Instance of PAL Library Class.\r
-//\r
-// This instance of PAL library retrieves the PAL Entry Point from the SAL System Table\r
-// register in the EFI System Confguration Table.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "UEFI Instance of PAL Library Class"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "This instance of PAL library retrieves the PAL Entry Point from the SAL System Table register in the EFI System Configuration Table."\r
-\r
# This library binds to the first PCI Root Bridge I/O Protocol in the platform. As a result,\r
# it should only be used on platforms that contain a single PCI root bridge.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 90EC42CB-B780-4eb8-8E99-C8E3E5F37530\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+ LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
\r
CONSTRUCTOR = PciLibConstructor\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# This library binds to all of the PCI Root Bridge I/O Protocols in the platform and handles\r
# the translation from a PCI segment number into a specific PCI Root Bridge I/O Protocol.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = C6068612-B6E0-48a3-BB92-60E4A4F89EDF\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+ LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
\r
CONSTRUCTOR = PciSegmentLibConstructor\r
DESTRUCTOR = PciSegmentLibDestructor\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
FILE_GUID = b1ee6c28-54aa-4d17-b705-3e28ccb27b2e\r
MODULE_TYPE = DXE_RUNTIME_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiRuntimeLib|DXE_RUNTIME_DRIVER DXE_SAL_DRIVER\r
+ LIBRARY_CLASS = UefiRuntimeLib|DXE_RUNTIME_DRIVER\r
\r
CONSTRUCTOR = RuntimeDriverLibConstruct\r
DESTRUCTOR = RuntimeDriverLibDeconstruct\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
\r
## @file\r
# UEFI Runtime Services Table Library implementation.\r
#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 19cbbb97-ff61-45ff-8c3f-dfa66dd118c8\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
+ LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE\r
\r
CONSTRUCTOR = UefiRuntimeServicesTableLibConstructor\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
+++ /dev/null
-/** @file\r
- SAL Library implementation retrieving the SAL Entry Point from the SAL System Table\r
- register in the EFI System Configuration Table.\r
-\r
- Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of\r
- the BSD License which accompanies this distribution. The full\r
- text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <PiDxe.h>\r
-#include <IndustryStandard/Sal.h>\r
-\r
-#include <Library/SalLib.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#include <Guid/SalSystemTable.h>\r
-\r
-EFI_PLABEL mPlabel;\r
-SAL_PROC mSalProcEntry;\r
-\r
-/**\r
- Makes a SAL procedure call.\r
-\r
- This is a wrapper function to make a SAL procedure call.\r
- No parameter checking is performed on the 8 input parameters,\r
- but there are some common rules that the caller should follow\r
- when making a SAL call. Any address passed to SAL as buffers\r
- for return parameters must be 8-byte aligned. Unaligned\r
- addresses may cause undefined results. For those parameters\r
- defined as reserved or some fields defined as reserved must be\r
- zero filled or the invalid argument return value may be returned\r
- or undefined result may occur during the execution of the procedure.\r
- This function is only available on IPF.\r
-\r
- @param Index The SAL procedure Index number.\r
- @param Arg2 The 2nd parameter for SAL procedure calls.\r
- @param Arg3 The 3rd parameter for SAL procedure calls.\r
- @param Arg4 The 4th parameter for SAL procedure calls.\r
- @param Arg5 The 5th parameter for SAL procedure calls.\r
- @param Arg6 The 6th parameter for SAL procedure calls.\r
- @param Arg7 The 7th parameter for SAL procedure calls.\r
- @param Arg8 The 8th parameter for SAL procedure calls.\r
-\r
- @return SAL returned registers.\r
-\r
-**/\r
-SAL_RETURN_REGS\r
-EFIAPI\r
-SalCall (\r
- IN UINT64 Index,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4,\r
- IN UINT64 Arg5,\r
- IN UINT64 Arg6,\r
- IN UINT64 Arg7,\r
- IN UINT64 Arg8\r
- )\r
-{\r
- //\r
- // mSalProcEntry is initialized in library constructor as SAL entry.\r
- //\r
- return mSalProcEntry(\r
- Index,\r
- Arg2,\r
- Arg3,\r
- Arg4,\r
- Arg5,\r
- Arg6,\r
- Arg7,\r
- Arg8\r
- );\r
-\r
-}\r
-\r
-/**\r
- The constructor function of UEFI SAL Lib.\r
-\r
- The constructor function looks up the SAL System Table in the EFI System Configuration\r
- Table. Once the SAL System Table is found, the SAL Entry Point in the SAL System Table\r
- will be derived and stored into a global variable for library usage.\r
- It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System\r
- Table is not the valid data.\r
-\r
- @param ImageHandle The firmware allocated handle for the EFI image.\r
- @param SystemTable A pointer to the EFI System Table.\r
-\r
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-UefiSalLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- SAL_ST_ENTRY_POINT_DESCRIPTOR *SalStEntryDes;\r
- SAL_SYSTEM_TABLE_HEADER *SalSystemTable;\r
-\r
- Status = EfiGetSystemConfigurationTable (\r
- &gEfiSalSystemTableGuid,\r
- (VOID **) &SalSystemTable\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- ASSERT (SalSystemTable != NULL);\r
-\r
- //\r
- // Check the first entry of SAL System Table,\r
- // because the SAL entry is in ascending order with the entry type,\r
- // the type 0 entry should be the first if exist.\r
- //\r
- SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);\r
-\r
- //\r
- // Assure the SAL ENTRY Type is 0\r
- //\r
- ASSERT (SalStEntryDes->Type == EFI_SAL_ST_ENTRY_POINT);\r
-\r
- mPlabel.EntryPoint = SalStEntryDes->SalProcEntry;\r
- mPlabel.GP = SalStEntryDes->SalGlobalDataPointer;\r
- //\r
- // Make sure the EntryPoint has the valid value\r
- //\r
- ASSERT ((mPlabel.EntryPoint != 0) && (mPlabel.GP != 0));\r
-\r
- mSalProcEntry = (SAL_PROC)((UINT64)&(mPlabel.EntryPoint));\r
-\r
- return EFI_SUCCESS;\r
-}\r
+++ /dev/null
-## @file\r
-# UEFI Instance of SAL Library Class.\r
-#\r
-# This instance of SAL library retrieves the SAL Entry Point from the SAL System Table\r
-# register in the EFI System Confguration Table.\r
-#\r
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php.\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-##\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = UefiSalLib\r
- MODULE_UNI_FILE = UefiSalLib.uni\r
- FILE_GUID = 4ABCFD77-4A33-4089-B003-5F09BCA940A2\r
- MODULE_TYPE = UEFI_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = SalLib|UEFI_DRIVER UEFI_APPLICATION\r
-\r
- CONSTRUCTOR = UefiSalLibConstructor\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IPF\r
-#\r
-\r
-[Sources]\r
- UefiSalLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- UefiLib\r
- DebugLib\r
-\r
-[Guids]\r
- gEfiSalSystemTableGuid ## CONSUMES ## SystemTable\r
-\r
+++ /dev/null
-// /** @file\r
-// UEFI Instance of SAL Library Class.\r
-//\r
-// This instance of SAL library retrieves the SAL Entry Point from the SAL System Table\r
-// register in the EFI System Confguration Table.\r
-//\r
-// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php.\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-// **/\r
-\r
-\r
-#string STR_MODULE_ABSTRACT #language en-US "UEFI Instance of SAL Library Class"\r
-\r
-#string STR_MODULE_DESCRIPTION #language en-US "This instance of SAL library retrieves the SAL Entry Point from the SAL System Table register in the EFI System Configuration Table."\r
-\r
FILE_GUID = 280E42C3-826E-4573-9772-B74EF1086D95\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiScsiLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = UefiScsiLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
# This library instance provides most usb APIs to support the Hid requests defined in\r
# Usb Hid 1.1 spec and the standard requests defined in Usb 1.1 spec.\r
#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = 87eb5df9-722a-4241-ad7f-370d0b3a56d7\r
MODULE_TYPE = UEFI_DRIVER\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiUsbLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+ LIBRARY_CLASS = UefiUsbLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
\r
\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
#\r
\r
[Sources]\r
[Includes.X64]\r
Include/X64\r
\r
-[Includes.IPF]\r
- Include/Ipf\r
-\r
[Includes.EBC]\r
Include/Ebc\r
\r
## @libraryclass Provides services to log the SMI handler registration.\r
SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h\r
\r
-[LibraryClasses.IPF]\r
- ## @libraryclass The SAL Library provides a service to make a SAL CALL.\r
- SalLib|Include/Library/SalLib.h\r
-\r
- ## @libraryclass Provides library services to make PAL Calls.\r
- PalLib|Include/Library/PalLib.h\r
-\r
- ## @libraryclass Provides library services to make Extended SAL Calls.\r
- ExtendedSalLib|Include/Library/ExtendedSalLib.h\r
-\r
[Guids]\r
#\r
# GUID defined in UEFI2.1/UEFI2.0/EFI1.1\r
# @Prompt Memory Address of GuidedExtractHandler Table.\r
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x1000000|UINT64|0x30001015\r
\r
-[PcdsFixedAtBuild.IPF, PcdsPatchableInModule.IPF]\r
- ## The base address of IO port space for IA64 arch.\r
- # @Prompt IA64 IO Port Space Base Address.\r
- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf|0x0ffffc000000|UINT64|0x0000000f\r
-\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
## This value is used to set the base address of PCI express hierarchy.\r
# @Prompt PCI Express Base Address.\r
PLATFORM_VERSION = 1.08\r
DSC_SPECIFICATION = 0x00010005\r
OUTPUT_DIRECTORY = Build/Mde\r
- SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM|AARCH64\r
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64\r
BUILD_TARGETS = DEBUG|RELEASE|NOOPT\r
SKUID_IDENTIFIER = DEFAULT\r
\r
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000\r
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
\r
-[PcdsFixedAtBuild.IPF]\r
- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf|0x0ffffc000000\r
-\r
-###################################################################################################\r
-#\r
-# Components Section - list of the modules and components that will be processed by compilation\r
-# tools and the EDK II tools to generate PE32/PE32+/Coff image files.\r
-#\r
-# Note: The EDK II DSC file is not used to specify how compiled binary images get placed\r
-# into firmware volume images. This section is just a list of modules to compile from\r
-# source into UEFI-compliant binaries.\r
-# It is the FDF file that contains information on combining binary files into firmware\r
-# volume images, whose concept is beyond UEFI and is described in PI specification.\r
-# Binary modules do not need to be listed in this section, as they should be\r
-# specified in the FDF file. For example: Shell binary (Shell_Full.efi), FAT binary (Fat.efi),\r
-# Logo (Logo.bmp), and etc.\r
-# There may also be modules listed in this section that are not required in the FDF file,\r
-# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be\r
-# generated for it, but the binary will not be put into any firmware volume.\r
-#\r
-###################################################################################################\r
-\r
[Components]\r
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf\r
MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf\r
\r
-[Components.IPF]\r
- MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
- MdePkg/Library/BasePalLibNull/BasePalLibNull.inf\r
- MdePkg/Library/PeiPalLib/PeiPalLib.inf\r
- MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf\r
- MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf\r
- MdePkg/Library/UefiPalLib/UefiPalLib.inf\r
- MdePkg/Library/UefiSalLib/UefiSalLib.inf\r
- MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf\r
- MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf\r
- MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf\r
- MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf\r
- MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf\r
- MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf\r
- MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf\r
- MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf\r
-\r
[Components.EBC]\r
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
"2 - VT100+<BR>\n"\r
"3 - UTF8<BR>"\r
\r
-#string STR_gEfiMdePkgTokenSpaceGuid_PcdIoBlockBaseAddressForIpf_PROMPT #language en-US "IA64 IO Port Space Base Address."\r
-\r
-#string STR_gEfiMdePkgTokenSpaceGuid_PcdIoBlockBaseAddressForIpf_HELP #language en-US "The base address of IO port space for IA64 arch."\r
-\r
#string STR_gEfiMdePkgTokenSpaceGuid_PcdComponentNameDisable_PROMPT #language en-US "Disable Component Name Protocol"\r
\r
#string STR_gEfiMdePkgTokenSpaceGuid_PcdComponentNameDisable_HELP #language en-US "Indicates if the component name protocol will be installed.<BR><BR>\n"\r
projects / mirror_edk2.git / commitdiff