Refine new library instances according to review comments.

[mirror_edk2.git] / MdePkg / Library / DxePciLibPciRootBridgeIo / PciLib.c

diff --git a/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c
index 3c690aa70af62723ac2702ce4ea49aec1089f5bd..a408b0a0f1e8eb8fb5bfa12d1b30ffdbad459547 100644 (file)
--- a/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c
+++ b/MdePkg/Library/DxePciLibPciRootBridgeIo/PciLib.c
@@ -34,14 +34,14 @@
   ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
 \r
 /**\r
-  Translate PCI Lib address into format of PCI CFG2 PPI.\r
+  Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.\r
 \r
   @param  A  Address that encodes the PCI Bus, Device, Function and\r
              Register.\r
 \r
 **/\r
-#define PCI_TO_PCICFG2_ADDRESS(A) \\r
-  (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)\r
+#define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \\r
+  ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
 \r
 //\r
 // Global varible to cache pointer to PCI Root Bridge I/O protocol.\r
@@ -101,7 +101,7 @@ DxePciLibPciRootBridgeIoReadWorker (
   mPciRootBridgeIo->Pci.Read (\r
                           mPciRootBridgeIo,\r
                           Width,\r
-                          PCI_TO_PCICFG2_ADDRESS (Address),\r
+                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
                           1,\r
                           &Data\r
                           );\r
@@ -135,7 +135,7 @@ DxePciLibPciRootBridgeIoWriteWorker (
   mPciRootBridgeIo->Pci.Write (\r
                           mPciRootBridgeIo,\r
                           Width,\r
-                          PCI_TO_PCICFG2_ADDRESS (Address),\r
+                          PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
                           1,\r
                           &Data\r
                           );\r
@@ -1228,7 +1228,7 @@ PciReadBuffer (
   UINTN                             ReturnValue;\r
 \r
   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
-  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
 \r
   if (Size == 0) {\r
     return Size;\r
@@ -1241,7 +1241,7 @@ PciReadBuffer (
   //\r
   ReturnValue = Size;\r
 \r
-  if ((StartAddress & 1) != 0) {\r
+  if ((StartAddress & BIT0) != 0) {\r
     //\r
     // Read a byte if StartAddress is byte aligned\r
     //\r
@@ -1251,7 +1251,7 @@ PciReadBuffer (
     Buffer = (UINT8*)Buffer + 1;\r
   }\r
 \r
-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
     //\r
     // Read a word if StartAddress is word aligned\r
     //\r
@@ -1326,7 +1326,7 @@ PciWriteBuffer (
   UINTN                             ReturnValue;\r
 \r
   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
-  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
 \r
   if (Size == 0) {\r
     return 0;\r
@@ -1339,7 +1339,7 @@ PciWriteBuffer (
   //\r
   ReturnValue = Size;\r
 \r
-  if ((StartAddress & 1) != 0) {\r
+  if ((StartAddress & BIT0) != 0) {\r
     //\r
     // Write a byte if StartAddress is byte aligned\r
     //\r
@@ -1349,7 +1349,7 @@ PciWriteBuffer (
     Buffer = (UINT8*)Buffer + 1;\r
   }\r
 \r
-  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
     //\r
     // Write a word if StartAddress is word aligned\r
     //\r