# @file\r
-# Component description file for PCI Lib using PCI Root Bridge I/O Protocol\r
+# PCI Library that layers on top of the PCI Root Bridge I/O Protocol.\r
#\r
# This library produces the APIs from the PCI Library and implements these APIs\r
# by calling into the PCI Root Bridge I/O Protocol. The PCI Root Bridge I/O Protocol is\r
# This library binds to the first PCI Root Bridge I/O Protocol in the platform. As a result,\r
# it should only be used on platforms that contain a single PCI root bridge.\r
#\r
-# Copyright (c) 2007, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
\r
/**\r
- Translate PCI Lib address into format of PCI CFG2 PPI.\r
+ Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.\r
\r
@param A Address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
**/\r
-#define PCI_TO_PCICFG2_ADDRESS(A) \\r
- (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)\r
+#define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \\r
+ ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
\r
//\r
// Global varible to cache pointer to PCI Root Bridge I/O protocol.\r
mPciRootBridgeIo->Pci.Read (\r
mPciRootBridgeIo,\r
Width,\r
- PCI_TO_PCICFG2_ADDRESS (Address),\r
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
1,\r
&Data\r
);\r
mPciRootBridgeIo->Pci.Write (\r
mPciRootBridgeIo,\r
Width,\r
- PCI_TO_PCICFG2_ADDRESS (Address),\r
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
1,\r
&Data\r
);\r
UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
return Size;\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Read a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
return 0;\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
# @file\r
-# Component description file for PCI Segment Lib using PCI Root Bridge I/O Protocol\r
+# PCI Segment Library that layers on top of the PCI Root Bridge I/O Protocol.\r
#\r
# This library produces the APIs from the PCI Library and implements these APIs\r
# by calling into the PCI Root Bridge I/O Protocols that are present in the platform.\r
# This library binds to all of the PCI Root Bridge I/O Protocols in the platform and handles\r
# the translation from a PCI segment number into a specific PCI Root Bridge I/O Protocol.\r
#\r
-# Copyright (c) 2007, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
/** @file\r
- Functions accessing PCI configuration registers on any supported PCI segment\r
+ PCI Segment Library implementation using PCI Root Bridge I/O Protocol.\r
\r
Copyright (c) 2007 - 2008, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
ASSERT (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR);\r
}\r
\r
- Status = gBS->FreePool(HandleBuffer);\r
- ASSERT_EFI_ERROR (Status);\r
+ FreePool(HandleBuffer);\r
\r
return EFI_SUCCESS;\r
}\r
PciRootBridgeIo->Pci.Read (\r
PciRootBridgeIo,\r
Width,\r
- PCI_TO_PCICFG2_ADDRESS (Address),\r
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
1,\r
&Data\r
);\r
PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
Width,\r
- PCI_TO_PCICFG2_ADDRESS (Address),\r
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
1,\r
&Data\r
);\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer receiving the data read.\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Read a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer containing the data to write.\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
ASSERT (((A) & (0xf0000000 | (M))) == 0)\r
\r
/**\r
- Translate PCI Lib address into format of PCI CFG2 PPI.\r
+ Translate PCI Lib address into format of PCI Root Bridge I/O Protocol\r
\r
@param A Address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
**/\r
-#define PCI_TO_PCICFG2_ADDRESS(A) \\r
- (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)\r
+#define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \\r
+ ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
\r
#endif\r
\r
**/\r
#define PCI_TO_PCICFG2_ADDRESS(A) \\r
- (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)\r
+ ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
\r
/**\r
Internal worker function to read a PCI configuration register.\r
UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
return Size;\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Read a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
return 0;\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
# @file\r
-# Component description file for PCI Lib using PCI CFG2 PPI\r
+# PCI Library that layers on top of the PCI CFG2 PPI.\r
#\r
# This library produces the APIs from the PCI Library and implements\r
# these APIs by calling into the EFI_PEI_PCI CFG2 PPI. One or more EFI_PEI_PCI CFG2\r
# the first PPI found, so this library instance should only be used platforms\r
# with a single PCI segment.\r
#\r
-# Copyright (c) 2007, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
FILE_GUID = FA3AD693-D58A-4619-960B-8EE85C914870\r
MODULE_TYPE = PEIM\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciLib|PEIM\r
+ LIBRARY_CLASS = PciLib|PEIM SEC PEI_CORE\r
EDK_RELEASE_VERSION = 0x00020000\r
EFI_SPECIFICATION_VERSION = 0x00020000\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
#\r
\r
[Sources.common]\r
\r
**/\r
#define PCI_TO_PCICFG2_ADDRESS(A) \\r
- (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)\r
+ ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
\r
/**\r
Gets PCI CFG2 PPI.\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer receiving the data read.\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Read a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer containing the data to write.\r
//\r
ReturnValue = Size;\r
\r
- if ((StartAddress & 1) != 0) {\r
+ if ((StartAddress & BIT0) != 0) {\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
Buffer = (UINT8*)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
# @file\r
-# This driver implements PCI Segment Lib using PCI CFG2 PPI.\r
+# PCI Segment Library that layers on top of the PCI CFG2 PPI.\r
#\r
# This library produces the APIs from the PCI Segment Library and\r
# implements these APIs by calling into the EFI_PEI_PCI CFG2 PPI. One or more\r
FILE_GUID = 254901AD-7DB7-45f8-93C8-93D579398D9F\r
MODULE_TYPE = PEIM\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciSegmentLib|PEIM\r
+ LIBRARY_CLASS = PciLib|PEIM SEC PEI_CORE\r
EDK_RELEASE_VERSION = 0x00020000\r
EFI_SPECIFICATION_VERSION = 0x00020000\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)\r
#\r
\r
[Sources.common]\r
/** @file\r
- PAL Library implementation built upon UEFI.\r
+ PAL Library implementation retrieving the PAL Entry Point from the SAL System Table\r
+ register in the EFI System Confguration Table.\r
\r
Copyright (c) 2007 - 2008, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
returned or undefined result may occur during the execution of the procedure.\r
This function is only available on IPF.\r
\r
- @param Index - The PAL procedure Index number.\r
- @param Arg2 - The 2nd parameter for PAL procedure calls.\r
- @param Arg3 - The 3rd parameter for PAL procedure calls.\r
- @param Arg4 - The 4th parameter for PAL procedure calls.\r
+ @param Index The PAL procedure Index number.\r
+ @param Arg2 The 2nd parameter for PAL procedure calls.\r
+ @param Arg3 The 3rd parameter for PAL procedure calls.\r
+ @param Arg4 The 4th parameter for PAL procedure calls.\r
\r
- @return structure returned from the PAL Call procedure, including the status and return value.\r
+ @return Structure returned from the PAL Call procedure, including the status and return value.\r
\r
**/\r
PAL_CALL_RETURN\r
\r
The constructor function looks up the SAL System Table in the EFI System Configuration\r
Table. Once the SAL System Table is found, the PAL Entry Point in the SAL System Table\r
- will be derived and stored inot a global variable for library usage.\r
+ will be derived and stored into a global variable for library usage.\r
It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System\r
Table is not the valid data.\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
- // Move the SAL System Table point to the first Entry\r
- // Due to the SAL Entry is in ascending order with the Entry type,\r
- // the type 0 Entry should be the first if exist.\r
+ // Check the first entry of SAL System Table,\r
+ // because the SAL entry is in ascending order with the entry type,\r
+ // the type 0 entry should be the first if exist.\r
//\r
SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);\r
\r
# @file\r
-# Uefi Instance of PAL Library Class\r
+# UEFI Instance of PAL Library Class.\r
#\r
-# This library implements the PAL Library Class by getting the PAL entry from SAL System\r
-# Table, and use AsmPalCall to produce the Pal Call.\r
+# This instance of PAL library retrieves the PAL Entry Point from the SAL System Table\r
+# register in the EFI System Confguration Table.\r
#\r
-# Copyright (c) 2007, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
BASE_NAME = UefiPalLib\r
FILE_GUID = B7F30170-9E5F-482a-B553-A145A5787003\r
MODULE_TYPE = UEFI_DRIVER\r
- VERSION_STRING = 1.04\r
+ VERSION_STRING = 1.0\r
LIBRARY_CLASS = PalLib|UEFI_DRIVER UEFI_APPLICATION\r
EDK_RELEASE_VERSION = 0x00020000\r
EFI_SPECIFICATION_VERSION = 0x00020000\r
/** @file\r
- SAL Library implementation built upon UEFI.\r
+ SAL Library implementation retrieving the SAL Entry Point from the SAL System Table\r
+ register in the EFI System Confguration Table.\r
\r
Copyright (c) 2007 - 2008, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
\r
The constructor function looks up the SAL System Table in the EFI System Configuration\r
Table. Once the SAL System Table is found, the SAL Entry Point in the SAL System Table\r
- will be derived and stored inot a global variable for library usage.\r
+ will be derived and stored into a global variable for library usage.\r
It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System\r
Table is not the valid data.\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
- // Move the SAL System Table point to the first Entry\r
- // Due to the SAL Entry is in ascending order with the Entry type,\r
- // the type 0 Entry should be the first if exist.\r
+ // Check the first entry of SAL System Table,\r
+ // because the SAL entry is in ascending order with the entry type,\r
+ // the type 0 entry should be the first if exist.\r
//\r
SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);\r
\r
mPlabel.EntryPoint = SalStEntryDes->SalProcEntry;\r
mPlabel.GP = SalStEntryDes->SalGlobalDataPointer;\r
//\r
- // Make sure the EntryPoint has the real value\r
+ // Make sure the EntryPoint has the valid value\r
//\r
ASSERT ((mPlabel.EntryPoint != 0) && (mPlabel.GP != 0));\r
\r
# @file\r
-# The library implements the UEFI SAL Library Class.\r
+# UEFI Instance of SAL Library Class.\r
#\r
-# The library implements the UEFI SAL Library Class.\r
-# This library is for boot service only modules.\r
+# This instance of SAL library retrieves the SAL Entry Point from the SAL System Table\r
+# register in the EFI System Confguration Table.\r
#\r
-# Copyright (c) 2007, Intel Corporation.\r
+# Copyright (c) 2007 - 2008, Intel Corporation.\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
BASE_NAME = UefiSalLib\r
FILE_GUID = 4ABCFD77-4A33-4089-B003-5F09BCA940A2\r
MODULE_TYPE = UEFI_DRIVER\r
- VERSION_STRING = 1.04\r
+ VERSION_STRING = 1.0\r
LIBRARY_CLASS = SalLib|UEFI_DRIVER UEFI_APPLICATION\r
EDK_RELEASE_VERSION = 0x00020000\r
EFI_SPECIFICATION_VERSION = 0x00020000\r
\r
[LibraryClasses]\r
UefiLib\r
- BaseLib\r
DebugLib\r
projects / mirror_edk2.git / commitdiff