/** @file\r
PCI Library using PCI Root Bridge I/O Protocol.\r
\r
- Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials are\r
- licensed and made available under the terms and conditions of\r
- the BSD License which accompanies this distribution. The full\r
- text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php.\r
- \r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
-#include <PiDxe.h>\r
-\r
#include <Protocol/PciRootBridgeIo.h>\r
\r
#include <Library/PciLib.h>\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_ADDRESS(A, M) \\r
ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
\r
/**\r
//\r
// Global varible to cache pointer to PCI Root Bridge I/O protocol.\r
//\r
-EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL; \r
+EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r
\r
/**\r
The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r
- \r
+\r
The constructor function locates PCI Root Bridge I/O protocol from protocol database.\r
- It will ASSERT() if that operation fails and it will always return EFI_SUCCESS. \r
+ It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r
\r
@param ImageHandle The firmware allocated handle for the EFI image.\r
@param SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
- \r
- Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mPciRootBridgeIo);\r
+\r
+ Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID **)&mPciRootBridgeIo);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mPciRootBridgeIo != NULL);\r
\r
\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- @param Width Width of data to read\r
+ @param Width The width of data to read\r
\r
@return The value read from the PCI configuration register.\r
\r
\r
This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r
It writes the PCI configuration register specified by Address with the\r
- value specified by Data. The width of data is specifed by Width.\r
+ value specified by Data. The width of data is specified by Width.\r
Data is returned.\r
\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- @param Width Width of data to write\r
+ @param Width The width of data to write\r
@param Data The value to write.\r
\r
@return The value written to the PCI configuration register.\r
}\r
\r
/**\r
- Registers a PCI device so PCI configuration registers may be accessed after \r
+ Registers a PCI device so PCI configuration registers may be accessed after\r
SetVirtualAddressMap().\r
- \r
- Registers the PCI device specified by Address so all the PCI configuration registers \r
+\r
+ Registers the PCI device specified by Address so all the PCI configuration registers\r
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
- \r
+\r
If Address > 0x0FFFFFFF, then ASSERT().\r
\r
@param Address The address that encodes the PCI Bus, Device, Function and\r
Register.\r
- \r
+\r
@retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
- @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function\r
after ExitBootServices().\r
@retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
at runtime could not be mapped.\r
UINT8\r
EFIAPI\r
PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
+ return (UINT8)DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
+ return (UINT8)DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r
+ return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciWrite8 (\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciWrite8 (\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT8\r
EFIAPI\r
PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
UINT16\r
EFIAPI\r
PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
+ return (UINT16)DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
+ return (UINT16)DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r
+ return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciWrite16 (\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciWrite16 (\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT16\r
EFIAPI\r
PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
UINT32\r
EFIAPI\r
PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciWrite32 (\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address The PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
UINTN\r
EFIAPI\r
PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
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