Reads an 8-bit PCI configuration register.\r
\r
Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ \r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
+ @return The 8-bit PCI configuration register specified by Address.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
/**\r
Writes an 8-bit PCI configuration register.\r
\r
- Writes the 8-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If any reserved bits in Address are set, then ASSERT().\r
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
+ If Address > 0x0FFFFFFF, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Value The value to write.\r
\r
@return The value written to the PCI configuration register.\r
\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Data\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
\r
- return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);\r
+ return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
}\r
\r
/**\r
- Performs a bitwise OR of an 8-bit PCI configuration register with\r
- an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r
\r
+ Reads the 8-bit PCI configuration register specified by Address,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
+ and writes the result to the 8-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
}\r
\r
/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
\r
+ Reads the 8-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ and writes the result to the 8-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
}\r
\r
/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise OR with another 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
+ followed a bitwise OR with another 8-bit value.\r
+ \r
+ Reads the 8-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 8-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
Reads a 16-bit PCI configuration register.\r
\r
Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ \r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
-\r
- @return The value read from the PCI configuration register.\r
+ @return The 16-bit PCI configuration register specified by Address.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
/**\r
Writes a 16-bit PCI configuration register.\r
\r
- Writes the 16-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The parameter of Value.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Data\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
\r
- return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);\r
+ return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
}\r
\r
/**\r
are serialized.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
Register.\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
}\r
\r
/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
\r
+ Reads the 16-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ and writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ \r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
}\r
\r
/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise OR with another 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
+ followed a bitwise OR with another 16-bit value.\r
+ \r
+ Reads the 16-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
returned.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
16-bit register is returned.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciSegmentWrite16 (\r
}\r
\r
/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
+ Reads the 16-bit PCI configuration register specified by Address,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
+ and writes the result to the 16-bit PCI configuration register specified by Address. \r
\r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
}\r
\r
/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r
+ and writes the result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
+ and writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ Extra left bits in OrData are stripped.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address PCI configuration register to write.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
+ The ordinal of the least significant bit in a byte is bit 0.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
+ The ordinal of the most significant bit in a byte is bit 7.\r
+ @param AndData The value to AND with the read value from the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
Reads a 32-bit PCI configuration register.\r
\r
Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
- @return The value read from the PCI configuration register.\r
+ @return The 32-bit PCI configuration register specified by Address.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
/**\r
Writes a 32-bit PCI configuration register.\r
\r
- Writes the 32-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param Data The value to write.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Value The value to write.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The parameter of Value.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Data\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
\r
- return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);\r
+ return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);\r
}\r
\r
/**\r
- Performs a bitwise OR of a 32-bit PCI configuration register with\r
- a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r
\r
+ Reads the 32-bit PCI configuration register specified by Address,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
+ and writes the result to the 32-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
}\r
\r
/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
\r
+ Reads the 32-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ and writes the result to the 32-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
}\r
\r
/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise OR with another 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
+ followed a bitwise OR with another 32-bit value.\r
+ \r
+ Reads the 32-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 32-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ \r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written back to the PCI configuration register.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
returned.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
32-bit register is returned.\r
\r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
AND, and writes the result back to the bit field in the 32-bit register.\r
\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
+ \r
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
+ AND between the read result and the value specified by AndData, and writes the result\r
+ to the 32-bit PCI configuration register specified by Address. The value written to\r
+ the PCI configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in AndData are stripped.\r
If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ \r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
/**\r
Reads a range of PCI configuration registers into a caller supplied buffer.\r
\r
- Reads the range of PCI configuration registers specified by StartAddress\r
- and Size into the buffer specified by Buffer.\r
- This function only allows the PCI configuration registers from a single PCI function to be read.\r
- Size is returned.\r
- \r
- If any reserved bits in StartAddress are set, then ASSERT().\r
+ Reads the range of PCI configuration registers specified by StartAddress and\r
+ Size into the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be read. Size is\r
+ returned. When possible 32-bit PCI configuration read cycles are used to read\r
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ and 16-bit PCI configuration read cycles may be used at the beginning and the\r
+ end of the range.\r
+\r
+ If StartAddress > 0x0FFFFFFF, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
+ Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer receiving the data read.\r
\r
- @return The parameter of Size.\r
+ @return Size\r
\r
**/\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
UINTN ReturnValue;\r
}\r
\r
/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress\r
- and Size from the buffer specified by Buffer.\r
- This function only allows the PCI configuration registers from a single PCI function to be written.\r
- Size is returned.\r
- \r
- If any reserved bits in StartAddress are set, then ASSERT().\r
+ Copies the data in a caller supplied buffer to a specified range of PCI\r
+ configuration space.\r
+\r
+ Writes the range of PCI configuration registers specified by StartAddress and\r
+ Size from the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be written. Size is\r
+ returned. When possible 32-bit PCI configuration write cycles are used to\r
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
+ and the end of the range.\r
+\r
+ If StartAddress > 0x0FFFFFFF, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
+ Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer containing the data to write.\r
\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
UINTN ReturnValue;\r
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