/** @file\r
- Template for Metronome Architecture Protocol driver of the ARM flavor\r
+ Handle OMAP35xx interrupt controller\r
\r
- Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
- \r
- All rights reserved. This program and the accompanying materials\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
#include <Library/UefiLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
+#include <Library/ArmLib.h>\r
\r
#include <Protocol/Cpu.h>\r
#include <Protocol/HardwareInterrupt.h>\r
//\r
// Notifications\r
//\r
-VOID *CpuProtocolNotificationToken = NULL;\r
-EFI_EVENT CpuProtocolNotificationEvent = (EFI_EVENT)NULL;\r
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
\r
\r
\r
/**\r
Shutdown our hardware\r
- \r
+\r
DXE Core will disable interrupts and turn off the timer and disable interrupts\r
after all the event handlers have run.\r
\r
)\r
{\r
// Disable all interrupts\r
- MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+\r
+ // Add code here to disable all FIQs as debugger may have turned one on\r
}\r
\r
/**\r
if (Source > MAX_VECTOR) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
- } \r
- \r
+ }\r
+\r
+ if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {\r
+ // This vector has been programmed as FIQ so we can't use it for IRQ\r
+ // EFI does not use FIQ, but the debugger can use it to check for\r
+ // ctrl-c. So this ASSERT means you have a conflict with the debug agent\r
+ ASSERT (FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
{\r
UINTN Bank;\r
UINTN Bit;\r
- \r
+\r
if (Source > MAX_VECTOR) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
Bank = Source / 32;\r
Bit = 1UL << (Source % 32);\r
- \r
- MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit);\r
- \r
+\r
+ MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DisableInterruptSource(\r
+DisableInterruptSource (\r
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
UINTN Bank;\r
UINTN Bit;\r
- \r
+\r
if (Source > MAX_VECTOR) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
- \r
+\r
Bank = Source / 32;\r
Bit = 1UL << (Source % 32);\r
- \r
- MmioWrite32(INTCPS_MIR_SET(Bank), Bit);\r
- \r
+\r
+ MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
{\r
UINTN Bank;\r
UINTN Bit;\r
- \r
+\r
if (InterruptState == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
if (Source > MAX_VECTOR) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
\r
Bank = Source / 32;\r
Bit = 1UL << (Source % 32);\r
- \r
+\r
if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {\r
*InterruptState = FALSE;\r
} else {\r
*InterruptState = TRUE;\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Signal to the hardware that the End Of Intrrupt state\r
+ has been reached.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt EOI'ed.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfInterrupt (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ ArmDataSyncronizationBarrier ();\r
+ return EFI_SUCCESS;\r
+}\r
\r
\r
/**\r
{\r
UINT32 Vector;\r
HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
- \r
- Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
+\r
+ Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
\r
// Needed to prevent infinite nesting when Time Driver lowers TPL\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ ArmDataSyncronizationBarrier ();\r
\r
InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
if (InterruptHandler != NULL) {\r
// Call the registered interrupt handler.\r
- InterruptHandler(Vector, SystemContext);\r
+ InterruptHandler (Vector, SystemContext);\r
}\r
- \r
+\r
// Needed to clear after running the handler\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ ArmDataSyncronizationBarrier ();\r
}\r
\r
//\r
RegisterInterruptSource,\r
EnableInterruptSource,\r
DisableInterruptSource,\r
- GetInterruptSourceState\r
+ GetInterruptSourceState,\r
+ EndOfInterrupt\r
};\r
\r
-//\r
-// Notification routines\r
-//\r
-VOID\r
-CpuProtocolInstalledNotification (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_CPU_ARCH_PROTOCOL *Cpu;\r
- \r
- //\r
- // Get the cpu protocol that this driver requires.\r
- //\r
- Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
- ASSERT_EFI_ERROR(Status);\r
-\r
- //\r
- // Unregister the default exception handler.\r
- //\r
- Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);\r
- ASSERT_EFI_ERROR(Status);\r
-\r
- //\r
- // Register to receive interrupts\r
- //\r
- Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
- ASSERT_EFI_ERROR(Status);\r
-}\r
-\r
/**\r
Initialize the state information for the CPU Architectural Protocol\r
\r
)\r
{\r
EFI_STATUS Status;\r
+ EFI_CPU_ARCH_PROTOCOL *Cpu;\r
\r
// Make sure the Interrupt Controller Protocol is not already installed in the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
// Make sure all interrupts are disabled by default.\r
- MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
- \r
+ MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
+ MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+\r
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,\r
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
NULL);\r
ASSERT_EFI_ERROR(Status);\r
- \r
- // Set up to be notified when the Cpu protocol is installed.\r
- Status = gBS->CreateEvent(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent); \r
+\r
+ //\r
+ // Get the CPU protocol that this driver requires.\r
+ //\r
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
ASSERT_EFI_ERROR(Status);\r
\r
- Status = gBS->RegisterProtocolNotify(&gEfiCpuArchProtocolGuid, CpuProtocolNotificationEvent, (VOID *)&CpuProtocolNotificationToken);\r
+ //\r
+ // Unregister the default exception handler.\r
+ //\r
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ //\r
+ // Register to receive interrupts\r
+ //\r
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
ASSERT_EFI_ERROR(Status);\r
\r
// Register for an ExitBootServicesEvent\r
projects / mirror_edk2.git / blobdiff