edk2: Remove packages moved to edk2-platforms

[mirror_edk2.git] / Omap35xxPkg / Library / DebugAgentTimerLib / DebugAgentTimerLib.c

diff --git a/Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c b/Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
deleted file mode 100644 (file)
index d0e77e1..0000000
--- a/Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/** @file\r
-  Debug Agent timer lib for OMAP 35xx.\r
-\r
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-\r
-  SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-#include <Base.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/OmapLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Omap3530/Omap3530.h>\r
-\r
-\r
-volatile UINT32 gVector;\r
-\r
-// Cached registers\r
-volatile UINT32 gTISR;\r
-volatile UINT32 gTCLR;\r
-volatile UINT32 gTLDR;\r
-volatile UINT32 gTCRR;\r
-volatile UINT32 gTIER;\r
-\r
-VOID\r
-EnableInterruptSource (\r
-  VOID\r
-  )\r
-{\r
-  UINTN Bank;\r
-  UINTN Bit;\r
-\r
-  // Map vector to FIQ, IRQ is default\r
-  MmioWrite32 (INTCPS_ILR (gVector), 1);\r
-\r
-  Bank = gVector / 32;\r
-  Bit  = 1UL << (gVector % 32);\r
-\r
-  MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r
-}\r
-\r
-VOID\r
-DisableInterruptSource (\r
-  VOID\r
-  )\r
-{\r
-  UINTN Bank;\r
-  UINTN Bit;\r
-\r
-  Bank = gVector / 32;\r
-  Bit  = 1UL << (gVector % 32);\r
-\r
-  MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r
-}\r
-\r
-\r
-\r
-/**\r
-  Setup all the hardware needed for the debug agents timer.\r
-\r
-  This function is used to set up debug enviroment. It may enable interrupts.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-DebugAgentTimerIntialize (\r
-  VOID\r
-  )\r
-{\r
-  UINT32      TimerBaseAddress;\r
-  UINT32      TimerNumber;\r
-\r
-  TimerNumber = PcdGet32(PcdOmap35xxDebugAgentTimer);\r
-  gVector = InterruptVectorForTimer (TimerNumber);\r
-\r
-  // Set up the timer registers\r
-  TimerBaseAddress = TimerBase (TimerNumber);\r
-  gTISR = TimerBaseAddress + GPTIMER_TISR;\r
-  gTCLR = TimerBaseAddress + GPTIMER_TCLR;\r
-  gTLDR = TimerBaseAddress + GPTIMER_TLDR;\r
-  gTCRR = TimerBaseAddress + GPTIMER_TCRR;\r
-  gTIER = TimerBaseAddress + GPTIMER_TIER;\r
-\r
-  if ((TimerNumber < 2) || (TimerNumber > 9)) {\r
-    // This code assumes one the General Purpose timers is used\r
-    // GPT2 - GPT9\r
-    CpuDeadLoop ();\r
-  }\r
-  // Set source clock for GPT2 - GPT9 to SYS_CLK\r
-  MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));\r
-\r
-}\r
-\r
-\r
-/**\r
-  Set the period for the debug agent timer. Zero means disable the timer.\r
-\r
-  @param[in] TimerPeriodMilliseconds    Frequency of the debug agent timer.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-DebugAgentTimerSetPeriod (\r
-  IN  UINT32  TimerPeriodMilliseconds\r
-  )\r
-{\r
-  UINT64      TimerCount;\r
-  INT32       LoadValue;\r
-\r
-  if (TimerPeriodMilliseconds == 0) {\r
-    // Turn off GPTIMER3\r
-    MmioWrite32 (gTCLR, TCLR_ST_OFF);\r
-\r
-    DisableInterruptSource ();\r
-  } else {\r
-    // Calculate required timer count\r
-    TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds));\r
-\r
-    // Set GPTIMER5 Load register\r
-    LoadValue = (INT32) -TimerCount;\r
-    MmioWrite32 (gTLDR, LoadValue);\r
-    MmioWrite32 (gTCRR, LoadValue);\r
-\r
-    // Enable Overflow interrupt\r
-    MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);\r
-\r
-    // Turn on GPTIMER3, it will reload at overflow\r
-    MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
-\r
-    EnableInterruptSource ();\r
-  }\r
-}\r
-\r
-\r
-/**\r
-  Perform End Of Interrupt for the debug agent timer. This is called in the\r
-  interrupt handler after the interrupt has been processed.\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-DebugAgentTimerEndOfInterrupt (\r
-  VOID\r
-  )\r
-{\r
-   // Clear all timer interrupts\r
-  MmioWrite32 (gTISR, TISR_CLEAR_ALL);\r
-\r
-  // Poll interrupt status bits to ensure clearing\r
-  while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);\r
-\r
-  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);\r
-  ArmDataSynchronizationBarrier ();\r
-\r
-}\r
-\r