Add PCD setting for Timer, default is 10 times a second. You need the timer to detect...

[mirror_edk2.git] / Omap35xxPkg / Library / OmapDmaLib / OmapDmaLib.c

diff --git a/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c b/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c
index f979b9444abfd20e73f77e73d37874d4cd17f068..fa4bce8853caa6a9963bc0c4e9e0ba73f3a36e9f 100755 (executable)
--- a/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c
+++ b/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c
@@ -125,11 +125,17 @@ EnableDmaChannel (
 \r
   /* - Set the destination frame index CDFI[31:0]*/\r
   MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
-  \r
+ \r
+  MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
+\r
+  // Enable all the status bits since we are polling\r
+  MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);\r
+  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);\r
+\r
   /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */\r
   /*--------------------------------------------------------------*/\r
   //write enable bit\r
-  MmioOr32 (DMA4_CCR(0), DMA4_CCR_ENABLE); //Launch transfer
+  MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
 
   return EFI_SUCCESS;
 }
@@ -138,6 +144,8 @@ EnableDmaChannel (
   Turn of DMA channel configured by EnableDma().\r
             \r
   @param  Channel               DMA Channel to configure\r
+  @param  SuccesMask            Bits in DMA4_CSR register indicate EFI_SUCCESS\r
+  @param  ErrorMask             Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r
                                   \r
   @retval EFI_SUCCESS           DMA hardware disabled\r
   @retval EFI_INVALID_PARAMETER Channel is not valid\r
@@ -147,17 +155,39 @@ EnableDmaChannel (
 EFI_STATUS
 EFIAPI
 DisableDmaChannel (
-  IN  UINTN       Channel
+  IN  UINTN       Channel,
+  IN  UINT32      SuccessMask,
+  IN  UINT32      ErrorMask
   )
 {
+  EFI_STATUS  Status = EFI_SUCCESS;
+  UINT32      Reg;
+
+
   if (Channel > DMA4_MAX_CHANNEL) {
     return EFI_INVALID_PARAMETER;
   }
 
+  do {
+    Reg = MmioRead32 (DMA4_CSR(Channel));
+    if ((Reg & ErrorMask) != 0) {
+      Status = EFI_DEVICE_ERROR;
+      DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));
+      break;
+    }
+  } while ((Reg & SuccessMask) != SuccessMask);
+
+
+  // Disable all status bits and clear them
+  MmioWrite32 (DMA4_CICR (Channel), 0);\r
+  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);
+
   MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE)); 
-  return EFI_SUCCESS;
+  return Status;
 }
 
+
+
 /**                                                                 \r
   Provides the DMA controller-specific addresses needed to access system memory.\r
   \r