ARM Packages: Removed trailing spaces

[mirror_edk2.git] / Omap35xxPkg / PciEmulation / PciEmulation.c

diff --git a/Omap35xxPkg/PciEmulation/PciEmulation.c b/Omap35xxPkg/PciEmulation/PciEmulation.c
index afa64193a261d0c97c4022cb02cc6f82957e9ae4..5af8849c4adc429c9eef5550a6b9921185ad2280 100644 (file)
--- a/Omap35xxPkg/PciEmulation/PciEmulation.c
+++ b/Omap35xxPkg/PciEmulation/PciEmulation.c
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  \r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -36,7 +36,7 @@ typedef struct {
 #define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE     SIGNATURE_32('p', 'c', 'i', 'o')\r
 #define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a)  CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)\r
 \r
-EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate = \r
+EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =\r
 {\r
   {\r
     { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },\r
@@ -82,7 +82,7 @@ ConfigureUSBHost (
 \r
   // Get the Power IC protocol\r
   Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);\r
-  ASSERT_EFI_ERROR (Status);  \r
+  ASSERT_EFI_ERROR (Status);\r
 \r
   // Power the USB PHY\r
   Data = VAUX_DEV_GRP_P1;\r
@@ -91,7 +91,7 @@ ConfigureUSBHost (
 \r
   Data = VAUX_DEDICATED_18V;\r
   Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEDICATED), 1, &Data);\r
-  ASSERT_EFI_ERROR (Status);  \r
+  ASSERT_EFI_ERROR (Status);\r
 \r
   // Enable power to the USB hub\r
   Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);\r
@@ -150,7 +150,7 @@ PciIoMemRead (
 {\r
   EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
 \r
-  return PciRootBridgeIoMemRead (&Private->RootBridge.Io, \r
+  return PciRootBridgeIoMemRead (&Private->RootBridge.Io,\r
                                 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
                                 Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
                                 Count,\r
@@ -170,7 +170,7 @@ PciIoMemWrite (
 {\r
   EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
 \r
-  return PciRootBridgeIoMemWrite (&Private->RootBridge.Io, \r
+  return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,\r
                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
                                  Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
                                  Count,\r
@@ -217,11 +217,11 @@ PciIoPciRead (
 {\r
   EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
 \r
-  return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width, \r
-                               Count, \r
-                               TRUE, \r
-                               (PTR)(UINTN)Buffer, \r
-                               TRUE, \r
+  return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
+                               Count,\r
+                               TRUE,\r
+                               (PTR)(UINTN)Buffer,\r
+                               TRUE,\r
                                (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)\r
                               );\r
 }\r
@@ -237,11 +237,11 @@ PciIoPciWrite (
 {\r
   EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
 \r
-  return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, \r
-                               Count, \r
-                               TRUE, \r
-                               (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset), \r
-                               TRUE, \r
+  return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+                               Count,\r
+                               TRUE,\r
+                               (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),\r
+                               TRUE,\r
                                (PTR)(UINTN)Buffer\r
                                );\r
 }\r
@@ -385,7 +385,7 @@ PciIoAttributes (
   case EfiPciIoAttributeOperationDisable:\r
     // Since we are not a real PCI device no enable/set or disable operations exist.\r
     return EFI_SUCCESS;\r
-    \r
+\r
   default:\r
   ASSERT (FALSE);\r
     return EFI_INVALID_PARAMETER;\r
@@ -418,7 +418,7 @@ PciIoSetBarAttributes (
   return EFI_UNSUPPORTED;\r
 }\r
 \r
-EFI_PCI_IO_PROTOCOL PciIoTemplate = \r
+EFI_PCI_IO_PROTOCOL PciIoTemplate =\r
 {\r
   PciIoPollMem,\r
   PciIoPollIo,\r
@@ -463,7 +463,7 @@ PciEmulationEntryPoint (
     Status = EFI_OUT_OF_RESOURCES;\r
     return Status;\r
   }\r
-  \r
+\r
   Private->Signature              = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE;  // Fill in signature\r
   Private->RootBridge.Signature   = PCI_ROOT_BRIDGE_SIGNATURE;          // Fake Root Bridge structure needs a signature too\r
   Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE;                 // Get the USB capability register base\r
@@ -504,7 +504,7 @@ PciEmulationEntryPoint (
   // Unique device path.\r
   CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));\r
   Private->DevicePath.AcpiDevicePath.UID = 0;\r
-  \r
+\r
   // Copy protocol structure\r
   CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));\r
 \r