/** @file\r
Legacy Region Support\r
\r
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials are\r
licensed and made available under the terms and conditions of the BSD License\r
#include "LegacyRegion.h"\r
\r
//\r
-// 440 PAM map.\r
+// 440/Q35 PAM map.\r
//\r
-// PAM Range Offset Bits Operation\r
-// =============== ====== ==== ===============================================================\r
-// 0xC0000-0xC3FFF 0x5a 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xC4000-0xC7FFF 0x5a 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xC8000-0xCBFFF 0x5b 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xCC000-0xCFFFF 0x5b 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xD0000-0xD3FFF 0x5c 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xD4000-0xD7FFF 0x5c 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xD8000-0xDBFFF 0x5d 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xDC000-0xDFFFF 0x5d 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xE0000-0xE3FFF 0x5e 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xE4000-0xE7FFF 0x5e 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xE8000-0xEBFFF 0x5f 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xEC000-0xEFFFF 0x5f 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
-// 0xF0000-0xFFFFF 0x59 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// PAM Range Offset Bits Operation\r
+// 440 Q35\r
+// =============== ==== ==== ==== ===============================================================\r
+// 0xC0000-0xC3FFF 0x5a 0x91 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xC4000-0xC7FFF 0x5a 0x91 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xC8000-0xCBFFF 0x5b 0x92 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xCC000-0xCFFFF 0x5b 0x92 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xD0000-0xD3FFF 0x5c 0x93 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xD4000-0xD7FFF 0x5c 0x93 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xD8000-0xDBFFF 0x5d 0x94 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xDC000-0xDFFFF 0x5d 0x94 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xE0000-0xE3FFF 0x5e 0x95 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xE4000-0xE7FFF 0x5e 0x95 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xE8000-0xEBFFF 0x5f 0x96 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xEC000-0xEFFFF 0x5f 0x96 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
+// 0xF0000-0xFFFFF 0x59 0x90 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal\r
//\r
STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = {\r
{0xC0000, SIZE_16KB, FALSE, FALSE},\r
{0xF0000, SIZE_64KB, FALSE, FALSE}\r
};\r
\r
-STATIC PAM_REGISTER_VALUE mRegisterValues[] = {\r
- {REG_PAM1_OFFSET, 0x01, 0x02},\r
- {REG_PAM1_OFFSET, 0x10, 0x20},\r
- {REG_PAM2_OFFSET, 0x01, 0x02},\r
- {REG_PAM2_OFFSET, 0x10, 0x20},\r
- {REG_PAM3_OFFSET, 0x01, 0x02},\r
- {REG_PAM3_OFFSET, 0x10, 0x20},\r
- {REG_PAM4_OFFSET, 0x01, 0x02},\r
- {REG_PAM4_OFFSET, 0x10, 0x20},\r
- {REG_PAM5_OFFSET, 0x01, 0x02},\r
- {REG_PAM5_OFFSET, 0x10, 0x20},\r
- {REG_PAM6_OFFSET, 0x01, 0x02},\r
- {REG_PAM6_OFFSET, 0x10, 0x20},\r
- {REG_PAM0_OFFSET, 0x10, 0x20}\r
+STATIC PAM_REGISTER_VALUE mRegisterValues440[] = {\r
+ {REG_PAM1_OFFSET_440, 0x01, 0x02},\r
+ {REG_PAM1_OFFSET_440, 0x10, 0x20},\r
+ {REG_PAM2_OFFSET_440, 0x01, 0x02},\r
+ {REG_PAM2_OFFSET_440, 0x10, 0x20},\r
+ {REG_PAM3_OFFSET_440, 0x01, 0x02},\r
+ {REG_PAM3_OFFSET_440, 0x10, 0x20},\r
+ {REG_PAM4_OFFSET_440, 0x01, 0x02},\r
+ {REG_PAM4_OFFSET_440, 0x10, 0x20},\r
+ {REG_PAM5_OFFSET_440, 0x01, 0x02},\r
+ {REG_PAM5_OFFSET_440, 0x10, 0x20},\r
+ {REG_PAM6_OFFSET_440, 0x01, 0x02},\r
+ {REG_PAM6_OFFSET_440, 0x10, 0x20},\r
+ {REG_PAM0_OFFSET_440, 0x10, 0x20}\r
};\r
\r
+STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] = {\r
+ {REG_PAM1_OFFSET_Q35, 0x01, 0x02},\r
+ {REG_PAM1_OFFSET_Q35, 0x10, 0x20},\r
+ {REG_PAM2_OFFSET_Q35, 0x01, 0x02},\r
+ {REG_PAM2_OFFSET_Q35, 0x10, 0x20},\r
+ {REG_PAM3_OFFSET_Q35, 0x01, 0x02},\r
+ {REG_PAM3_OFFSET_Q35, 0x10, 0x20},\r
+ {REG_PAM4_OFFSET_Q35, 0x01, 0x02},\r
+ {REG_PAM4_OFFSET_Q35, 0x10, 0x20},\r
+ {REG_PAM5_OFFSET_Q35, 0x01, 0x02},\r
+ {REG_PAM5_OFFSET_Q35, 0x10, 0x20},\r
+ {REG_PAM6_OFFSET_Q35, 0x01, 0x02},\r
+ {REG_PAM6_OFFSET_Q35, 0x10, 0x20},\r
+ {REG_PAM0_OFFSET_Q35, 0x10, 0x20}\r
+};\r
+\r
+STATIC PAM_REGISTER_VALUE *mRegisterValues;\r
+\r
//\r
// Handle used to install the Legacy Region Protocol\r
//\r
)\r
{\r
EFI_STATUS Status;\r
+ UINT16 HostBridgeDevId;\r
+\r
+ //\r
+ // Query Host Bridge DID to determine platform type\r
+ //\r
+ HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);\r
+ switch (HostBridgeDevId) {\r
+ case INTEL_82441_DEVICE_ID:\r
+ mRegisterValues = mRegisterValues440;\r
+ break;\r
+ case INTEL_Q35_MCH_DEVICE_ID:\r
+ mRegisterValues = mRegisterValuesQ35;\r
+ break;\r
+ default:\r
+ DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ __FUNCTION__, HostBridgeDevId));\r
+ ASSERT (FALSE);\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
\r
//\r
// Install the Legacy Region Protocol on a new handle\r
projects / mirror_edk2.git / blobdiff