OvmfPkg: factor the MMIO aperture shared by all PCI root bridges into PCDs

[mirror_edk2.git] / OvmfPkg / OvmfPkg.dec

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index d61600225919ff6d7d36e910c1215a7419e0554e..784542f62368d59f99f127e4c192b0394a033958 100644 (file)
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -48,6 +48,10 @@
   #\r
   XenHypercallLib|Include/Library/XenHypercallLib.h\r
 \r
+  ##  @libraryclass  Manage XenBus device path and I/O handles\r
+  #\r
+  XenIoMmioLib|Include/Library/XenIoMmioLib.h\r
+\r
 [Guids]\r
   gUefiOvmfPkgTokenSpaceGuid      = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
   gEfiXenInfoGuid                 = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
@@ -85,7 +89,13 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6\r
   gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7\r
 \r
-[PcdsFixedAtBuild]\r
+  ## The following setting controls how many megabytes we configure as TSEG on\r
+  #  Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values cause\r
+  #  undefined behavior.\r
+  #\r
+  #  This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below).\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT8|0x20\r
+\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa\r
@@ -102,13 +112,35 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19\r
   gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f\r
+\r
+  ## The IO port aperture shared by all PCI root bridges.\r
+  #\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0xC000|UINT64|0x22\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x4000|UINT64|0x23\r
 \r
 [PcdsDynamic, PcdsDynamicEx]\r
   gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r
+\r
+  ## The 32-bit MMIO aperture shared by all PCI root bridges.\r
+  #\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r
 \r
 [PcdsFeatureFlag]\r
   gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootEnable|FALSE|BOOLEAN|3\r
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d\r
+\r
+  ## This feature flag enables SMM/SMRAM support. Note that it also requires\r
+  #  such support from the underlying QEMU instance; if that support is not\r
+  #  present, the firmware will reject continuing after a certain point.\r
+  #\r
+  #  The flag also acts as a general "security switch"; when TRUE, many\r
+  #  components will change behavior, with the goal of preventing a malicious\r
+  #  runtime OS from tampering with firmware structures (special memory ranges\r
+  #  used by OVMF, the varstore pflash chip, LockBox etc).\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e\r