+\r
+/**\r
+ Return the highest address that DXE could possibly use, plus one.\r
+**/\r
+STATIC\r
+UINT64\r
+GetFirstNonAddress (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 FirstNonAddress;\r
+ UINT64 Pci64Base, Pci64Size;\r
+ CHAR8 MbString[7 + 1];\r
+ EFI_STATUS Status;\r
+ FIRMWARE_CONFIG_ITEM FwCfgItem;\r
+ UINTN FwCfgSize;\r
+ UINT64 HotPlugMemoryEnd;\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ //\r
+ // set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r
+ //\r
+ FirstNonAddress = 0;\r
+\r
+ //\r
+ // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM\r
+ // address from it. This can express an address >= 4GB+1TB.\r
+ //\r
+ // Otherwise, get the flat size of the memory above 4GB from the CMOS (which\r
+ // can only express a size smaller than 1TB), and add it to 4GB.\r
+ //\r
+ Status = ScanOrAdd64BitE820Ram (&FirstNonAddress);\r
+ if (EFI_ERROR (Status)) {\r
+ FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
+ }\r
+\r
+ //\r
+ // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
+ // resources to 32-bit anyway. See DegradeResource() in\r
+ // "PciResourceSupport.c".\r
+ //\r
+#ifdef MDE_CPU_IA32\r
+ if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
+ return FirstNonAddress;\r
+ }\r
+#endif\r
+\r
+ //\r
+ // Otherwise, in order to calculate the highest address plus one, we must\r
+ // consider the 64-bit PCI host aperture too. Fetch the default size.\r
+ //\r
+ Pci64Size = PcdGet64 (PcdPciMmio64Size);\r
+\r
+ //\r
+ // See if the user specified the number of megabytes for the 64-bit PCI host\r
+ // aperture. The number of non-NUL characters in MbString allows for\r
+ // 9,999,999 MB, which is approximately 10 TB.\r
+ //\r
+ // As signaled by the "X-" prefix, this knob is experimental, and might go\r
+ // away at any time.\r
+ //\r
+ Status = QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem,\r
+ &FwCfgSize);\r
+ if (!EFI_ERROR (Status)) {\r
+ if (FwCfgSize >= sizeof MbString) {\r
+ DEBUG ((EFI_D_WARN,\r
+ "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r
+ __FUNCTION__));\r
+ } else {\r
+ QemuFwCfgSelectItem (FwCfgItem);\r
+ QemuFwCfgReadBytes (FwCfgSize, MbString);\r
+ MbString[FwCfgSize] = '\0';\r
+ Pci64Size = LShiftU64 (AsciiStrDecimalToUint64 (MbString), 20);\r
+ }\r
+ }\r
+\r
+ if (Pci64Size == 0) {\r
+ if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",\r
+ __FUNCTION__));\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ }\r
+\r
+ //\r
+ // There's nothing more to do; the amount of memory above 4GB fully\r
+ // determines the highest address plus one. The memory hotplug area (see\r
+ // below) plays no role for the firmware in this case.\r
+ //\r
+ return FirstNonAddress;\r
+ }\r
+\r
+ //\r
+ // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r
+ // absolute, exclusive end address for the memory hotplug area. This area\r
+ // starts right at the end of the memory above 4GB. The 64-bit PCI host\r
+ // aperture must be placed above it.\r
+ //\r
+ Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,\r
+ &FwCfgSize);\r
+ if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {\r
+ QemuFwCfgSelectItem (FwCfgItem);\r
+ QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r
+ DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,\r
+ HotPlugMemoryEnd));\r
+\r
+ ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r
+ FirstNonAddress = HotPlugMemoryEnd;\r
+ }\r
+\r
+ //\r
+ // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r
+ // that the host can map it with 1GB hugepages. Follow suit.\r
+ //\r
+ Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r
+ Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r
+\r
+ //\r
+ // The 64-bit PCI host aperture should also be "naturally" aligned. The\r
+ // alignment is determined by rounding the size of the aperture down to the\r
+ // next smaller or equal power of two. That is, align the aperture by the\r
+ // largest BAR size that can fit into it.\r
+ //\r
+ Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r
+\r
+ if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ //\r
+ // The core PciHostBridgeDxe driver will automatically add this range to\r
+ // the GCD memory space map through our PciHostBridgeLib instance; here we\r
+ // only need to set the PCDs.\r
+ //\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
+ DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
+ __FUNCTION__, Pci64Base, Pci64Size));\r
+ }\r
+\r
+ //\r
+ // The useful address space ends with the 64-bit PCI host aperture.\r
+ //\r
+ FirstNonAddress = Pci64Base + Pci64Size;\r
+ return FirstNonAddress;\r
+}\r
+\r
+\r
+/**\r
+ Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
+**/\r
+VOID\r
+AddressWidthInitialization (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 FirstNonAddress;\r
+\r
+ //\r
+ // As guest-physical memory size grows, the permanent PEI RAM requirements\r
+ // are dominated by the identity-mapping page tables built by the DXE IPL.\r
+ // The DXL IPL keys off of the physical address bits advertized in the CPU\r
+ // HOB. To conserve memory, we calculate the minimum address width here.\r
+ //\r
+ FirstNonAddress = GetFirstNonAddress ();\r
+ mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
+\r
+ //\r
+ // If FirstNonAddress is not an integral power of two, then we need an\r
+ // additional bit.\r
+ //\r
+ if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r
+ ++mPhysMemAddressWidth;\r
+ }\r
+\r
+ //\r
+ // The minimum address width is 36 (covers up to and excluding 64 GB, which\r
+ // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r
+ // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r
+ // can simply assert that here, since 48 bits are good enough for 256 TB.\r
+ //\r
+ if (mPhysMemAddressWidth <= 36) {\r
+ mPhysMemAddressWidth = 36;\r
+ }\r
+ ASSERT (mPhysMemAddressWidth <= 48);\r
+}\r
+\r
+\r
+/**\r
+ Calculate the cap for the permanent PEI memory.\r
+**/\r
+STATIC\r
+UINT32\r
+GetPeiMemoryCap (\r
+ VOID\r
+ )\r
+{\r
+ BOOLEAN Page1GSupport;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINT32 Pml4Entries;\r
+ UINT32 PdpEntries;\r
+ UINTN TotalPages;\r
+\r
+ //\r
+ // If DXE is 32-bit, then just return the traditional 64 MB cap.\r
+ //\r
+#ifdef MDE_CPU_IA32\r
+ if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
+ return SIZE_64MB;\r
+ }\r
+#endif\r
+\r
+ //\r
+ // Dependent on physical address width, PEI memory allocations can be\r
+ // dominated by the page tables built for 64-bit DXE. So we key the cap off\r
+ // of those. The code below is based on CreateIdentityMappingPageTables() in\r
+ // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r
+ //\r
+ Page1GSupport = FALSE;\r
+ if (PcdGetBool (PcdUse1GPageTable)) {\r
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= 0x80000001) {\r
+ AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
+ if ((RegEdx & BIT26) != 0) {\r
+ Page1GSupport = TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (mPhysMemAddressWidth <= 39) {\r
+ Pml4Entries = 1;\r
+ PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
+ ASSERT (PdpEntries <= 0x200);\r
+ } else {\r
+ Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
+ ASSERT (Pml4Entries <= 0x200);\r
+ PdpEntries = 512;\r
+ }\r
+\r
+ TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
+ (PdpEntries + 1) * Pml4Entries + 1;\r
+ ASSERT (TotalPages <= 0x40201);\r
+\r
+ //\r
+ // Add 64 MB for miscellaneous allocations. Note that for\r
+ // mPhysMemAddressWidth values close to 36, the cap will actually be\r
+ // dominated by this increment.\r
+ //\r
+ return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
+}\r
+\r
+\r