if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// The MMCONFIG area is expected to fall between the top of low RAM and\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// The MMCONFIG area is expected to fall between the top of low RAM and\r
ASSERT (TopOfLowRam <= PciExBarBase);\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
ASSERT (TopOfLowRam <= PciExBarBase);\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
ASSERT_RETURN_ERROR (PcdStatus);\r