//\r
// The Library classes this module consumes\r
//\r
+#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
-#include <IndustryStandard/SmBios.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
EFI_PHYSICAL_ADDRESS MemoryBase,\r
- UINT64 MemorySize\r
+ UINT64 MemorySize,\r
+ BOOLEAN Cacheable\r
)\r
{\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ (Cacheable ?\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
+ 0\r
+ ) |\r
EFI_RESOURCE_ATTRIBUTE_TESTED,\r
MemoryBase,\r
MemorySize\r
EFI_RESOURCE_IO,\r
EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
- 0xC000,\r
- 0x4000\r
+ PcdGet64 (PcdPciIoBase),\r
+ PcdGet64 (PcdPciIoSize)\r
);\r
\r
//\r
\r
if (!mXen) {\r
UINT32 TopOfLowRam;\r
+ UINT32 PciBase;\r
+ UINT32 PciSize;\r
+\r
TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ //\r
+ // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
+ // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
+ // the RAM below 4 GB exceed it.\r
+ //\r
+ PciBase = BASE_2GB + BASE_1GB;\r
+ ASSERT (TopOfLowRam <= PciBase);\r
+ } else {\r
+ PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
+ }\r
\r
//\r
// address purpose size\r
// 0xFED20000 gap 896 KB\r
// 0xFEE00000 LAPIC 1 MB\r
//\r
- AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
- BASE_2GB : TopOfLowRam, 0xFC000000);\r
+ PciSize = 0xFC000000 - PciBase;\r
+ AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
+ PcdSet64 (PcdPciMmio32Base, PciBase);\r
+ PcdSet64 (PcdPciMmio32Size, PciSize);\r
AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
}\r
}\r
\r
+EFI_STATUS\r
+GetNamedFwCfgBoolean (\r
+ IN CHAR8 *FwCfgFileName,\r
+ OUT BOOLEAN *Setting\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ FIRMWARE_CONFIG_ITEM FwCfgItem;\r
+ UINTN FwCfgSize;\r
+ UINT8 Value[3];\r
+\r
+ Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if (FwCfgSize > sizeof Value) {\r
+ return EFI_BAD_BUFFER_SIZE;\r
+ }\r
+ QemuFwCfgSelectItem (FwCfgItem);\r
+ QemuFwCfgReadBytes (FwCfgSize, Value);\r
+\r
+ if ((FwCfgSize == 1) ||\r
+ (FwCfgSize == 2 && Value[1] == '\n') ||\r
+ (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
+ switch (Value[0]) {\r
+ case '0':\r
+ case 'n':\r
+ case 'N':\r
+ *Setting = FALSE;\r
+ return EFI_SUCCESS;\r
+\r
+ case '1':\r
+ case 'y':\r
+ case 'Y':\r
+ *Setting = TRUE;\r
+ return EFI_SUCCESS;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ return EFI_PROTOCOL_ERROR;\r
+}\r
+\r
+#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
+ do { \\r
+ BOOLEAN Setting; \\r
+ \\r
+ if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
+ "opt/ovmf/" #TokenName, &Setting))) { \\r
+ PcdSetBool (TokenName, Setting); \\r
+ } \\r
+ } while (0)\r
+\r
+VOID\r
+NoexecDxeInitialization (\r
+ VOID\r
+ )\r
+{\r
+ UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
+ UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
+}\r
\r
VOID\r
MiscInitialization (\r
IoOr8 (0x92, BIT1);\r
\r
//\r
- // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
+ // S3 resume as well, so we build it unconditionally.)\r
//\r
- BuildCpuHob (36, 16);\r
+ BuildCpuHob (mPhysMemAddressWidth, 16);\r
\r
//\r
// Determine platform type and save Host Bridge DID to PCD\r
if (CmosRead8 (0xF) == 0xFE) {\r
mBootMode = BOOT_ON_S3_RESUME;\r
}\r
+ CmosWrite8 (0xF, 0x00);\r
\r
Status = PeiServicesSetBootMode (mBootMode);\r
ASSERT_EFI_ERROR (Status);\r
VOID\r
)\r
{\r
- UINTN Loop;\r
+ UINT32 Loop;\r
\r
DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
}\r
\r
\r
-/**\r
- Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
-**/\r
-STATIC\r
VOID\r
-SmbiosVersionInitialization (\r
+S3Verification (\r
VOID\r
)\r
{\r
- FIRMWARE_CONFIG_ITEM Anchor;\r
- UINTN AnchorSize;\r
- SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
- UINT16 SmbiosVersion;\r
-\r
- if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
- &AnchorSize)) ||\r
- AnchorSize != sizeof QemuAnchor) {\r
- return;\r
+#if defined (MDE_CPU_X64)\r
+ if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
+ DEBUG ((EFI_D_ERROR,\r
+ "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
+ DEBUG ((EFI_D_ERROR,\r
+ "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
+ __FUNCTION__));\r
+ DEBUG ((EFI_D_ERROR,\r
+ "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
}\r
-\r
- QemuFwCfgSelectItem (Anchor);\r
- QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
- if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||\r
- CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
- return;\r
- }\r
-\r
- SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |\r
- QemuAnchor.MinorVersion);\r
- DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
- SmbiosVersion));\r
- PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
+#endif\r
}\r
\r
\r
mS3Supported = TRUE;\r
}\r
\r
+ S3Verification ();\r
BootModeInitialization ();\r
AddressWidthInitialization ();\r
\r
\r
if (mBootMode != BOOT_ON_S3_RESUME) {\r
ReserveEmuVariableNvStore ();\r
-\r
PeiFvInitialization ();\r
-\r
MemMapInitialization ();\r
-\r
- SmbiosVersionInitialization ();\r
+ NoexecDxeInitialization ();\r
}\r
\r
MiscInitialization ();\r
projects / mirror_edk2.git / blobdiff