OvmfPkg: factor the MMIO aperture shared by all PCI root bridges into PCDs

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 6735b50d703520a7a9cbe3d71ca8d29b5c84f59f..7d0941209f252bb5db0c1e0341081f567f1cf9a5 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -201,8 +201,8 @@ MemMapInitialization (
     EFI_RESOURCE_IO,\r
     EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
-    0xC000,\r
-    0x4000\r
+    PcdGet64 (PcdPciIoBase),\r
+    PcdGet64 (PcdPciIoSize)\r
     );\r
 \r
   //\r
@@ -213,6 +213,7 @@ MemMapInitialization (
   if (!mXen) {\r
     UINT32  TopOfLowRam;\r
     UINT32  PciBase;\r
+    UINT32  PciSize;\r
 \r
     TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
@@ -240,7 +241,10 @@ MemMapInitialization (
     // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
-    AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
+    PciSize = 0xFC000000 - PciBase;\r
+    AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
+    PcdSet64 (PcdPciMmio32Base, PciBase);\r
+    PcdSet64 (PcdPciMmio32Size, PciSize);\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r