OvmfPkg/Csm/LegacyBiosDxe: Update to make it build for OVMF

[mirror_edk2.git] / PcAtChipsetPkg / Include / Library / IoApicLib.h

diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h b/PcAtChipsetPkg/Include/Library/IoApicLib.h
index c3eb0ce4b3960ca4238b93b22fdf00583f73760e..200ef731fbef8a309c2aa948fb7d37344de51742 100644 (file)
--- a/PcAtChipsetPkg/Include/Library/IoApicLib.h
+++ b/PcAtChipsetPkg/Include/Library/IoApicLib.h
@@ -4,14 +4,8 @@
   I/O APIC library assumes I/O APIC is enabled. It does not\r
   handles cases where I/O APIC is disabled.\r
 \r
-  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 #ifndef __IO_APIC_LIB_H__\r
@@ -21,7 +15,7 @@
   Read a 32-bit I/O APIC register.\r
 \r
   If Index is >= 0x100, then ASSERT().\r
-  \r
+\r
   @param  Index  Specifies the I/O APIC register to read.\r
 \r
   @return  The 32-bit value read from the I/O APIC register specified by Index.\r
@@ -36,7 +30,7 @@ IoApicRead (
   Write a 32-bit I/O APIC register.\r
 \r
   If Index is >= 0x100, then ASSERT().\r
-  \r
+\r
   @param  Index  Specifies the I/O APIC register to write.\r
   @param  Value  Specifies the value to write to the I/O APIC register specified by Index.\r
 \r
@@ -52,8 +46,8 @@ IoApicWrite (
 /**\r
   Set the interrupt mask of an I/O APIC interrupt.\r
 \r
-  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r
-  \r
+  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().\r
+\r
   @param  Irq     Specifies the I/O APIC interrupt to enable or disable.\r
   @param  Enable  If TRUE, then enable the I/O APIC interrupt specified by Irq.\r
                   If FALSE, then disable the I/O APIC interrupt specified by Irq.\r
@@ -67,13 +61,13 @@ IoApicEnableInterrupt (
 \r
 /**\r
   Configures an I/O APIC interrupt.\r
-  \r
+\r
   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical\r
-  mode to the Local APIC of the currntly executing CPU.  The default state of the \r
+  mode to the Local APIC of the currntly executing CPU.  The default state of the\r
   entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must\r
   be used to enable(unmask) the I/O APIC Interrupt.\r
 \r
-  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r
+  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().\r
   If Vector >= 0x100, then ASSERT().\r
   If DeliveryMode is not supported, then ASSERT().\r
 \r