]> git.proxmox.com Git - mirror_edk2.git/blobdiff - QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h
QuarkPlatformPkg/PlatformFlashAccessLib: Add instance for update.
[mirror_edk2.git] / QuarkPlatformPkg / Feature / Capsule / Library / PlatformFlashAccessLib / SpiFlashDevice.h
diff --git a/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h
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+/** @file\r
+  SPI flash device header file.\r
+\r
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SPI_FLASH_DEVICE_H_\r
+#define _SPI_FLASH_DEVICE_H_\r
+\r
+#include <PiDxe.h>\r
+#include <Protocol/Spi.h>\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+\r
+//\r
+// Supported SPI Flash Devices\r
+//\r
+typedef enum {\r
+  EnumSpiFlash25L3205D,   // Macronix 32Mbit part\r
+  EnumSpiFlashW25Q32,     // Winbond 32Mbit part\r
+  EnumSpiFlashW25X32,     // Winbond 32Mbit part\r
+  EnumSpiFlashAT25DF321,  // Atmel 32Mbit part\r
+  EnumSpiFlashQH25F320,   // Intel 32Mbit part\r
+  EnumSpiFlash25VF064C,   // SST 64Mbit part\r
+  EnumSpiFlashM25PX64,    // NUMONYX 64Mbit part\r
+  EnumSpiFlashAT25DF641,  // Atmel 64Mbit part\r
+  EnumSpiFlashS25FL064K,  // Spansion 64Mbit part\r
+  EnumSpiFlash25L6405D,   // Macronix 64Mbit part\r
+  EnumSpiFlashW25Q64,     // Winbond 64Mbit part\r
+  EnumSpiFlashW25X64,     // Winbond 64Mbit part\r
+  EnumSpiFlashQH25F640,   // Intel 64Mbit part\r
+  EnumSpiFlashMax\r
+} SPI_FLASH_TYPES_SUPPORTED;\r
+\r
+//\r
+// Flash Device commands\r
+//\r
+// If a supported device uses a command different from the list below, a device specific command\r
+// will be defined just below it's JEDEC id section.\r
+//\r
+#define SPI_COMMAND_WRITE                 0x02\r
+#define SPI_COMMAND_WRITE_AAI             0xAD\r
+#define SPI_COMMAND_READ                  0x03\r
+#define SPI_COMMAND_ERASE                 0x20\r
+#define SPI_COMMAND_WRITE_DISABLE         0x04\r
+#define SPI_COMMAND_READ_S                0x05\r
+#define SPI_COMMAND_WRITE_ENABLE          0x06\r
+#define SPI_COMMAND_READ_ID               0xAB\r
+#define SPI_COMMAND_JEDEC_ID              0x9F\r
+#define SPI_COMMAND_WRITE_S_EN            0x50\r
+#define SPI_COMMAND_WRITE_S               0x01\r
+#define SPI_COMMAND_CHIP_ERASE            0xC7\r
+#define SPI_COMMAND_BLOCK_ERASE           0xD8\r
+\r
+//\r
+// Flash JEDEC device ids\r
+//\r
+// SST 8Mbit part\r
+//\r
+#define SPI_SST25VF080B_ID1               0xBF\r
+#define SPI_SST25VF080B_ID2               0x25\r
+#define SPI_SST25VF080B_ID3               0x8E\r
+//\r
+// SST 16Mbit part\r
+//\r
+#define SPI_SST25VF016B_ID1               0xBF\r
+#define SPI_SST25VF016B_ID2               0x25\r
+#define SPI_SST25V016BF_ID3               0x41\r
+//\r
+// Macronix 32Mbit part\r
+//\r
+// MX25 part does not support WRITE_AAI comand (0xAD)\r
+//\r
+#define SPI_MX25L3205_ID1                 0xC2\r
+#define SPI_MX25L3205_ID2                 0x20\r
+#define SPI_MX25L3205_ID3                 0x16\r
+//\r
+// Intel 32Mbit part bottom boot\r
+//\r
+#define SPI_QH25F320_ID1                  0x89\r
+#define SPI_QH25F320_ID2                  0x89\r
+#define SPI_QH25F320_ID3                  0x12  // 32Mbit bottom boot\r
+//\r
+// Intel 64Mbit part bottom boot\r
+//\r
+#define SPI_QH25F640_ID1                  0x89\r
+#define SPI_QH25F640_ID2                  0x89\r
+#define SPI_QH25F640_ID3                  0x13  // 64Mbit bottom boot\r
+//\r
+// QH part does not support command 0x20 for erase; only 0xD8 (sector erase)\r
+// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)\r
+// 0x40 command ignored if address outside of parameter block range\r
+//\r
+#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40\r
+//\r
+// Winbond 32Mbit part\r
+//\r
+#define SPI_W25X32_ID1                    0xEF\r
+#define SPI_W25X32_ID2                    0x30  // Memory Type\r
+#define SPI_W25X32_ID3                    0x16  // Capacity\r
+#define SF_DEVICE_ID1_W25Q32              0x16\r
+\r
+//\r
+// Winbond 64Mbit part\r
+//\r
+#define SPI_W25X64_ID1                    0xEF\r
+#define SPI_W25X64_ID2                    0x30  // Memory Type\r
+#define SPI_W25X64_ID3                    0x17  // Capacity\r
+#define SF_DEVICE_ID0_W25QXX              0x40\r
+#define SF_DEVICE_ID1_W25Q64              0x17\r
+//\r
+// Winbond 128Mbit part\r
+//\r
+#define SF_DEVICE_ID0_W25Q128             0x40\r
+#define SF_DEVICE_ID1_W25Q128             0x18\r
+\r
+//\r
+// Atmel 32Mbit part\r
+//\r
+#define SPI_AT26DF321_ID1                 0x1F\r
+#define SPI_AT26DF321_ID2                 0x47  // [7:5]=Family, [4:0]=Density\r
+#define SPI_AT26DF321_ID3                 0x00\r
+\r
+#define SF_VENDOR_ID_ATMEL                0x1F\r
+#define SF_DEVICE_ID0_AT25DF641           0x48\r
+#define SF_DEVICE_ID1_AT25DF641           0x00\r
+\r
+//\r
+// SST 8Mbit part\r
+//\r
+#define SPI_SST25VF080B_ID1               0xBF\r
+#define SPI_SST25VF080B_ID2               0x25\r
+#define SPI_SST25VF080B_ID3               0x8E\r
+#define SF_DEVICE_ID0_25VF064C            0x25\r
+#define SF_DEVICE_ID1_25VF064C            0x4B\r
+\r
+//\r
+// SST 16Mbit part\r
+//\r
+#define SPI_SST25VF016B_ID1               0xBF\r
+#define SPI_SST25VF016B_ID2               0x25\r
+#define SPI_SST25V016BF_ID3               0x41\r
+\r
+//\r
+// Winbond 32Mbit part\r
+//\r
+#define SPI_W25X32_ID1                    0xEF\r
+#define SPI_W25X32_ID2                    0x30  // Memory Type\r
+#define SPI_W25X32_ID3                    0x16  // Capacity\r
+\r
+#define  SF_VENDOR_ID_MX             0xC2\r
+#define  SF_DEVICE_ID0_25L6405D      0x20\r
+#define  SF_DEVICE_ID1_25L6405D      0x17\r
+\r
+#define  SF_VENDOR_ID_NUMONYX        0x20\r
+#define  SF_DEVICE_ID0_M25PX64       0x71\r
+#define  SF_DEVICE_ID1_M25PX64       0x17\r
+\r
+//\r
+// Spansion 64Mbit part\r
+//\r
+#define SF_VENDOR_ID_SPANSION             0xEF\r
+#define SF_DEVICE_ID0_S25FL064K           0x40\r
+#define SF_DEVICE_ID1_S25FL064K           0x00\r
+\r
+//\r
+// index for prefix opcodes\r
+//\r
+#define SPI_WREN_INDEX                    0   // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE\r
+#define SPI_EWSR_INDEX                    1   // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN\r
+#define BIOS_CTRL                         0xDC\r
+\r
+#define PFAB_CARD_DEVICE_ID               0x5150\r
+#define PFAB_CARD_VENDOR_ID               0x8086\r
+#define PFAB_CARD_SETUP_REGISTER          0x40\r
+#define PFAB_CARD_SETUP_BYTE              0x0d\r
+\r
+\r
+#endif\r