+++ /dev/null
-/** @file\r
-Essential platform configuration.\r
-\r
-Copyright (c) 2013 Intel Corporation.\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-**/\r
-\r
-#include "PlatformInitDxe.h"\r
-\r
-//\r
-// The protocols, PPI and GUID defintions for this module\r
-//\r
-\r
-//\r
-// The Library classes this module consumes\r
-//\r
-\r
-//\r
-// RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE\r
-// Workaround to make default SMRAM UnCachable\r
-//\r
-#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address\r
-#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM\r
-\r
-BOOLEAN mMemCfgDone = FALSE;\r
-UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};\r
-\r
-VOID\r
-EFIAPI\r
-PlatformInitializeUart0MuxGalileo (\r
- VOID\r
- )\r
-/*++\r
-\r
-\r
-Routine Description:\r
-\r
- This is the routine to initialize UART0 for DBG2 support. The hardware used in this process is a\r
- Legacy Bridge (Legacy GPIO), I2C controller, a bi-directional MUX and a Cypress CY8C9540A chip.\r
-\r
-Arguments:\r
-\r
- None.\r
-\r
-Returns:\r
-\r
- None.\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress;\r
- UINTN Length;\r
- UINT8 Buffer[2];\r
-\r
- if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {\r
- I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR;\r
- } else {\r
- I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR;\r
- }\r
-\r
- //\r
- // Set GPIO_SUS<2> as an output, raise voltage to Vdd.\r
- //\r
- PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, 2, TRUE);\r
-\r
- //\r
- // Select Port 3\r
- //\r
- Length = 2;\r
- Buffer[0] = 0x18; //sub-address\r
- Buffer[1] = 0x03; //data\r
-\r
- Status = I2cWriteMultipleByte (\r
- I2CSlaveAddress,\r
- EfiI2CSevenBitAddrMode,\r
- &Length,\r
- &Buffer\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Set "Pin Direction" bit4 and bit5 as outputs\r
- //\r
- Length = 2;\r
- Buffer[0] = 0x1C; //sub-address\r
- Buffer[1] = 0xCF; //data\r
-\r
- Status = I2cWriteMultipleByte (\r
- I2CSlaveAddress,\r
- EfiI2CSevenBitAddrMode,\r
- &Length,\r
- &Buffer\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Lower GPORT3 bit4 and bit5 to Vss\r
- //\r
- Length = 2;\r
- Buffer[0] = 0x0B; //sub-address\r
- Buffer[1] = 0xCF; //data\r
-\r
- Status = I2cWriteMultipleByte (\r
- I2CSlaveAddress,\r
- EfiI2CSevenBitAddrMode,\r
- &Length,\r
- &Buffer\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-PlatformInitializeUart0MuxGalileoGen2 (\r
- VOID\r
- )\r
-/*++\r
-\r
-\r
-Routine Description:\r
-\r
- This is the routine to initialize UART0 on GalileoGen2. The hardware used in this process is\r
- I2C controller and the configuring the following IO Expander signal.\r
-\r
- EXP1.P1_5 should be configured as an output & driven high.\r
- EXP1.P0_0 should be configured as an output & driven high.\r
- EXP0.P1_4 should be configured as an output, driven low.\r
- EXP1.P0_1 pullup should be disabled.\r
- EXP0.P1_5 Pullup should be disabled.\r
-\r
-Arguments:\r
-\r
- None.\r
-\r
-Returns:\r
-\r
- None.\r
-\r
---*/\r
-\r
-{\r
- //\r
- // EXP1.P1_5 should be configured as an output & driven high.\r
- //\r
- PlatformPcal9555GpioSetDir (\r
- GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
- 13, // P1-5.\r
- TRUE\r
- );\r
- PlatformPcal9555GpioSetLevel (\r
- GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
- 13, // P1-5.\r
- TRUE\r
- );\r
-\r
- //\r
- // EXP1.P0_0 should be configured as an output & driven high.\r
- //\r
- PlatformPcal9555GpioSetDir (\r
- GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
- 0, // P0_0.\r
- TRUE\r
- );\r
- PlatformPcal9555GpioSetLevel (\r
- GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
- 0, // P0_0.\r
- TRUE\r
- );\r
-\r
- //\r
- // EXP0.P1_4 should be configured as an output, driven low.\r
- //\r
- PlatformPcal9555GpioSetDir (\r
- GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
- 12, // P1-4.\r
- FALSE\r
- );\r
- PlatformPcal9555GpioSetLevel ( // IO Expander 0.\r
- GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // P1-4\r
- 12,\r
- FALSE\r
- );\r
-\r
- //\r
- // EXP1.P0_1 pullup should be disabled.\r
- //\r
- PlatformPcal9555GpioDisablePull (\r
- GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
- 1 // P0-1.\r
- );\r
-\r
- //\r
- // EXP0.P1_5 Pullup should be disabled.\r
- //\r
- PlatformPcal9555GpioDisablePull (\r
- GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
- 13 // P1-5.\r
- );\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-PlatformConfigOnSmmConfigurationProtocol (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Function runs in PI-DXE to perform platform specific config when\r
- SmmConfigurationProtocol is installed.\r
-\r
-Arguments:\r
- Event - The event that occured.\r
- Context - For EFI compatiblity. Not used.\r
-\r
-Returns:\r
- None.\r
---*/\r
-\r
-{\r
- EFI_STATUS Status;\r
- UINT32 NewValue;\r
- UINT64 BaseAddress;\r
- UINT64 SmramLength;\r
- VOID *SmmCfgProt;\r
-\r
- Status = gBS->LocateProtocol (&gEfiSmmConfigurationProtocolGuid, NULL, &SmmCfgProt);\r
- if (Status != EFI_SUCCESS){\r
- DEBUG ((DEBUG_INFO, "gEfiSmmConfigurationProtocolGuid triggered but not valid.\n"));\r
- return;\r
- }\r
- if (mMemCfgDone) {\r
- DEBUG ((DEBUG_INFO, "Platform DXE Mem config already done.\n"));\r
- return;\r
- }\r
-\r
- //\r
- // Disable eSram block (this will also clear/zero eSRAM)\r
- // We only use eSRAM in the PEI phase. Disable now that we are in the DXE phase\r
- //\r
- NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK);\r
- NewValue |= BLOCK_DISABLE_PG;\r
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue);\r
-\r
- //\r
- // Update HMBOUND to top of DDR3 memory and LOCK\r
- // We disabled eSRAM so now we move HMBOUND down to top of DDR3\r
- //\r
- QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength);\r
- NewValue = (UINT32)(BaseAddress + SmramLength);\r
- DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));\r
- QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));\r
-\r
- //\r
- // Lock IMR5 now that HMBOUND is locked (legacy S3 region)\r
- //\r
- NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL);\r
- NewValue |= IMR_LOCK;\r
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);\r
-\r
- //\r
- // Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved)\r
- //\r
- NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL);\r
- NewValue |= IMR_LOCK;\r
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);\r
-\r
- //\r
- // Disable IMR2 memory protection (RMU Main Binary)\r
- //\r
- QncImrWrite (\r
- QUARK_NC_MEMORY_MANAGER_IMR2,\r
- (UINT32)(IMRL_RESET & ~IMR_EN),\r
- (UINT32)IMRH_RESET,\r
- (UINT32)IMRX_ALL_ACCESS,\r
- (UINT32)IMRX_ALL_ACCESS\r
- );\r
-\r
- //\r
- // Disable IMR3 memory protection (Default SMRAM)\r
- //\r
- QncImrWrite (\r
- QUARK_NC_MEMORY_MANAGER_IMR3,\r
- (UINT32)(IMRL_RESET & ~IMR_EN),\r
- (UINT32)IMRH_RESET,\r
- (UINT32)IMRX_ALL_ACCESS,\r
- (UINT32)IMRX_ALL_ACCESS\r
- );\r
-\r
- //\r
- // Disable IMR4 memory protection (eSRAM).\r
- //\r
- QncImrWrite (\r
- QUARK_NC_MEMORY_MANAGER_IMR4,\r
- (UINT32)(IMRL_RESET & ~IMR_EN),\r
- (UINT32)IMRH_RESET,\r
- (UINT32)IMRX_ALL_ACCESS,\r
- (UINT32)IMRX_ALL_ACCESS\r
- );\r
-\r
- //\r
- // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE\r
- // Workaround to make default SMRAM UnCachable\r
- //\r
- Status = gDS->SetMemorySpaceAttributes (\r
- (EFI_PHYSICAL_ADDRESS) SMM_DEFAULT_SMBASE,\r
- SMM_DEFAULT_SMBASE_SIZE_BYTES,\r
- EFI_MEMORY_WB\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- mMemCfgDone = TRUE;\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-PlatformConfigOnSpiReady (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Function runs in PI-DXE to perform platform specific config when SPI\r
- interface is ready.\r
-\r
-Arguments:\r
- Event - The event that occured.\r
- Context - For EFI compatiblity. Not used.\r
-\r
-Returns:\r
- None.\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
- VOID *SpiReadyProt = NULL;\r
- EFI_PLATFORM_TYPE Type;\r
- EFI_BOOT_MODE BootMode;\r
-\r
- BootMode = GetBootModeHob ();\r
-\r
- Status = gBS->LocateProtocol (&gEfiSmmSpiReadyProtocolGuid, NULL, &SpiReadyProt);\r
- if (Status != EFI_SUCCESS){\r
- DEBUG ((DEBUG_INFO, "gEfiSmmSpiReadyProtocolGuid triggered but not valid.\n"));\r
- return;\r
- }\r
-\r
- //\r
- // Lock regions SPI flash.\r
- //\r
- PlatformFlashLockPolicy (FALSE);\r
-\r
- //\r
- // Configurations and checks to be done when DXE tracing available.\r
- //\r
-\r
- //\r
- // Platform specific Signal routing.\r
- //\r
-\r
- //\r
- // Skip any signal not needed for recovery and flash update.\r
- //\r
- if (BootMode != BOOT_ON_FLASH_UPDATE && BootMode != BOOT_IN_RECOVERY_MODE) {\r
-\r
- //\r
- // Galileo Platform UART0 support.\r
- //\r
- Type = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);\r
- if (Type == Galileo) {\r
- //\r
- // Use MUX to connect out UART0 pins.\r
- //\r
- PlatformInitializeUart0MuxGalileo ();\r
- }\r
-\r
- //\r
- // GalileoGen2 Platform UART0 support.\r
- //\r
- if (Type == GalileoGen2) {\r
- //\r
- // Use route out UART0 pins.\r
- //\r
- PlatformInitializeUart0MuxGalileoGen2 ();\r
- }\r
- }\r
-}\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CreateConfigEvents (\r
- VOID\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
- None\r
-\r
-Returns:\r
- EFI_STATUS\r
-\r
---*/\r
-{\r
- EFI_EVENT EventSmmCfg;\r
- EFI_EVENT EventSpiReady;\r
- VOID *RegistrationSmmCfg;\r
- VOID *RegistrationSpiReady;\r
-\r
- //\r
- // Schedule callback for when SmmConfigurationProtocol installed.\r
- //\r
- EventSmmCfg = EfiCreateProtocolNotifyEvent (\r
- &gEfiSmmConfigurationProtocolGuid,\r
- TPL_CALLBACK,\r
- PlatformConfigOnSmmConfigurationProtocol,\r
- NULL,\r
- &RegistrationSmmCfg\r
- );\r
- ASSERT (EventSmmCfg != NULL);\r
-\r
- //\r
- // Schedule callback to setup SPI Flash Policy when SPI interface ready.\r
- //\r
- EventSpiReady = EfiCreateProtocolNotifyEvent (\r
- &gEfiSmmSpiReadyProtocolGuid,\r
- TPL_CALLBACK,\r
- PlatformConfigOnSpiReady,\r
- NULL,\r
- &RegistrationSpiReady\r
- );\r
- ASSERT (EventSpiReady != NULL);\r
- return EFI_SUCCESS;\r
-}\r
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