--- /dev/null
+## @file\r
+# This is the Platform PEIM to initialize whole platform on PEI phase.\r
+#\r
+# This PEIM includes 3 parts, pre memory initialization, MRC\r
+# wrapper and post memory initialization.\r
+# On pre memory, following action is performed,\r
+# 1. Initizluize GMCH.\r
+# 2. Detect boot mode.\r
+# 3. Detect video adapter to determine whether we need pre allocated\r
+# memory.\r
+#\r
+# After that MRC wrapper calls MRC to initialize memory and install a PPI\r
+# notify to do post memory\r
+# initialization. MRC wrapper performance following actions,\r
+# 1. Install EFI Memory.\r
+# 2. Create HOB of system memory.\r
+#\r
+# On post memory, following action is performed,\r
+# 1. QNC initialization after MRC.\r
+# 2. SIO initialization.\r
+# 3. Install ResetSystem and FinvFv PPI, relocate Stall to memory on\r
+# recovery boot mode.\r
+# 4. Set MTRR for PEI\r
+# 5. Create FV HOB and Flash HOB\r
+# 6. Install RecoveryModule and AtaController PPI if on recovery boot mode.\r
+#\r
+# This PEIM does not have any register access directly, it depends on\r
+# IntelQNCLib, QNCAccess libraries to access Chipset\r
+# registers.\r
+#\r
+# Platform.c - Provide main flow and entrypoint of PEIM.\r
+# MemoryCallback.c - Includes a memory call back function notified when\r
+# MRC is done.\r
+# Recovery.c - provides the platform recoveyr functionality.\r
+# MrcWrapper.c - Contains the logic to call MRC PPI and do Framework\r
+# memory specific stuff like build memory map, build\r
+# resource description hob for DXE phase,etc.\r
+# Bootmode.c - Detect boot mode.\r
+# Copyright (c) 2013 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformEarlyInitPei\r
+ FILE_GUID = 9618C0DC-50A4-496c-994F-7241F282ED01\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = PeiInitPlatform\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ Generic/Recovery.c\r
+ PlatformErratas.c\r
+ MrcWrapper.c\r
+ MrcWrapper.h\r
+ PlatformEarlyInit.c\r
+ PlatformEarlyInit.h\r
+ MemoryCallback.c\r
+ BootMode.c\r
+ CommonHeader.h\r
+ PeiFvSecurity.c\r
+ PeiFvSecurity.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+\r
+[LibraryClasses]\r
+ ResetSystemLib\r
+ PrintLib\r
+ TimerLib\r
+ RecoveryOemHookLib\r
+ PcdLib\r
+ IntelQNCLib\r
+ ReportStatusCodeLib\r
+ PciLib\r
+ PciExpressLib\r
+ IoLib\r
+ PciCf8Lib\r
+ HobLib\r
+ BaseMemoryLib\r
+ PeiServicesTablePointerLib\r
+ PeiServicesLib\r
+ BaseLib\r
+ PeimEntryPoint\r
+ DebugLib\r
+ MemoryAllocationLib\r
+ PerformanceLib\r
+ CacheMaintenanceLib\r
+ MtrrLib\r
+ QNCAccessLib\r
+ PlatformHelperLib\r
+ PlatformPcieHelperLib\r
+\r
+[Guids]\r
+ gEfiMemoryConfigDataGuid # ALWAYS_CONSUMED L"MemoryConfig"\r
+ gEfiAcpiVariableGuid # ALWAYS_CONSUMED L"AcpiGlobalVariab"\r
+ gEfiMemoryTypeInformationGuid # ALWAYS_CONSUMED L"MemoryTypeInformation"\r
+ gEfiMemoryConfigDataGuid # SOMETIMES_PRODUCED Hob: GUID_EXTENSION\r
+ gEfiSmmPeiSmramMemoryReserveGuid # ALWAYS_PRODUCED Hob: GUID_EXTENSION\r
+ gEfiFirmwareFileSystem2Guid # ALWAYS_CONSUMED\r
+ gEfiCapsuleGuid # ALWAYS_CONSUMED\r
+ gPeiCapsuleOnDataCDGuid\r
+ gPeiCapsuleOnFatIdeDiskGuid\r
+ gPeiCapsuleOnFatUsbDiskGuid\r
+ gEfiMemoryOverwriteControlDataGuid # SOMETIMES_CONSUMED\r
+ gEfiQuarkCapsuleGuid\r
+\r
+[Ppis]\r
+ gQNCMemoryInitPpiGuid # PPI ALWAYS_CONSUMED\r
+ gEfiPeiMemoryDiscoveredPpiGuid # PPI ALWAYS_PRODUCED\r
+ gPeiAtaControllerPpiGuid # PPI SOMETIMES_PRODUCED\r
+ gEfiPeiStallPpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPeiDeviceRecoveryModulePpiGuid # PPI SOMETIMES_CONSUMED\r
+ gEfiPeiRecoveryModulePpiGuid # PPI SOMETIMES_PRODUCED\r
+ gEfiPeiResetPpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPeiReadOnlyVariable2PpiGuid # PPI ALWAYS_CONSUMED\r
+ gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED\r
+ gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPeiFirmwareVolumeInfoPpiGuid\r
+ gEfiEndOfPeiSignalPpiGuid\r
+ gEfiPeiVirtualBlockIoPpiGuid\r
+ gPeiCapsulePpiGuid # PPI ALWAYS_CONSUMED\r
+\r
+[FeaturePcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatUsbDisk\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport\r
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubBlkSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashQNCMicrocodeSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1\r
+\r
+[Depex]\r
+ gEfiPeiReadOnlyVariable2PpiGuid AND gQNCMemoryInitPpiGuid\r
projects / mirror_edk2.git / blobdiff