--- /dev/null
+/** @file\r
+This file contains the definination for host controller\r
+register operation routines.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+#ifndef _OHCI_REG_H\r
+#define _OHCI_REG_H\r
+\r
+#define HC_STATE_RESET 0x0\r
+#define HC_STATE_RESUME 0x1\r
+#define HC_STATE_OPERATIONAL 0x2\r
+#define HC_STATE_SUSPEND 0x3\r
+\r
+#define PERIODIC_ENABLE 0x01\r
+#define ISOCHRONOUS_ENABLE 0x02\r
+#define CONTROL_ENABLE 0x04\r
+#define BULK_ENABLE 0x08\r
+#define CONTROL_BULK_RATIO 0x10\r
+\r
+#define HC_FUNCTIONAL_STATE 0x20\r
+#define INTERRUPT_ROUTING 0x40\r
+\r
+#define HC_RESET 0x01\r
+#define CONTROL_LIST_FILLED 0x02\r
+#define BULK_LIST_FILLED 0x04\r
+#define CHANGE_OWNER_REQUEST 0x08\r
+\r
+#define SCHEDULE_OVERRUN_COUNT 0x10\r
+\r
+#define SCHEDULE_OVERRUN 0x00001\r
+#define WRITEBACK_DONE_HEAD 0x00002\r
+#define START_OF_FRAME 0x00004\r
+#define RESUME_DETECT 0x00008\r
+#define UNRECOVERABLE_ERROR 0x00010\r
+#define FRAME_NUMBER_OVERFLOW 0x00020\r
+#define ROOTHUB_STATUS_CHANGE 0x00040\r
+#define OWNERSHIP_CHANGE 0x00080\r
+\r
+#define MASTER_INTERRUPT 0x00400\r
+\r
+#define CONTROL_HEAD 0x001\r
+#define BULK_HEAD 0x002\r
+#define DONE_HEAD 0x004\r
+\r
+#define Hc_HCCA 0x001\r
+#define Hc_PERIODIC_CURRENT 0x002\r
+#define Hc_CONTOL_HEAD 0x004\r
+#define Hc_CONTROL_CURRENT_PTR 0x008\r
+#define Hc_BULK_HEAD 0x010\r
+#define Hc_BULK_CURRENT_PTR 0x020\r
+#define Hc_DONE_HEAD 0x040\r
+\r
+#define FRAME_INTERVAL 0x008\r
+#define FS_LARGEST_DATA_PACKET 0x010\r
+#define FRMINT_TOGGLE 0x020\r
+#define FRAME_REMAINING 0x040\r
+#define FRAME_REMAIN_TOGGLE 0x080\r
+\r
+#define RH_DESC_A 0x00001\r
+#define RH_DESC_B 0x00002\r
+#define RH_NUM_DS_PORTS 0x00004\r
+#define RH_NO_PSWITCH 0x00008\r
+#define RH_PSWITCH_MODE 0x00010\r
+#define RH_DEVICE_TYPE 0x00020\r
+#define RH_OC_PROT_MODE 0x00040\r
+#define RH_NOC_PROT 0x00080\r
+#define RH_POTPGT 0x00100\r
+#define RH_NO_POTPGT 0x00200\r
+#define RH_DEV_REMOVABLE 0x00400\r
+#define RH_PORT_PWR_CTRL_MASK 0x00800\r
+\r
+#define RH_LOCAL_PSTAT 0x00001\r
+#define RH_OC_ID 0x00002\r
+#define RH_REMOTE_WK_ENABLE 0x00004\r
+#define RH_LOCAL_PSTAT_CHANGE 0x00008\r
+#define RH_OC_ID_CHANGE 0x00010\r
+#define RH_CLR_RMT_WK_ENABLE 0x00020\r
+\r
+#define RH_CLEAR_PORT_ENABLE 0x0001\r
+#define RH_SET_PORT_ENABLE 0x0002\r
+#define RH_SET_PORT_SUSPEND 0x0004\r
+#define RH_CLEAR_SUSPEND_STATUS 0x0008\r
+#define RH_SET_PORT_RESET 0x0010\r
+#define RH_SET_PORT_POWER 0x0020\r
+#define RH_CLEAR_PORT_POWER 0x0040\r
+#define RH_CONNECT_STATUS_CHANGE 0x10000\r
+#define RH_PORT_ENABLE_STAT_CHANGE 0x20000\r
+#define RH_PORT_SUSPEND_STAT_CHANGE 0x40000\r
+#define RH_OC_INDICATOR_CHANGE 0x80000\r
+#define RH_PORT_RESET_STAT_CHANGE 0x100000\r
+\r
+#define RH_CURR_CONNECT_STAT 0x0001\r
+#define RH_PORT_ENABLE_STAT 0x0002\r
+#define RH_PORT_SUSPEND_STAT 0x0004\r
+#define RH_PORT_OC_INDICATOR 0x0008\r
+#define RH_PORT_RESET_STAT 0x0010\r
+#define RH_PORT_POWER_STAT 0x0020\r
+#define RH_LSDEVICE_ATTACHED 0x0040\r
+\r
+#define RESET_SYSTEM_BUS (1 << 0)\r
+#define RESET_HOST_CONTROLLER (1 << 1)\r
+#define RESET_CLOCK_GENERATION (1 << 2)\r
+#define RESET_SSE_GLOBAL (1 << 5)\r
+#define RESET_PSPL (1 << 6)\r
+#define RESET_PCPL (1 << 7)\r
+#define RESET_SSEP1 (1 << 9)\r
+#define RESET_SSEP2 (1 << 10)\r
+#define RESET_SSEP3 (1 << 11)\r
+\r
+#define ONE_SECOND 1000000\r
+#define ONE_MILLI_SEC 1000\r
+#define MAX_BYTES_PER_TD 0x1000\r
+#define MAX_RETRY_TIMES 100\r
+#define PORT_NUMBER_ON_MAINSTONE2 1\r
+\r
+\r
+//\r
+// Operational Register Offsets\r
+//\r
+\r
+//\r
+// Command & Status Registers Offsets\r
+//\r
+#define HC_REVISION 0x00\r
+#define HC_CONTROL 0x04\r
+#define HC_COMMAND_STATUS 0x08\r
+#define HC_INTERRUPT_STATUS 0x0C\r
+#define HC_INTERRUPT_ENABLE 0x10\r
+#define HC_INTERRUPT_DISABLE 0x14\r
+\r
+//\r
+// Memory Pointer Offsets\r
+//\r
+#define HC_HCCA 0x18\r
+#define HC_PERIODIC_CURRENT 0x1C\r
+#define HC_CONTROL_HEAD 0x20\r
+#define HC_CONTROL_CURRENT_PTR 0x24\r
+#define HC_BULK_HEAD 0x28\r
+#define HC_BULK_CURRENT_PTR 0x2C\r
+#define HC_DONE_HEAD 0x30\r
+\r
+//\r
+// Frame Register Offsets\r
+//\r
+#define HC_FRM_INTERVAL 0x34\r
+#define HC_FRM_REMAINING 0x38\r
+#define HC_FRM_NUMBER 0x3C\r
+#define HC_PERIODIC_START 0x40\r
+#define HC_LS_THREASHOLD 0x44\r
+\r
+//\r
+// Root Hub Register Offsets\r
+//\r
+#define HC_RH_DESC_A 0x48\r
+#define HC_RH_DESC_B 0x4C\r
+#define HC_RH_STATUS 0x50\r
+#define HC_RH_PORT_STATUS 0x54\r
+\r
+#define USBHOST_OFFSET_UHCHR 0x64 // Usb Host reset register\r
+\r
+#define OHC_BAR_INDEX 0\r
+\r
+//\r
+// Usb Host controller register offset\r
+//\r
+#define USBHOST_OFFSET_UHCREV 0x0 // Usb Host revision register\r
+#define USBHOST_OFFSET_UHCHCON 0x4 // Usb Host control register\r
+#define USBHOST_OFFSET_UHCCOMS 0x8 // Usb Host Command Status register\r
+#define USBHOST_OFFSET_UHCINTS 0xC // Usb Host Interrupt Status register\r
+#define USBHOST_OFFSET_UHCINTE 0x10 // Usb Host Interrupt Enable register\r
+#define USBHOST_OFFSET_UHCINTD 0x14 // Usb Host Interrupt Disable register\r
+#define USBHOST_OFFSET_UHCHCCA 0x18 // Usb Host Controller Communication Area\r
+#define USBHOST_OFFSET_UHCPCED 0x1C // Usb Host Period Current Endpoint Descriptor\r
+#define USBHOST_OFFSET_UHCCHED 0x20 // Usb Host Control Head Endpoint Descriptor\r
+#define USBHOST_OFFSET_UHCCCED 0x24 // Usb Host Control Current Endpoint Descriptor\r
+#define USBHOST_OFFSET_UHCBHED 0x28 // Usb Host Bulk Head Endpoint Descriptor\r
+#define USBHOST_OFFSET_UHCBCED 0x2C // Usb Host Bulk Current Endpoint Descriptor\r
+#define USBHOST_OFFSET_UHCDHEAD 0x30 // Usb Host Done Head register\r
+#define USBHOST_OFFSET_UHCFMI 0x34 // Usb Host Frame Interval register\r
+#define USBHOST_OFFSET_UHCFMR 0x38 // Usb Host Frame Remaining register\r
+#define USBHOST_OFFSET_UHCFMN 0x3C // Usb Host Frame Number register\r
+#define USBHOST_OFFSET_UHCPERS 0x40 // Usb Host Periodic Start register\r
+#define USBHOST_OFFSET_UHCLST 0x44 // Usb Host Low-Speed Threshold register\r
+#define USBHOST_OFFSET_UHCRHDA 0x48 // Usb Host Root Hub Descriptor A register\r
+#define USBHOST_OFFSET_UHCRHDB 0x4C // Usb Host Root Hub Descriptor B register\r
+#define USBHOST_OFFSET_UHCRHS 0x50 // Usb Host Root Hub Status register\r
+#define USBHOST_OFFSET_UHCRHPS1 0x54 // Usb Host Root Hub Port Status 1 register\r
+\r
+//\r
+// Usb Host controller register bit fields\r
+//\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ UINT8 ProgInterface;\r
+ UINT8 SubClassCode;\r
+ UINT8 BaseCode;\r
+} USB_CLASSC;\r
+\r
+typedef struct {\r
+ UINT32 Revision:8;\r
+ UINT32 Rsvd:24;\r
+} HcREVISION;\r
+\r
+typedef struct {\r
+ UINT32 ControlBulkRatio:2;\r
+ UINT32 PeriodicEnable:1;\r
+ UINT32 IsochronousEnable:1;\r
+ UINT32 ControlEnable:1;\r
+ UINT32 BulkEnable:1;\r
+ UINT32 FunctionalState:2;\r
+ UINT32 InterruptRouting:1;\r
+ UINT32 RemoteWakeup:1;\r
+ UINT32 RemoteWakeupEnable:1;\r
+ UINT32 Reserved:21;\r
+} HcCONTROL;\r
+\r
+typedef struct {\r
+ UINT32 HcReset:1;\r
+ UINT32 ControlListFilled:1;\r
+ UINT32 BulkListFilled:1;\r
+ UINT32 ChangeOwnerRequest:1;\r
+ UINT32 Reserved1:12;\r
+ UINT32 ScheduleOverrunCount:2;\r
+ UINT32 Reserved:14;\r
+} HcCOMMAND_STATUS;\r
+\r
+typedef struct {\r
+ UINT32 SchedulingOverrun:1;\r
+ UINT32 WriteBackDone:1;\r
+ UINT32 Sof:1;\r
+ UINT32 ResumeDetected:1;\r
+ UINT32 UnrecoverableError:1;\r
+ UINT32 FrameNumOverflow:1;\r
+ UINT32 RHStatusChange:1;\r
+ UINT32 Reserved1:23;\r
+ UINT32 OwnerChange:1;\r
+ UINT32 Reserved2:1;\r
+} HcINTERRUPT_STATUS;\r
+\r
+typedef struct {\r
+ UINT32 SchedulingOverrunInt:1;\r
+ UINT32 WriteBackDoneInt:1;\r
+ UINT32 SofInt:1;\r
+ UINT32 ResumeDetectedInt:1;\r
+ UINT32 UnrecoverableErrorInt:1;\r
+ UINT32 FrameNumOverflowInt:1;\r
+ UINT32 RHStatusChangeInt:1;\r
+ UINT32 Reserved:23;\r
+ UINT32 OwnerChangedInt:1;\r
+ UINT32 MasterInterruptEnable:1;\r
+} HcINTERRUPT_CONTROL;\r
+\r
+typedef struct {\r
+ UINT32 Rerserved:8;\r
+ UINT32 Hcca:24;\r
+} HcHCCA;\r
+\r
+typedef struct {\r
+ UINT32 Reserved:4;\r
+ UINT32 MemoryPtr:28;\r
+} HcMEMORY_PTR;\r
+\r
+typedef struct {\r
+ UINT32 FrameInterval:14;\r
+ UINT32 Reserved:2;\r
+ UINT32 FSMaxDataPacket:15;\r
+ UINT32 FrmIntervalToggle:1;\r
+} HcFRM_INTERVAL;\r
+\r
+typedef struct {\r
+ UINT32 FrameRemaining:14;\r
+ UINT32 Reserved:17;\r
+ UINT32 FrameRemainingToggle:1;\r
+} HcFRAME_REMAINING;\r
+\r
+typedef struct {\r
+ UINT32 FrameNumber:16;\r
+ UINT32 Reserved:16;\r
+} HcFRAME_NUMBER;\r
+\r
+typedef struct {\r
+ UINT32 PeriodicStart:14;\r
+ UINT32 Reserved:18;\r
+} HcPERIODIC_START;\r
+\r
+typedef struct {\r
+ UINT32 LsThreshold:12;\r
+ UINT32 Reserved:20;\r
+} HcLS_THRESHOLD;\r
+\r
+typedef struct {\r
+ UINT32 NumDownStrmPorts:8;\r
+ UINT32 PowerSwitchMode:1;\r
+ UINT32 NoPowerSwitch:1;\r
+ UINT32 DeviceType:1;\r
+ UINT32 OverCurrentProtMode:1;\r
+ UINT32 NoOverCurrentProtMode:1;\r
+ UINT32 Reserved:11;\r
+ UINT32 PowerOnToPowerGoodTime:8;\r
+} HcRH_DESC_A;\r
+\r
+typedef struct {\r
+ UINT32 DeviceRemovable:16;\r
+ UINT32 PortPowerControlMask:16;\r
+} HcRH_DESC_B;\r
+\r
+typedef struct {\r
+ UINT32 LocalPowerStat:1;\r
+ UINT32 OverCurrentIndicator:1;\r
+ UINT32 Reserved1:13;\r
+ UINT32 DevRemoteWakeupEnable:1;\r
+ UINT32 LocalPowerStatChange:1;\r
+ UINT32 OverCurrentIndicatorChange:1;\r
+ UINT32 Reserved2:13;\r
+ UINT32 ClearRemoteWakeupEnable:1;\r
+} HcRH_STATUS;\r
+\r
+typedef struct {\r
+ UINT32 CurrentConnectStat:1;\r
+ UINT32 EnableStat:1;\r
+ UINT32 SuspendStat:1;\r
+ UINT32 OCIndicator:1;\r
+ UINT32 ResetStat:1;\r
+ UINT32 Reserved1:3;\r
+ UINT32 PowerStat:1;\r
+ UINT32 LsDeviceAttached:1;\r
+ UINT32 Reserved2:6;\r
+ UINT32 ConnectStatChange:1;\r
+ UINT32 EnableStatChange:1;\r
+ UINT32 SuspendStatChange:1;\r
+ UINT32 OCIndicatorChange:1;\r
+ UINT32 ResetStatChange:1;\r
+ UINT32 Reserved3:11;\r
+} HcRHPORT_STATUS;\r
+\r
+typedef struct {\r
+ UINT32 FSBIR:1;\r
+ UINT32 FHR:1;\r
+ UINT32 CGR:1;\r
+ UINT32 SSDC:1;\r
+ UINT32 UIT:1;\r
+ UINT32 SSE:1;\r
+ UINT32 PSPL:1;\r
+ UINT32 PCPL:1;\r
+ UINT32 Reserved0:1;\r
+ UINT32 SSEP1:1;\r
+ UINT32 SSEP2:1;\r
+ UINT32 SSEP3:1;\r
+ UINT32 Reserved1:20;\r
+} HcRESET;\r
+\r
+\r
+#pragma pack()\r
+\r
+//\r
+// Func List\r
+//\r
+\r
+\r
+/**\r
+\r
+ Get OHCI operational reg value\r
+\r
+ @param PciIo PciIo protocol instance\r
+ @param Offset Offset of the operational reg\r
+\r
+ @retval Value of the register\r
+\r
+**/\r
+UINT32\r
+OhciGetOperationalReg (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset\r
+ );\r
+\r
+/**\r
+\r
+ Set OHCI operational reg value\r
+\r
+ @param PciIo PCI Bus Io protocol instance\r
+ @param Offset Offset of the operational reg\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set to the reg\r
+\r
+**/\r
+\r
+\r
+EFI_STATUS\r
+OhciSetOperationalReg (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN UINT32 Offset,\r
+ IN VOID *Value\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Get HcRevision reg value\r
+\r
+ @param PciIo PCI Bus Io protocol instance\r
+\r
+ @retval Value of the register\r
+\r
+**/\r
+\r
+\r
+UINT32\r
+OhciGetHcRevision (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo\r
+ );\r
+\r
+/**\r
+\r
+ Set HcReset reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to set\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetHcReset (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Field,\r
+ IN UINT32 Value\r
+ );\r
+/**\r
+\r
+ Get specific field of HcReset reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetHcReset (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Field\r
+ );\r
+/**\r
+\r
+ Set HcControl reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to set\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetHcControl (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field,\r
+ IN UINT32 Value\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Get specific field of HcControl reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+\r
+UINT32\r
+OhciGetHcControl (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Set HcCommand reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to set\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetHcCommandStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field,\r
+ IN UINT32 Value\r
+ );\r
+\r
+/**\r
+\r
+ Get specific field of HcCommand reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetHcCommandStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+/**\r
+\r
+ Clear specific fields of Interrupt Status\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to clear\r
+\r
+ @retval EFI_SUCCESS Fields cleared\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciClearInterruptStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+/**\r
+\r
+ Get fields of HcInterrupt reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetHcInterruptStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+/**\r
+\r
+ Set Interrupt Control reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param StatEnable Enable or Disable\r
+ @param Field Field to set\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetInterruptControl (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN BOOLEAN StatEnable,\r
+ IN UINTN Field,\r
+ IN UINT32 Value\r
+ );\r
+\r
+/**\r
+\r
+ Get field of HcInterruptControl reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetHcInterruptControl (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Set memory pointer of specific type\r
+\r
+ @param Ohc UHC private data\r
+ @param PointerType Type of the pointer to set\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Memory pointer set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetMemoryPointer(\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 PointerType,\r
+ IN VOID *Value\r
+ );\r
+\r
+/**\r
+\r
+ Get memory pointer of specific type\r
+\r
+ @param Ohc UHC private data\r
+ @param PointerType Type of pointer\r
+\r
+ @retval Memory pointer of the specific type\r
+\r
+**/\r
+\r
+VOID *\r
+OhciGetMemoryPointer (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 PointerType\r
+ );\r
+\r
+/**\r
+\r
+ Set Frame Interval value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to set\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetFrameInterval (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field,\r
+ IN UINT32 Value\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Get field of frame interval reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetFrameInterval (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Set Frame Remaining reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetFrameRemaining (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Value\r
+ );\r
+\r
+/**\r
+\r
+ Get value of frame remaining reg\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of frame remaining reg\r
+\r
+**/\r
+UINT32\r
+OhciGetFrameRemaining (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+/**\r
+\r
+ Set frame number reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetFrameNumber(\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Value\r
+ );\r
+\r
+/**\r
+\r
+ Get frame number reg value\r
+\r
+ @param Ohc UHC private data\r
+\r
+ @retval Value of frame number reg\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetFrameNumber (\r
+ IN USB_OHCI_HC_DEV *Ohc\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Set period start reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetPeriodicStart (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Value\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Get periodic start reg value\r
+\r
+ @param Ohc UHC private data\r
+\r
+ @param Value of periodic start reg\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetPeriodicStart (\r
+ IN USB_OHCI_HC_DEV *Ohc\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Set Ls Threshold reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetLsThreshold (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Value\r
+ );\r
+\r
+/**\r
+\r
+ Get Ls Threshold reg value\r
+\r
+ @param Ohc UHC private data\r
+\r
+ @retval Value of Ls Threshold reg\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetLsThreshold (\r
+ IN USB_OHCI_HC_DEV *Ohc\r
+ );\r
+\r
+/**\r
+\r
+ Set Root Hub Descriptor reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to set\r
+ @param Value Value to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+EFI_STATUS\r
+OhciSetRootHubDescriptor (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field,\r
+ IN UINT32 Value\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Get Root Hub Descriptor reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetRootHubDescriptor (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+/**\r
+\r
+ Set Root Hub Status reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetRootHubStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Get Root Hub Status reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field\r
+\r
+**/\r
+\r
+UINT32\r
+OhciGetRootHubStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINTN Field\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Set Root Hub Port Status reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Index Index of the port\r
+ @param Field Field to set\r
+\r
+ @retval EFI_SUCCESS Value set\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+OhciSetRootHubPortStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Index,\r
+ IN UINTN Field\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Get Root Hub Port Status reg value\r
+\r
+ @param Ohc UHC private data\r
+ @param Index Index of the port\r
+ @param Field Field to get\r
+\r
+ @retval Value of the field and index\r
+\r
+**/\r
+\r
+UINT32\r
+OhciReadRootHubPortStatus (\r
+ IN USB_OHCI_HC_DEV *Ohc,\r
+ IN UINT32 Index,\r
+ IN UINTN Field\r
+ );\r
+\r
+#endif\r
projects / mirror_edk2.git / blobdiff