/** @file\r
Main file for Pci shell Debug1 function.\r
\r
- Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <IndustryStandard/Acpi.h>\r
#include "Pci.h"\r
\r
-#define PCI_CLASS_STRING_LIMIT 54\r
//\r
// Printable strings for Pci class code\r
//\r
PCI_CLASS_ENTRY PCISubClass_0f[];\r
PCI_CLASS_ENTRY PCISubClass_10[];\r
PCI_CLASS_ENTRY PCISubClass_11[];\r
+PCI_CLASS_ENTRY PCISubClass_12[];\r
+PCI_CLASS_ENTRY PCISubClass_13[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[];\r
PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0105[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[];\r
PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0609[];\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[];\r
PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r
PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
\r
//\r
L"Data Acquisition & Signal Processing Controllers",\r
PCISubClass_11\r
},\r
+ {\r
+ 0x12,\r
+ L"Processing Accelerators",\r
+ PCISubClass_12\r
+ },\r
+ {\r
+ 0x13,\r
+ L"Non-Essential Instrumentation",\r
+ PCISubClass_13\r
+ },\r
{\r
0xff,\r
L"Device does not fit in any defined classes",\r
PCI_CLASS_ENTRY PCISubClass_01[] = {\r
{\r
0x00,\r
- L"SCSI controller",\r
- PCIBlankEntry\r
+ L"SCSI",\r
+ PCIPIFClass_0100\r
},\r
{\r
0x01,\r
L"RAID controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"ATA controller with ADMA interface",\r
+ PCIPIFClass_0105\r
+ },\r
+ {\r
+ 0x06,\r
+ L"Serial ATA controller",\r
+ PCIPIFClass_0106\r
+ },\r
+ {\r
+ 0x07,\r
+ L"Serial Attached SCSI (SAS) controller ",\r
+ PCIPIFClass_0107\r
+ },\r
+ {\r
+ 0x08,\r
+ L"Non-volatile memory subsystem",\r
+ PCIPIFClass_0108\r
+ },\r
+ {\r
+ 0x09,\r
+ L"Universal Flash Storage (UFS) controller ",\r
+ PCIPIFClass_0109\r
+ },\r
{\r
0x80,\r
L"Other mass storage controller",\r
L"ISDN controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"WorldFip controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x06,\r
+ L"PICMG 2.14 Multi Computing",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"InfiniBand controller",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other network controller",\r
L"Computer Telephony device",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x03,\r
+ L"Mixed mode device",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other multimedia device",\r
L"RACEway bridge",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x09,\r
+ L"Semi-transparent PCI-to-PCI bridge",\r
+ PCIPIFClass_0609\r
+ },\r
+ {\r
+ 0x0A,\r
+ L"InfiniBand-to-PCI host bridge",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x0B,\r
+ L"Advanced Switching to PCI host bridge",\r
+ PCIPIFClass_060b\r
+ },\r
{\r
0x80,\r
L"Other bridge type",\r
L"Modem",\r
PCIPIFClass_0703\r
},\r
+ {\r
+ 0x04,\r
+ L"GPIB (IEEE 488.1/2) controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x05,\r
+ L"Smart Card",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other communication device",\r
L"Generic PCI Hot-Plug controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"SD Host controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x06,\r
+ L"IOMMU",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"Root Complex Event Collector",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other system peripheral",\r
PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
{\r
0x00,\r
- L"Firewire(IEEE 1394)",\r
- PCIPIFClass_0c03\r
+ L"IEEE 1394",\r
+ PCIPIFClass_0c00\r
},\r
{\r
0x01,\r
{\r
0x03,\r
L"USB",\r
- PCIPIFClass_0c00\r
+ PCIPIFClass_0c03\r
},\r
{\r
0x04,\r
L"System Management Bus",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x06,\r
+ L"InfiniBand",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"IPMI",\r
+ PCIPIFClass_0c07\r
+ },\r
+ {\r
+ 0x08,\r
+ L"SERCOS Interface Standard (IEC 61491)",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x09,\r
+ L"CANbus",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other bus type",\r
},\r
{\r
0x01,\r
- L"Consumer IR controller",\r
- PCIBlankEntry\r
+ L"",\r
+ PCIPIFClass_0d01\r
},\r
{\r
0x10,\r
L"RF controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x11,\r
+ L"Bluetooth",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x12,\r
+ L"Broadband",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"Ethernet (802.11a - 5 GHz)",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x21,\r
+ L"Ethernet (802.11b - 2.4 GHz)",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other type of wireless controller",\r
\r
PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
{\r
- 0x00,\r
+ 0x01,\r
L"TV",\r
PCIBlankEntry\r
},\r
{\r
- 0x01,\r
+ 0x02,\r
L"Audio",\r
PCIBlankEntry\r
},\r
{\r
- 0x02,\r
+ 0x03,\r
L"Voice",\r
PCIBlankEntry\r
},\r
{\r
- 0x03,\r
+ 0x04,\r
L"Data",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x80,\r
+ L"Other satellite communication controller",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x00,\r
NULL,\r
L"DPIO modules",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x01,\r
+ L"Performance Counters",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x10,\r
+ L"Communications synchronization plus time and frequency test/measurement ",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"Management card",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other DAQ & SP controllers",\r
}\r
};\r
\r
+PCI_CLASS_ENTRY PCISubClass_12[] = {\r
+ {\r
+ 0x00,\r
+ L"Processing Accelerator",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCISubClass_13[] = {\r
+ {\r
+ 0x00,\r
+ L"Non-Essential Instrumentation Function",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
//\r
// Programming Interface entries\r
//\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r
+ {\r
+ 0x00,\r
+ L"SCSI controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x11,\r
+ L"SCSI storage device SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x12,\r
+ L"SCSI controller SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x13,\r
+ L"SCSI storage device and controller SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x21,\r
+ L"SCSI storage device SOP using NVMe",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
{\r
0x00,\r
}\r
};\r
\r
+PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r
+ {\r
+ 0x20,\r
+ L"Single stepping",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x30,\r
+ L"Continuous operation",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"AHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"Serial Storage Bus",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"Obsolete",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"NVMHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"NVM Express",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"UFSHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
{\r
0x00,\r
}\r
};\r
\r
+PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r
+ {\r
+ 0x40,\r
+ L"Primary PCI bus side facing the system host processor",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x80,\r
+ L"Secondary PCI bus side facing the system host processor",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r
+ {\r
+ 0x00,\r
+ L"Custom",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"ASI-SIG Defined Portal",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
{\r
0x00,\r
PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
{\r
0x00,\r
- L"Universal Host Controller spec",\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x10,\r
+ L"Using 1394 OpenHCI spec",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
+ {\r
+ 0x00,\r
+ L"UHCI",\r
PCIBlankEntry\r
},\r
{\r
0x10,\r
- L"Open Host Controller spec",\r
+ L"OHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"EHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x30,\r
+ L"xHCI",\r
PCIBlankEntry\r
},\r
{\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r
{\r
0x00,\r
- L"",\r
+ L"SMIC",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"Keyboard Controller Style",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"Block Transfer",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r
+ {\r
+ 0x00,\r
+ L"Consumer IR controller",\r
PCIBlankEntry\r
},\r
{\r
0x10,\r
- L"Using 1394 OpenHCI spec",\r
+ L"UWB Radio controller",\r
PCIBlankEntry\r
},\r
{\r
bits 23:16 - Base Class Code\r
bits 15:8 - Sub-Class Code\r
bits 7:0 - Programming Interface\r
- @param[in,out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
+ @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
printable class strings corresponding to ClassCode. The\r
caller must not modify the strings that are pointed by\r
the fields in ClassStrings.\r
Print strings that represent PCI device class, subclass and programmed I/F.\r
\r
@param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
- configuation space.\r
+ configuration space.\r
@param[in] IncludePIF If the printed string should include the programming I/F part\r
**/\r
VOID\r
{\r
UINT32 ClassCode;\r
PCI_CLASS_STRINGS ClassStrings;\r
- CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];\r
\r
ClassCode = 0;\r
- ClassCode |= ClassCodePtr[0];\r
- ClassCode |= (ClassCodePtr[1] << 8);\r
- ClassCode |= (ClassCodePtr[2] << 16);\r
+ ClassCode |= (UINT32)ClassCodePtr[0];\r
+ ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r
+ ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r
\r
//\r
// Get name from class code\r
\r
if (IncludePIF) {\r
//\r
- // Only print base class and sub class name\r
+ // Print base class, sub class, and programming inferface name\r
//\r
- ShellPrintEx(-1,-1, L"%s - %s - %s",\r
+ ShellPrintEx (-1, -1, L"%s - %s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass,\r
ClassStrings.PIFClass\r
\r
} else {\r
//\r
- // Print base class, sub class, and programming inferface name\r
+ // Only print base class and sub class name\r
//\r
- UnicodeSPrint (\r
- OutputString,\r
- PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),\r
- L"%s - %s",\r
+ ShellPrintEx (-1, -1, L"%s - %s",\r
ClassStrings.BaseClass,\r
ClassStrings.SubClass\r
- );\r
-\r
- OutputString[PCI_CLASS_STRING_LIMIT] = 0;\r
- ShellPrintEx(-1,-1, L"%s", OutputString);\r
+ );\r
}\r
}\r
\r
It also moves the pointer backward a node, to get prepared to be called\r
again.\r
\r
- @param[in,out] Descriptors Points to current position of a serial of address space\r
- descriptors.\r
- @param[out] MinBus The lower range of bus number.\r
- @param[out] ManBus The upper range of bus number.\r
- @param[out] IsEnd Meet end of the serial of descriptors.\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
-\r
- @retval EFI_SUCCESS The command completed successfully.\r
**/\r
-EFI_STATUS\r
-PciExplainData (\r
+VOID\r
+PciExplainPci (\r
IN PCI_CONFIG_SPACE *ConfigSpace,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
- IN PCI_DEVICE_HEADER *Device,\r
+ IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
- IN PCI_BRIDGE_HEADER *Bridge,\r
+ IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
/**\r
Explain the Base Address Register(Bar) in PCI configuration space.\r
\r
- @param[in] Bar Points to the Base Address Register intended to interpret.\r
- @param[in] Command Points to the register Command.\r
- @param[in] Address Address used to access configuration space of this PCI device.\r
- @param[in] IoDev Handle used to access configuration space of PCI device.\r
- @param[in,out] Index The Index.\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
- IN PCI_CARDBUS_HEADER *CardBus,\r
+ IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
);\r
);\r
\r
/**\r
- Print each capability structure.\r
+ Locate capability register block per capability ID.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] CapabilityId The capability ID.\r
\r
- @retval EFI_SUCCESS The operation was successful.\r
+ @return The offset of the register block per capability ID.\r
**/\r
-EFI_STATUS\r
-PciExplainCapabilityStruct (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapPtr\r
+UINT8\r
+LocatePciCapability (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT8 CapabilityId\r
);\r
\r
/**\r
Display Pcie device structure.\r
\r
- @param[in] IoDev The pointer to the root pci protocol.\r
- @param[in] Address The Address to start at.\r
- @param[in] CapabilityPtr The offset from the address to start.\r
+ @param[in] PciExpressCap PCI Express capability buffer.\r
+ @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
+ @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
**/\r
-EFI_STATUS\r
+VOID\r
PciExplainPciExpress (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapabilityPtr\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
+ IN UINT8 *ExtendedConfigSpace,\r
+ IN CONST UINT16 ExtendedCapability\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
);\r
\r
-typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
+typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCI_CAPABILITY_PCIEXP *PciExpressCap);\r
\r
typedef enum {\r
FieldWidthUINT8,\r
STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
{L"-s", TypeValue},\r
{L"-i", TypeFlag},\r
+ {L"-ec", TypeValue},\r
{NULL, TypeMax}\r
};\r
\r
UINT64 Address;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
EFI_STATUS Status;\r
- PCI_COMMON_HEADER PciHeader;\r
+ PCI_DEVICE_INDEPENDENT_REGION PciHeader;\r
PCI_CONFIG_SPACE ConfigSpace;\r
UINTN ScreenCount;\r
UINTN TempColumn;\r
LIST_ENTRY *Package;\r
CHAR16 *ProblemParam;\r
SHELL_STATUS ShellStatus;\r
- UINTN Size;\r
CONST CHAR16 *Temp;\r
+ UINT64 RetVal;\r
+ UINT16 ExtendedCapability;\r
+ UINT8 PcieCapabilityPtr;\r
+ UINT8 *ExtendedConfigSpace;\r
+ UINTN ExtendedConfigSize;\r
\r
ShellStatus = SHELL_SUCCESS;\r
Status = EFI_SUCCESS;\r
Address = 0;\r
- Size = 0;\r
IoDev = NULL;\r
HandleBuf = NULL;\r
Package = NULL;\r
Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
if (EFI_ERROR(Status)) {\r
if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam); \r
FreePool(ProblemParam);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
} else {\r
} else {\r
\r
if (ShellCommandLineGetCount(Package) == 2) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (ShellCommandLineGetCount(Package) > 4) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci"); \r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+ if (ShellCommandLineGetFlag(Package, L"-ec") && ShellCommandLineGetValue(Package, L"-ec") == NULL) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec"); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s"); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
HandleBufSize = sizeof (EFI_HANDLE);\r
HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
}\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
&Descriptors\r
);\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
ShellStatus = SHELL_ABORTED;\r
goto Done;\r
}\r
- Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
+ Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
IoDev->Pci.Read (\r
IoDev,\r
EfiPciWidthUint16,\r
Bus = 0;\r
Device = 0;\r
Func = 0;\r
+ ExtendedCapability = 0xFFFF;\r
if (ShellCommandLineGetFlag(Package, L"-i")) {\r
ExplainData = TRUE;\r
}\r
\r
Temp = ShellCommandLineGetValue(Package, L"-s");\r
if (Temp != NULL) {\r
- Segment = (UINT16) ShellStrToUintn (Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Segment = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
}\r
\r
//\r
//\r
Temp = ShellCommandLineGetRawValue(Package, 1);\r
if (Temp != NULL) {\r
- Bus = (UINT16)ShellStrToUintn(Temp);\r
- if (Bus > MAX_BUS_NUMBER) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Bus = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
+ if (Bus > PCI_MAX_BUS) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
}\r
Temp = ShellCommandLineGetRawValue(Package, 2);\r
if (Temp != NULL) {\r
- Device = (UINT16) ShellStrToUintn(Temp);\r
- if (Device > MAX_DEVICE_NUMBER){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Device = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
+ if (Device > PCI_MAX_DEVICE){\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
Temp = ShellCommandLineGetRawValue(Package, 3);\r
if (Temp != NULL) {\r
- Func = (UINT16) ShellStrToUintn(Temp);\r
- if (Func > MAX_FUNCTION_NUMBER){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ Func = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+\r
+ if (Func > PCI_MAX_FUNC){\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
+ ShellStatus = SHELL_INVALID_PARAMETER;\r
+ goto Done;\r
+ }\r
+ }\r
+\r
+ Temp = ShellCommandLineGetValue (Package, L"-ec");\r
+ if (Temp != NULL) {\r
+ //\r
+ // Input converted to hexadecimal number.\r
+ //\r
+ if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
+ ExtendedCapability = (UINT16) RetVal;\r
+ } else {\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (EFI_ERROR (Status)) {\r
ShellPrintHiiEx(\r
- -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
- gShellDebug1HiiHandle,\r
+ -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci", \r
Segment,\r
Bus\r
);\r
goto Done;\r
}\r
\r
- Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
+ Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
Status = IoDev->Pci.Read (\r
IoDev,\r
EfiPciWidthUint8,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_ACCESS_DENIED;\r
goto Done;\r
}\r
ConfigSpace.Data\r
);\r
\r
+ ExtendedConfigSpace = NULL;\r
+ ExtendedConfigSize = 0;\r
+ PcieCapabilityPtr = LocatePciCapability (&ConfigSpace, EFI_PCI_CAPABILITY_ID_PCIEXP);\r
+ if (PcieCapabilityPtr != 0) {\r
+ ExtendedConfigSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
+ ExtendedConfigSpace = AllocatePool (ExtendedConfigSize);\r
+ if (ExtendedConfigSpace != NULL) {\r
+ Status = IoDev->Pci.Read (\r
+ IoDev,\r
+ EfiPciWidthUint32,\r
+ EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET),\r
+ ExtendedConfigSize / sizeof (UINT32),\r
+ ExtendedConfigSpace\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ SHELL_FREE_NON_NULL (ExtendedConfigSpace);\r
+ }\r
+ }\r
+ }\r
+\r
+ if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
+ //\r
+ // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
+ //\r
+ ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
+\r
+ DumpHex (\r
+ 2,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
+ ExtendedConfigSize,\r
+ ExtendedConfigSpace\r
+ );\r
+ }\r
+\r
//\r
// If "-i" appears in command line, interpret data in configuration space\r
//\r
if (ExplainData) {\r
- Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
+ PciExplainPci (&ConfigSpace, Address, IoDev);\r
+ if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
+ PciExplainPciExpress (\r
+ (PCI_CAPABILITY_PCIEXP *) ((UINT8 *) &ConfigSpace + PcieCapabilityPtr),\r
+ ExtendedConfigSpace,\r
+ ExtendedCapability\r
+ );\r
+ }\r
}\r
}\r
Done:\r
{\r
UINTN Index;\r
EFI_STATUS Status;\r
- BOOLEAN FoundInterface;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
UINT16 MinBus;\r
UINT16 MaxBus;\r
BOOLEAN IsEnd;\r
\r
- FoundInterface = FALSE;\r
//\r
// Go through all handles, until the one meets the criteria is found\r
//\r
}\r
\r
if (MinBus <= Bus && MaxBus >= Bus) {\r
- FoundInterface = TRUE;\r
- break;\r
+ return EFI_SUCCESS;\r
}\r
}\r
}\r
\r
- if (FoundInterface) {\r
- return EFI_SUCCESS;\r
- } else {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
+ return EFI_NOT_FOUND;\r
}\r
\r
/**\r
It also moves the pointer backward a node, to get prepared to be called\r
again.\r
\r
- @param[in,out] Descriptors Points to current position of a serial of address space\r
- descriptors.\r
- @param[out] MinBus The lower range of bus number.\r
- @param[out] ManBus The upper range of bus number.\r
- @param[out] IsEnd Meet end of the serial of descriptors.\r
+ @param[in, out] Descriptors Points to current position of a serial of address space\r
+ descriptors.\r
+ @param[out] MinBus The lower range of bus number.\r
+ @param[out] MaxBus The upper range of bus number.\r
+ @param[out] IsEnd Meet end of the serial of descriptors.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
-\r
- @retval EFI_SUCCESS The command completed successfully.\r
**/\r
-EFI_STATUS\r
-PciExplainData (\r
+VOID\r
+PciExplainPci (\r
IN PCI_CONFIG_SPACE *ConfigSpace,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
{\r
- PCI_COMMON_HEADER *Common;\r
- PCI_HEADER_TYPE HeaderType;\r
- EFI_STATUS Status;\r
- UINT8 CapPtr;\r
+ PCI_DEVICE_INDEPENDENT_REGION *Common;\r
+ PCI_HEADER_TYPE HeaderType;\r
\r
Common = &(ConfigSpace->Common);\r
\r
- Print (L"\n");\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
\r
//\r
// Print Vendor Id and Device Id\r
//\r
// Print register Revision ID\r
//\r
- ShellPrintEx(-1, -1, L"/r/n");\r
+ ShellPrintEx(-1, -1, L"\r\n");\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
- INDEX_OF (&(Common->RevisionId)),\r
- Common->RevisionId\r
+ INDEX_OF (&(Common->RevisionID)),\r
+ Common->RevisionID\r
);\r
\r
//\r
// Print register BIST\r
//\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
- if ((Common->Bist & PCI_BIT_7) != 0) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r
+ if ((Common->BIST & BIT7) != 0) {\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
}\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
- Common->PrimaryLatencyTimer\r
+ INDEX_OF (&(Common->LatencyTimer)),\r
+ Common->LatencyTimer\r
);\r
\r
//\r
Common->HeaderType\r
);\r
\r
- if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
+ if ((Common->HeaderType & BIT7) != 0) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
\r
} else {\r
\r
//\r
// Print register Class Code\r
- //\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
- PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
- Print (L"\n");\r
-\r
- if (ShellGetExecutionBreakFlag()) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
- //\r
- // Interpret remaining part of PCI configuration header depending on\r
- // HeaderType\r
- //\r
- CapPtr = 0;\r
- Status = EFI_SUCCESS;\r
- switch (HeaderType) {\r
- case PciDevice:\r
- Status = PciExplainDeviceData (\r
- &(ConfigSpace->NonCommon.Device),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
- break;\r
-\r
- case PciP2pBridge:\r
- Status = PciExplainBridgeData (\r
- &(ConfigSpace->NonCommon.Bridge),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
- break;\r
-\r
- case PciCardBusBridge:\r
- Status = PciExplainCardBusData (\r
- &(ConfigSpace->NonCommon.CardBus),\r
- Address,\r
- IoDev\r
- );\r
- CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
- break;\r
- case PciUndefined:\r
- default:\r
- break;\r
- }\r
- //\r
- // If Status bit4 is 1, dump or explain capability structure\r
- //\r
- if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
- PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
- }\r
-\r
- return Status;\r
+ //\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
+ PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
+ ShellPrintEx (-1, -1, L"\r\n");\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
- IN PCI_DEVICE_HEADER *Device,\r
+ IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
if (!BarExist) {\r
BarExist = TRUE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
- Print (L" --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
\r
} else {\r
- Print (L"\n --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
\r
//\r
// Print register Expansion ROM Base Address\r
//\r
- if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
+ if ((Device->ExpansionRomBar & BIT0) == 0) {\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ExpansionRomBar)));\r
\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->ROMBar)),\r
- Device->ROMBar\r
+ INDEX_OF (&(Device->ExpansionRomBar)),\r
+ Device->ExpansionRomBar\r
);\r
}\r
//\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->CardBusCISPtr)),\r
- Device->CardBusCISPtr\r
+ INDEX_OF (&(Device->CISPtr)),\r
+ Device->CISPtr\r
);\r
\r
//\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->SubVendorId)),\r
- Device->SubVendorId\r
+ INDEX_OF (&(Device->SubsystemVendorID)),\r
+ Device->SubsystemVendorID\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->SubSystemId)),\r
- Device->SubSystemId\r
+ INDEX_OF (&(Device->SubsystemID)),\r
+ Device->SubsystemID\r
);\r
\r
//\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Device->CapabilitiesPtr)),\r
- Device->CapabilitiesPtr\r
+ INDEX_OF (&(Device->CapabilityPtr)),\r
+ Device->CapabilityPtr\r
);\r
\r
//\r
**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
- IN PCI_BRIDGE_HEADER *Bridge,\r
+ IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
if (!BarExist) {\r
BarExist = TRUE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
- Print (L" --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
}\r
\r
Status = PciExplainBar (\r
if (!BarExist) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
} else {\r
- Print (L"\n --------------------------------------------------------------------------");\r
+ ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
}\r
\r
//\r
// Expansion register ROM Base Address\r
//\r
- if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
+ if ((Bridge->ExpansionRomBAR & BIT0) == 0) {\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ExpansionRomBAR)));\r
\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Bridge->ROMBar)),\r
- Bridge->ROMBar\r
+ INDEX_OF (&(Bridge->ExpansionRomBAR)),\r
+ Bridge->ExpansionRomBAR\r
);\r
}\r
//\r
INDEX_OF (&(Bridge->SubordinateBus))\r
);\r
\r
- Print (L" ------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
// base and limit address are listed.\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
- Print (L"----------------------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
//\r
// IO Base & Limit\r
//\r
- IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
+ IoAddress32 = (Bridge->IoBaseUpper16 << 16 | Bridge->IoBase << 8);\r
IoAddress32 &= 0xfffff000;\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_TWO_VARS),\r
IoAddress32\r
);\r
\r
- IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
+ IoAddress32 = (Bridge->IoLimitUpper16 << 16 | Bridge->IoLimit << 8);\r
IoAddress32 |= 0x00000fff;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
- Bridge->PrefetchableBaseUpper,\r
- (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
+ INDEX_OF (&(Bridge->PrefetchableMemoryBase)),\r
+ Bridge->PrefetchableBaseUpper32,\r
+ (Bridge->PrefetchableMemoryBase << 16) & 0xfff00000\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
gShellDebug1HiiHandle,\r
- Bridge->PrefetchableLimitUpper,\r
- (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
+ Bridge->PrefetchableLimitUpper32,\r
+ (Bridge->PrefetchableMemoryLimit << 16) | 0x000fffff\r
);\r
\r
//\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
gShellDebug1HiiHandle,\r
- INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
- Bridge->CapabilitiesPtr\r
+ INDEX_OF (&(Bridge->CapabilityPtr)),\r
+ Bridge->CapabilityPtr\r
);\r
\r
//\r
/**\r
Explain the Base Address Register(Bar) in PCI configuration space.\r
\r
- @param[in] Bar Points to the Base Address Register intended to interpret.\r
- @param[in] Command Points to the register Command.\r
- @param[in] Address Address used to access configuration space of this PCI device.\r
- @param[in] IoDev Handle used to access configuration space of PCI device.\r
- @param[in,out] Index The Index.\r
+ @param[in] Bar Points to the Base Address Register intended to interpret.\r
+ @param[in] Command Points to the register Command.\r
+ @param[in] Address Address used to access configuration space of this PCI device.\r
+ @param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in, out] Index The Index.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
// According the bar type, list detail about this bar, for example: 32 or\r
// 64 bits; pre-fetchable or not.\r
//\r
- if ((*Bar & PCI_BIT_0) == 0) {\r
+ if ((*Bar & BIT0) == 0) {\r
//\r
// This bar is of memory type\r
//\r
IsMem = TRUE;\r
\r
- if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
+ if ((*Bar & BIT1) == 0 && (*Bar & BIT2) == 0) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
\r
- } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
+ } else if ((*Bar & BIT1) == 0 && (*Bar & BIT2) != 0) {\r
Bar64 = 0x0;\r
CopyMem (&Bar64, Bar, sizeof (UINT64));\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
}\r
\r
- if ((*Bar & PCI_BIT_3) == 0) {\r
+ if ((*Bar & BIT3) == 0) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
\r
} else {\r
//\r
IsMem = FALSE;\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
- Print (L"I/O ");\r
+ ShellPrintEx (-1, -1, L"I/O ");\r
}\r
\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
- Print (L" ");\r
+ ShellPrintEx (-1, -1, L" ");\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_RSHIFT),\r
gShellDebug1HiiHandle,\r
- RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
+ (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
\r
**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
- IN PCI_CARDBUS_HEADER *CardBus,\r
+ IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r
IN UINT64 Address,\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
)\r
INDEX_OF (&(CardBus->SubordinateBusNumber))\r
);\r
\r
- Print (L" ------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
// Print Memory/Io ranges this cardbus bridge forwards\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
- Print (L"----------------------------------------------------------------------\n");\r
+ ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_MEM_3),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->MemoryBase0)),\r
- CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
+ CardBus->BridgeControl & BIT8 ? L" Prefetchable" : L"Non-Prefetchable",\r
CardBus->MemoryBase0 & 0xfffff000,\r
CardBus->MemoryLimit0 | 0x00000fff\r
);\r
STRING_TOKEN (STR_PCI2_MEM_3),\r
gShellDebug1HiiHandle,\r
INDEX_OF (&(CardBus->MemoryBase1)),\r
- CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
+ CardBus->BridgeControl & BIT9 ? L" Prefetchable" : L"Non-Prefetchable",\r
CardBus->MemoryBase1 & 0xfffff000,\r
CardBus->MemoryLimit1 | 0x00000fff\r
);\r
\r
- Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
+ Io32Bit = (BOOLEAN) (CardBus->IoBase0 & BIT0);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_IO_2),\r
gShellDebug1HiiHandle,\r
(CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
);\r
\r
- Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
+ Io32Bit = (BOOLEAN) (CardBus->IoBase1 & BIT0);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_IO_2),\r
gShellDebug1HiiHandle,\r
// bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
// Address.\r
//\r
- CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
+ CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_CONTROL_REGISTER));\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
}\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & BIT4) != 0);\r
\r
//\r
// Bit 5 is meaningless for CardBus Bridge\r
//\r
if (HeaderType == PciCardBusBridge) {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r
\r
} else {\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r
}\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & BIT7) != 0);\r
\r
- ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
+ ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & BIT8) != 0);\r
//\r
// Bit 9 and bit 10 together decides the DEVSEL timing\r
//\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
- if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
+ if ((*Status & BIT9) == 0 && (*Status & BIT10) == 0) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
\r
- } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
+ } else if ((*Status & BIT9) != 0 && (*Status & BIT10) == 0) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
\r
- } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
+ } else if ((*Status & BIT9) == 0 && (*Status & BIT10) != 0) {\r
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_11) != 0\r
+ (*Status & BIT11) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_12) != 0\r
+ (*Status & BIT12) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_13) != 0\r
+ (*Status & BIT13) != 0\r
);\r
\r
if (MainStatus) {\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_14) != 0\r
+ (*Status & BIT14) != 0\r
);\r
\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_14) != 0\r
+ (*Status & BIT14) != 0\r
);\r
}\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
gShellDebug1HiiHandle,\r
- (*Status & PCI_BIT_15) != 0\r
+ (*Status & BIT15) != 0\r
);\r
\r
return EFI_SUCCESS;\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_0) != 0\r
+ (*Command & BIT0) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_1) != 0\r
+ (*Command & BIT1) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_2) != 0\r
+ (*Command & BIT2) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_3) != 0\r
+ (*Command & BIT3) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_4) != 0\r
+ (*Command & BIT4) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_5) != 0\r
+ (*Command & BIT5) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_6) != 0\r
+ (*Command & BIT6) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_7) != 0\r
+ (*Command & BIT7) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_8) != 0\r
+ (*Command & BIT8) != 0\r
);\r
\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
gShellDebug1HiiHandle,\r
- (*Command & PCI_BIT_9) != 0\r
+ (*Command & BIT9) != 0\r
);\r
\r
return EFI_SUCCESS;\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_0) != 0\r
+ (*BridgeControl & BIT0) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_1) != 0\r
+ (*BridgeControl & BIT1) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_2) != 0\r
+ (*BridgeControl & BIT2) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_3) != 0\r
+ (*BridgeControl & BIT3) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_5) != 0\r
+ (*BridgeControl & BIT5) != 0\r
);\r
\r
//\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_6) != 0\r
+ (*BridgeControl & BIT6) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_7) != 0\r
+ (*BridgeControl & BIT7) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
+ (*BridgeControl & BIT8)!=0 ? L"2^10" : L"2^15"\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
+ (*BridgeControl & BIT9)!=0 ? L"2^10" : L"2^15"\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_10) != 0\r
+ (*BridgeControl & BIT10) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_11) != 0\r
+ (*BridgeControl & BIT11) != 0\r
);\r
\r
} else {\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_6) != 0\r
+ (*BridgeControl & BIT6) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_7) != 0\r
+ (*BridgeControl & BIT7) != 0\r
);\r
ShellPrintHiiEx(-1, -1, NULL,\r
STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
gShellDebug1HiiHandle,\r
- (*BridgeControl & PCI_BIT_10) != 0\r
+ (*BridgeControl & BIT10) != 0\r
);\r
}\r
\r
}\r
\r
/**\r
- Print each capability structure.\r
+ Locate capability register block per capability ID.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
+ @param[in] ConfigSpace Data in PCI configuration space.\r
+ @param[in] CapabilityId The capability ID.\r
\r
- @retval EFI_SUCCESS The operation was successful.\r
+ @return The offset of the register block per capability ID,\r
+ or 0 if the register block cannot be found.\r
**/\r
-EFI_STATUS\r
-PciExplainCapabilityStruct (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapPtr\r
+UINT8\r
+LocatePciCapability (\r
+ IN PCI_CONFIG_SPACE *ConfigSpace,\r
+ IN UINT8 CapabilityId\r
)\r
{\r
- UINT8 CapabilityPtr;\r
- UINT16 CapabilityEntry;\r
- UINT8 CapabilityID;\r
- UINT64 RegAddress;\r
-\r
- CapabilityPtr = CapPtr;\r
+ UINT8 CapabilityPtr;\r
+ EFI_PCI_CAPABILITY_HDR *CapabilityEntry;\r
\r
//\r
- // Go through the Capability list\r
+ // To check the cpability of this device supports\r
//\r
- while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
- RegAddress = Address + CapabilityPtr;\r
- IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
+ if ((ConfigSpace->Common.Status & EFI_PCI_STATUS_CAPABILITY) == 0) {\r
+ return 0;\r
+ }\r
\r
- CapabilityID = (UINT8) CapabilityEntry;\r
+ switch ((PCI_HEADER_TYPE)(ConfigSpace->Common.HeaderType & 0x7f)) {\r
+ case PciDevice:\r
+ CapabilityPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;\r
+ break;\r
+ case PciP2pBridge:\r
+ CapabilityPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;\r
+ break;\r
+ case PciCardBusBridge:\r
+ CapabilityPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;\r
+ break;\r
+ default:\r
+ return 0;\r
+ }\r
\r
- //\r
- // Explain PciExpress data\r
- //\r
- if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
- PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
- return EFI_SUCCESS;\r
+ while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
+ CapabilityEntry = (EFI_PCI_CAPABILITY_HDR *) ((UINT8 *) ConfigSpace + CapabilityPtr);\r
+ if (CapabilityEntry->CapabilityID == CapabilityId) {\r
+ return CapabilityPtr;\r
}\r
+\r
//\r
- // Explain other capabilities here\r
+ // Certain PCI device may incorrectly have capability pointing to itself,\r
+ // break to avoid dead loop.\r
//\r
- CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
+ if (CapabilityPtr == CapabilityEntry->NextItemPtr) {\r
+ break;\r
+ }\r
+\r
+ CapabilityPtr = CapabilityEntry->NextItemPtr;\r
}\r
\r
- return EFI_SUCCESS;\r
+ return 0;\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieCapReg;\r
CHAR16 *DevicePortType;\r
\r
- PcieCapReg = PciExpressCap->PcieCapReg;\r
- Print (\r
- L" Capability Version(3:0): %E0x%04x%N\n",\r
- PCIE_CAP_VERSION (PcieCapReg)\r
+ ShellPrintEx (-1, -1,\r
+ L" Capability Version(3:0): %E0x%04x%N\r\n",\r
+ PciExpressCap->Capability.Bits.Version\r
);\r
- if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
- DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
+ if (PciExpressCap->Capability.Bits.DevicePortType < ARRAY_SIZE (DevicePortTypeTable)) {\r
+ DevicePortType = DevicePortTypeTable[PciExpressCap->Capability.Bits.DevicePortType];\r
} else {\r
DevicePortType = L"Unknown Type";\r
}\r
- Print (\r
- L" Device/PortType(7:4): %E%s%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Device/PortType(7:4): %E%s%N\r\n",\r
DevicePortType\r
);\r
//\r
// a) Root Port of PCI Express Root Complex, or\r
// b) Downstream Port of PCI Express Switch\r
//\r
- if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
- PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
- Print (\r
- L" Slot Implemented(8): %E%d%N\n",\r
- PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
+ if (PciExpressCap->Capability.Bits.DevicePortType== PCIE_DEVICE_PORT_TYPE_ROOT_PORT ||\r
+ PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) {\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Implemented(8): %E%d%N\r\n",\r
+ PciExpressCap->Capability.Bits.SlotImplemented\r
);\r
}\r
- Print (\r
- L" Interrupt Message Number(13:9): %E0x%05x%N\n",\r
- PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
+ ShellPrintEx (-1, -1,\r
+ L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
+ PciExpressCap->Capability.Bits.InterruptMessageNumber\r
);\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieCapReg;\r
- UINT32 PcieDeviceCap;\r
UINT8 DevicePortType;\r
UINT8 L0sLatency;\r
UINT8 L1Latency;\r
\r
- PcieCapReg = PciExpressCap->PcieCapReg;\r
- PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
- DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
- Print (L" Max_Payload_Size Supported(2:0): ");\r
- if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
+ DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
+ ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
+ if (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize < 6) {\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- Print (\r
- L" Phantom Functions Supported(4:3): %E%d%N\n",\r
- PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
+ PciExpressCap->DeviceCapability.Bits.PhantomFunctions\r
);\r
- Print (\r
- L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",\r
- PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
+ PciExpressCap->DeviceCapability.Bits.ExtendedTagField ? 8 : 5\r
);\r
//\r
// Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
- L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
- Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
+ L0sLatency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL0sAcceptableLatency;\r
+ L1Latency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL1AcceptableLatency;\r
+ ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
if (L0sLatency < 4) {\r
- Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
} else {\r
if (L0sLatency < 7) {\r
- Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
} else {\r
- Print (L"%ENo limit%N\n");\r
+ ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
- Print (L" Endpoint L1 Acceptable Latency(11:9): ");\r
+ ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
if (L1Latency < 7) {\r
- Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));\r
+ ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
} else {\r
- Print (L"%ENo limit%N\n");\r
+ ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
}\r
}\r
- Print (\r
- L" Role-based Error Reporting(15): %E%d%N\n",\r
- PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Role-based Error Reporting(15): %E%d%N\r\n",\r
+ PciExpressCap->DeviceCapability.Bits.RoleBasedErrorReporting\r
);\r
//\r
// Only valid for Upstream Port:\r
// a) Captured Slot Power Limit Value\r
// b) Captured Slot Power Scale\r
//\r
- if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
- Print (\r
- L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",\r
- PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
+ if (DevicePortType == PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) {\r
+ ShellPrintEx (-1, -1,\r
+ L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
+ PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitValue\r
);\r
- Print (\r
- L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",\r
- SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
+ ShellPrintEx (-1, -1,\r
+ L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
+ SlotPwrLmtScaleTable[PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitScale]\r
);\r
}\r
//\r
// Function Level Reset Capability is only valid for Endpoint\r
//\r
if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
- Print (\r
- L" Function Level Reset Capability(28): %E%d%N\n",\r
- PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Function Level Reset Capability(28): %E%d%N\r\n",\r
+ PciExpressCap->DeviceCapability.Bits.FunctionLevelReset\r
);\r
}\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieCapReg;\r
- UINT16 PcieDeviceControl;\r
-\r
- PcieCapReg = PciExpressCap->PcieCapReg;\r
- PcieDeviceControl = PciExpressCap->DeviceControl;\r
- Print (\r
- L" Correctable Error Reporting Enable(0): %E%d%N\n",\r
- PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- Print (\r
- L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",\r
- PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- Print (\r
- L" Fatal Error Reporting Enable(2): %E%d%N\n",\r
- PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- Print (\r
- L" Unsupported Request Reporting Enable(3): %E%d%N\n",\r
- PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
- );\r
- Print (\r
- L" Enable Relaxed Ordering(4): %E%d%N\n",\r
- PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
- );\r
- Print (L" Max_Payload_Size(7:5): ");\r
- if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
+ ShellPrintEx (-1, -1,\r
+ L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.CorrectableError\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.NonFatalError\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.FatalError\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.UnsupportedRequest\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.RelaxedOrdering\r
+ );\r
+ ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
+ if (PciExpressCap->DeviceControl.Bits.MaxPayloadSize < 6) {\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxPayloadSize + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
- Print (\r
- L" Extended Tag Field Enable(8): %E%d%N\n",\r
- PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.ExtendedTagField\r
);\r
- Print (\r
- L" Phantom Functions Enable(9): %E%d%N\n",\r
- PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Phantom Functions Enable(9): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.PhantomFunctions\r
);\r
- Print (\r
- L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",\r
- PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.AuxPower\r
);\r
- Print (\r
- L" Enable No Snoop(11): %E%d%N\n",\r
- PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable No Snoop(11): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.NoSnoop\r
);\r
- Print (L" Max_Read_Request_Size(14:12): ");\r
- if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
- Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
+ ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
+ if (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize < 6) {\r
+ ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize + 7));\r
} else {\r
- Print (L"%EUnknown%N\n");\r
+ ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
}\r
//\r
// Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
//\r
- if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- Print (\r
- L" Bridge Configuration Retry Enable(15): %E%d%N\n",\r
- PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
+ if (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r
+ ShellPrintEx (-1, -1,\r
+ L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
+ PciExpressCap->DeviceControl.Bits.BridgeConfigurationRetryOrFunctionLevelReset\r
);\r
}\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieDeviceStatus;\r
-\r
- PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
- Print (\r
- L" Correctable Error Detected(0): %E%d%N\n",\r
- PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Correctable Error Detected(0): %E%d%N\r\n",\r
+ PciExpressCap->DeviceStatus.Bits.CorrectableError\r
);\r
- Print (\r
- L" Non-Fatal Error Detected(1): %E%d%N\n",\r
- PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
+ PciExpressCap->DeviceStatus.Bits.NonFatalError\r
);\r
- Print (\r
- L" Fatal Error Detected(2): %E%d%N\n",\r
- PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Fatal Error Detected(2): %E%d%N\r\n",\r
+ PciExpressCap->DeviceStatus.Bits.FatalError\r
);\r
- Print (\r
- L" Unsupported Request Detected(3): %E%d%N\n",\r
- PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Unsupported Request Detected(3): %E%d%N\r\n",\r
+ PciExpressCap->DeviceStatus.Bits.UnsupportedRequest\r
);\r
- Print (\r
- L" AUX Power Detected(4): %E%d%N\n",\r
- PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" AUX Power Detected(4): %E%d%N\r\n",\r
+ PciExpressCap->DeviceStatus.Bits.AuxPower\r
);\r
- Print (\r
- L" Transactions Pending(5): %E%d%N\n",\r
- PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Transactions Pending(5): %E%d%N\r\n",\r
+ PciExpressCap->DeviceStatus.Bits.TransactionsPending\r
);\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT32 PcieLinkCap;\r
- CHAR16 *SupLinkSpeeds;\r
+ CHAR16 *MaxLinkSpeed;\r
CHAR16 *AspmValue;\r
\r
- PcieLinkCap = PciExpressCap->LinkCap;\r
- switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
+ switch (PciExpressCap->LinkCapability.Bits.MaxLinkSpeed) {\r
case 1:\r
- SupLinkSpeeds = L"2.5 GT/s";\r
+ MaxLinkSpeed = L"2.5 GT/s";\r
break;\r
case 2:\r
- SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
+ MaxLinkSpeed = L"5.0 GT/s";\r
+ break;\r
+ case 3:\r
+ MaxLinkSpeed = L"8.0 GT/s";\r
break;\r
default:\r
- SupLinkSpeeds = L"Unknown";\r
+ MaxLinkSpeed = L"Unknown";\r
break;\r
}\r
- Print (\r
- L" Supported Link Speeds(3:0): %E%s supported%N\n",\r
- SupLinkSpeeds\r
+ ShellPrintEx (-1, -1,\r
+ L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
+ MaxLinkSpeed\r
);\r
- Print (\r
- L" Maximum Link Width(9:4): %Ex%d%N\n",\r
- PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
+ PciExpressCap->LinkCapability.Bits.MaxLinkWidth\r
);\r
- switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
+ switch (PciExpressCap->LinkCapability.Bits.Aspm) {\r
+ case 0:\r
+ AspmValue = L"Not";\r
+ break;\r
case 1:\r
- AspmValue = L"L0s Entry";\r
+ AspmValue = L"L0s";\r
+ break;\r
+ case 2:\r
+ AspmValue = L"L1";\r
break;\r
case 3:\r
AspmValue = L"L0s and L1";\r
AspmValue = L"Reserved";\r
break;\r
}\r
- Print (\r
- L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
+ ShellPrintEx (-1, -1,\r
+ L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
AspmValue\r
);\r
- Print (\r
- L" L0s Exit Latency(14:12): %E%s%N\n",\r
- L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
+ ShellPrintEx (-1, -1,\r
+ L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
+ L0sLatencyStrTable[PciExpressCap->LinkCapability.Bits.L0sExitLatency]\r
);\r
- Print (\r
- L" L1 Exit Latency(17:15): %E%s%N\n",\r
- L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
+ ShellPrintEx (-1, -1,\r
+ L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
+ L1LatencyStrTable[PciExpressCap->LinkCapability.Bits.L1ExitLatency]\r
);\r
- Print (\r
- L" Clock Power Management(18): %E%d%N\n",\r
- PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Clock Power Management(18): %E%d%N\r\n",\r
+ PciExpressCap->LinkCapability.Bits.ClockPowerManagement\r
);\r
- Print (\r
- L" Surprise Down Error Reporting Capable(19): %E%d%N\n",\r
- PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
+ PciExpressCap->LinkCapability.Bits.SurpriseDownError\r
);\r
- Print (\r
- L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",\r
- PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
+ PciExpressCap->LinkCapability.Bits.DataLinkLayerLinkActive\r
);\r
- Print (\r
- L" Link Bandwidth Notification Capability(21): %E%d%N\n",\r
- PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
+ PciExpressCap->LinkCapability.Bits.LinkBandwidthNotification\r
);\r
- Print (\r
- L" Port Number(31:24): %E0x%02x%N\n",\r
- PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Port Number(31:24): %E0x%02x%N\r\n",\r
+ PciExpressCap->LinkCapability.Bits.PortNumber\r
);\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieLinkControl;\r
UINT8 DevicePortType;\r
\r
- PcieLinkControl = PciExpressCap->LinkControl;\r
- DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
- Print (\r
- L" Active State Power Management Control(1:0): %E%s%N\n",\r
- ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
+ DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
+ ShellPrintEx (-1, -1,\r
+ L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
+ ASPMCtrlStrTable[PciExpressCap->LinkControl.Bits.AspmControl]\r
);\r
//\r
// RCB is not applicable to switches\r
//\r
if (!IS_PCIE_SWITCH(DevicePortType)) {\r
- Print (\r
- L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",\r
- 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
+ ShellPrintEx (-1, -1,\r
+ L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
+ 1 << (PciExpressCap->LinkControl.Bits.ReadCompletionBoundary + 6)\r
);\r
}\r
//\r
// c) Upstream Ports of Switches\r
//\r
if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
- DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
- DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
- Print (\r
- L" Link Disable(4): %E%d%N\n",\r
- PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
+ DevicePortType != PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT &&\r
+ DevicePortType != PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Disable(4): %E%d%N\r\n",\r
+ PciExpressCap->LinkControl.Bits.LinkDisable\r
);\r
}\r
- Print (\r
- L" Common Clock Configuration(6): %E%d%N\n",\r
- PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Common Clock Configuration(6): %E%d%N\r\n",\r
+ PciExpressCap->LinkControl.Bits.CommonClockConfiguration\r
);\r
- Print (\r
- L" Extended Synch(7): %E%d%N\n",\r
- PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Extended Synch(7): %E%d%N\r\n",\r
+ PciExpressCap->LinkControl.Bits.ExtendedSynch\r
);\r
- Print (\r
- L" Enable Clock Power Management(8): %E%d%N\n",\r
- PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Enable Clock Power Management(8): %E%d%N\r\n",\r
+ PciExpressCap->LinkControl.Bits.ClockPowerManagement\r
);\r
- Print (\r
- L" Hardware Autonomous Width Disable(9): %E%d%N\n",\r
- PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
+ PciExpressCap->LinkControl.Bits.HardwareAutonomousWidthDisable\r
);\r
- Print (\r
- L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",\r
- PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
+ PciExpressCap->LinkControl.Bits.LinkBandwidthManagementInterrupt\r
);\r
- Print (\r
- L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",\r
- PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
+ PciExpressCap->LinkControl.Bits.LinkAutonomousBandwidthInterrupt\r
);\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieLinkStatus;\r
- CHAR16 *SupLinkSpeeds;\r
+ CHAR16 *CurLinkSpeed;\r
\r
- PcieLinkStatus = PciExpressCap->LinkStatus;\r
- switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
+ switch (PciExpressCap->LinkStatus.Bits.CurrentLinkSpeed) {\r
case 1:\r
- SupLinkSpeeds = L"2.5 GT/s";\r
+ CurLinkSpeed = L"2.5 GT/s";\r
break;\r
case 2:\r
- SupLinkSpeeds = L"5.0 GT/s";\r
+ CurLinkSpeed = L"5.0 GT/s";\r
+ break;\r
+ case 3:\r
+ CurLinkSpeed = L"8.0 GT/s";\r
break;\r
default:\r
- SupLinkSpeeds = L"Reserved";\r
+ CurLinkSpeed = L"Reserved";\r
break;\r
}\r
- Print (\r
- L" Current Link Speed(3:0): %E%s%N\n",\r
- SupLinkSpeeds\r
+ ShellPrintEx (-1, -1,\r
+ L" Current Link Speed(3:0): %E%s%N\r\n",\r
+ CurLinkSpeed\r
);\r
- Print (\r
- L" Negotiated Link Width(9:4): %Ex%d%N\n",\r
- PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
+ PciExpressCap->LinkStatus.Bits.NegotiatedLinkWidth\r
);\r
- Print (\r
- L" Link Training(11): %E%d%N\n",\r
- PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Training(11): %E%d%N\r\n",\r
+ PciExpressCap->LinkStatus.Bits.LinkTraining\r
);\r
- Print (\r
- L" Slot Clock Configuration(12): %E%d%N\n",\r
- PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Clock Configuration(12): %E%d%N\r\n",\r
+ PciExpressCap->LinkStatus.Bits.SlotClockConfiguration\r
);\r
- Print (\r
- L" Data Link Layer Link Active(13): %E%d%N\n",\r
- PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
+ PciExpressCap->LinkStatus.Bits.DataLinkLayerLinkActive\r
);\r
- Print (\r
- L" Link Bandwidth Management Status(14): %E%d%N\n",\r
- PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
+ PciExpressCap->LinkStatus.Bits.LinkBandwidthManagement\r
);\r
- Print (\r
- L" Link Autonomous Bandwidth Status(15): %E%d%N\n",\r
- PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
+ PciExpressCap->LinkStatus.Bits.LinkAutonomousBandwidth\r
);\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT32 PcieSlotCap;\r
-\r
- PcieSlotCap = PciExpressCap->SlotCap;\r
-\r
- Print (\r
- L" Attention Button Present(0): %E%d%N\n",\r
- PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Present(0): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.AttentionButton\r
);\r
- Print (\r
- L" Power Controller Present(1): %E%d%N\n",\r
- PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Controller Present(1): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.PowerController\r
);\r
- Print (\r
- L" MRL Sensor Present(2): %E%d%N\n",\r
- PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Present(2): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.MrlSensor\r
);\r
- Print (\r
- L" Attention Indicator Present(3): %E%d%N\n",\r
- PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Indicator Present(3): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.AttentionIndicator\r
);\r
- Print (\r
- L" Power Indicator Present(4): %E%d%N\n",\r
- PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Indicator Present(4): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.PowerIndicator\r
);\r
- Print (\r
- L" Hot-Plug Surprise(5): %E%d%N\n",\r
- PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.HotPlugSurprise\r
);\r
- Print (\r
- L" Hot-Plug Capable(6): %E%d%N\n",\r
- PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Capable(6): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.HotPlugCapable\r
);\r
- Print (\r
- L" Slot Power Limit Value(14:7): %E0x%02x%N\n",\r
- PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.SlotPowerLimitValue\r
);\r
- Print (\r
- L" Slot Power Limit Scale(16:15): %E%s%N\n",\r
- SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
+ ShellPrintEx (-1, -1,\r
+ L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
+ SlotPwrLmtScaleTable[PciExpressCap->SlotCapability.Bits.SlotPowerLimitScale]\r
);\r
- Print (\r
- L" Electromechanical Interlock Present(17): %E%d%N\n",\r
- PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.ElectromechanicalInterlock\r
);\r
- Print (\r
- L" No Command Completed Support(18): %E%d%N\n",\r
- PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" No Command Completed Support(18): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.NoCommandCompleted\r
);\r
- Print (\r
- L" Physical Slot Number(31:19): %E%d%N\n",\r
- PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" Physical Slot Number(31:19): %E%d%N\r\n",\r
+ PciExpressCap->SlotCapability.Bits.PhysicalSlotNumber\r
);\r
\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieSlotControl;\r
-\r
- PcieSlotControl = PciExpressCap->SlotControl;\r
- Print (\r
- L" Attention Button Pressed Enable(0): %E%d%N\n",\r
- PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
- );\r
- Print (\r
- L" Power Fault Detected Enable(1): %E%d%N\n",\r
- PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
- );\r
- Print (\r
- L" MRL Sensor Changed Enable(2): %E%d%N\n",\r
- PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
- );\r
- Print (\r
- L" Presence Detect Changed Enable(3): %E%d%N\n",\r
- PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
- );\r
- Print (\r
- L" Command Completed Interrupt Enable(4): %E%d%N\n",\r
- PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
- );\r
- Print (\r
- L" Hot-Plug Interrupt Enable(5): %E%d%N\n",\r
- PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
- );\r
- Print (\r
- L" Attention Indicator Control(7:6): %E%s%N\n",\r
- IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
- );\r
- Print (\r
- L" Power Indicator Control(9:8): %E%s%N\n",\r
- IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
- );\r
- Print (L" Power Controller Control(10): %EPower ");\r
- if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
- Print (L"Off%N\n");\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.AttentionButtonPressed\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.PowerFaultDetected\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.MrlSensorChanged\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.PresenceDetectChanged\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.CommandCompletedInterrupt\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.HotPlugInterrupt\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
+ IndicatorTable[\r
+ PciExpressCap->SlotControl.Bits.AttentionIndicator]\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Indicator Control(9:8): %E%s%N\r\n",\r
+ IndicatorTable[PciExpressCap->SlotControl.Bits.PowerIndicator]\r
+ );\r
+ ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
+ if (\r
+ PciExpressCap->SlotControl.Bits.PowerController) {\r
+ ShellPrintEx (-1, -1, L"Off%N\r\n");\r
} else {\r
- Print (L"On%N\n");\r
+ ShellPrintEx (-1, -1, L"On%N\r\n");\r
}\r
- Print (\r
- L" Electromechanical Interlock Control(11): %E%d%N\n",\r
- PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.ElectromechanicalInterlock\r
);\r
- Print (\r
- L" Data Link Layer State Changed Enable(12): %E%d%N\n",\r
- PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
+ PciExpressCap->SlotControl.Bits.DataLinkLayerStateChanged\r
);\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieSlotStatus;\r
-\r
- PcieSlotStatus = PciExpressCap->SlotStatus;\r
-\r
- Print (\r
- L" Attention Button Pressed(0): %E%d%N\n",\r
- PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
- );\r
- Print (\r
- L" Power Fault Detected(1): %E%d%N\n",\r
- PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
- );\r
- Print (\r
- L" MRL Sensor Changed(2): %E%d%N\n",\r
- PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
- );\r
- Print (\r
- L" Presence Detect Changed(3): %E%d%N\n",\r
- PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
- );\r
- Print (\r
- L" Command Completed(4): %E%d%N\n",\r
- PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
- );\r
- Print (L" MRL Sensor State(5): %EMRL ");\r
- if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
- Print (L" Opened%N\n");\r
+ ShellPrintEx (-1, -1,\r
+ L" Attention Button Pressed(0): %E%d%N\r\n",\r
+ PciExpressCap->SlotStatus.Bits.AttentionButtonPressed\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Power Fault Detected(1): %E%d%N\r\n",\r
+ PciExpressCap->SlotStatus.Bits.PowerFaultDetected\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" MRL Sensor Changed(2): %E%d%N\r\n",\r
+ PciExpressCap->SlotStatus.Bits.MrlSensorChanged\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Presence Detect Changed(3): %E%d%N\r\n",\r
+ PciExpressCap->SlotStatus.Bits.PresenceDetectChanged\r
+ );\r
+ ShellPrintEx (-1, -1,\r
+ L" Command Completed(4): %E%d%N\r\n",\r
+ PciExpressCap->SlotStatus.Bits.CommandCompleted\r
+ );\r
+ ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
+ if (\r
+ PciExpressCap->SlotStatus.Bits.MrlSensor) {\r
+ ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
} else {\r
- Print (L" Closed%N\n");\r
+ ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
}\r
- Print (L" Presence Detect State(6): ");\r
- if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
- Print (L"%ECard Present in slot%N\n");\r
+ ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
+ if (\r
+ PciExpressCap->SlotStatus.Bits.PresenceDetect) {\r
+ ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
} else {\r
- Print (L"%ESlot Empty%N\n");\r
+ ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
}\r
- Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
- if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
- Print (L"Engaged%N\n");\r
+ ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
+ if (\r
+ PciExpressCap->SlotStatus.Bits.ElectromechanicalInterlock) {\r
+ ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
} else {\r
- Print (L"Disengaged%N\n");\r
+ ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
}\r
- Print (\r
- L" Data Link Layer State Changed(8): %E%d%N\n",\r
- PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
+ PciExpressCap->SlotStatus.Bits.DataLinkLayerStateChanged\r
);\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieRootControl;\r
-\r
- PcieRootControl = PciExpressCap->RootControl;\r
-\r
- Print (\r
- L" System Error on Correctable Error Enable(0): %E%d%N\n",\r
- PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
+ PciExpressCap->RootControl.Bits.SystemErrorOnCorrectableError\r
);\r
- Print (\r
- L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",\r
- PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
+ PciExpressCap->RootControl.Bits.SystemErrorOnNonFatalError\r
);\r
- Print (\r
- L" System Error on Fatal Error Enable(2): %E%d%N\n",\r
- PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
+ PciExpressCap->RootControl.Bits.SystemErrorOnFatalError\r
);\r
- Print (\r
- L" PME Interrupt Enable(3): %E%d%N\n",\r
- PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Interrupt Enable(3): %E%d%N\r\n",\r
+ PciExpressCap->RootControl.Bits.PmeInterrupt\r
);\r
- Print (\r
- L" CRS Software Visibility Enable(4): %E%d%N\n",\r
- PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
+ ShellPrintEx (-1, -1,\r
+ L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
+ PciExpressCap->RootControl.Bits.CrsSoftwareVisibility\r
);\r
\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT16 PcieRootCap;\r
-\r
- PcieRootCap = PciExpressCap->RsvdP;\r
-\r
- Print (\r
- L" CRS Software Visibility(0): %E%d%N\n",\r
- PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
+ ShellPrintEx (-1, -1,\r
+ L" CRS Software Visibility(0): %E%d%N\r\n",\r
+ PciExpressCap->RootCapability.Bits.CrsSoftwareVisibility\r
);\r
\r
return EFI_SUCCESS;\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
)\r
{\r
- UINT32 PcieRootStatus;\r
-\r
- PcieRootStatus = PciExpressCap->RootStatus;\r
-\r
- Print (\r
- L" PME Requester ID(15:0): %E0x%04x%N\n",\r
- PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
+ PciExpressCap->RootStatus.Bits.PmeRequesterId\r
);\r
- Print (\r
- L" PME Status(16): %E%d%N\n",\r
- PCIE_CAP_PME_STATUS (PcieRootStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Status(16): %E%d%N\r\n",\r
+ PciExpressCap->RootStatus.Bits.PmeStatus\r
);\r
- Print (\r
- L" PME Pending(17): %E%d%N\n",\r
- PCIE_CAP_PME_PENDING (PcieRootStatus)\r
+ ShellPrintEx (-1, -1,\r
+ L" PME Pending(17): %E%d%N\r\n",\r
+ PciExpressCap->RootStatus.Bits.PmePending\r
);\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
- Display Pcie device structure.\r
+ Function to interpret and print out the link control structure\r
\r
- @param[in] IoDev The pointer to the root pci protocol.\r
- @param[in] Address The Address to start at.\r
- @param[in] CapabilityPtr The offset from the address to start.\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
-PciExplainPciExpress (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
- IN UINT64 Address,\r
- IN UINT8 CapabilityPtr\r
+PrintInterpretedExtendedCompatibilityLinkControl (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
)\r
{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
+ gShellDebug1HiiHandle, \r
+ Header->RootComplexLinkCapabilities,\r
+ Header->RootComplexLinkControl,\r
+ Header->RootComplexLinkStatus\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
\r
- PCIE_CAP_STURCTURE PciExpressCap;\r
- EFI_STATUS Status;\r
- UINT64 CapRegAddress;\r
- UINT8 Bus;\r
- UINT8 Dev;\r
- UINT8 Func;\r
- UINT8 *ExRegBuffer;\r
- UINTN ExtendRegSize;\r
- UINT64 Pciex_Address;\r
- UINT8 DevicePortType;\r
- UINTN Index;\r
- UINT8 *RegAddr;\r
- UINTN RegValue;\r
-\r
- CapRegAddress = Address + CapabilityPtr;\r
- IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint32,\r
- CapRegAddress,\r
- sizeof (PciExpressCap) / sizeof (UINT32),\r
- &PciExpressCap\r
- );\r
+/**\r
+ Function to interpret and print out the power budgeting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
+ gShellDebug1HiiHandle, \r
+ Header->DataSelect,\r
+ Header->Data,\r
+ Header->PowerBudgetCapability\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the ACS structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityAcs (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r
+ UINT16 VectorSize;\r
+ UINT16 LoopCounter;\r
+\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r
+ VectorSize = 0;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
+ gShellDebug1HiiHandle, \r
+ Header->AcsCapability,\r
+ Header->AcsControl\r
+ ); \r
+ if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
+ VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
+ if (VectorSize == 0) {\r
+ VectorSize = 256;\r
+ }\r
+ for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
+ gShellDebug1HiiHandle, \r
+ LoopCounter + 1,\r
+ Header->EgressControlVectorArray[LoopCounter]\r
+ ); \r
+ }\r
+ }\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the latency tolerance reporting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
+ gShellDebug1HiiHandle, \r
+ Header->MaxSnoopLatency,\r
+ Header->MaxNoSnoopLatency\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the serial number structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilitySerialNumber (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
+ gShellDebug1HiiHandle, \r
+ Header->SerialNumber\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the RCRB structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityRcrb (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
+ gShellDebug1HiiHandle, \r
+ Header->VendorId,\r
+ Header->DeviceId,\r
+ Header->RcrbCapabilities,\r
+ Header->RcrbControl\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the vendor specific structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityVendorSpecific (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
+ gShellDebug1HiiHandle, \r
+ Header->VendorSpecificHeader\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the Event Collector Endpoint Association structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityECEA (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
+ gShellDebug1HiiHandle, \r
+ Header->AssociationBitmap\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the ARI structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityAri (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
+ gShellDebug1HiiHandle, \r
+ Header->AriCapability,\r
+ Header->AriControl\r
+ ); \r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
\r
- DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
+/**\r
+ Function to interpret and print out the DPA structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
+ UINT8 LinkCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
+ gShellDebug1HiiHandle, \r
+ Header->DpaCapability,\r
+ Header->DpaLatencyIndicator,\r
+ Header->DpaStatus,\r
+ Header->DpaControl\r
+ ); \r
+ for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
+ gShellDebug1HiiHandle, \r
+ LinkCount+1,\r
+ Header->DpaPowerAllocationArray[LinkCount]\r
+ );\r
+ }\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the link declaration structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r
+ UINT8 LinkCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
+ gShellDebug1HiiHandle, \r
+ Header->ElementSelfDescription\r
+ );\r
+\r
+ for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
+ gShellDebug1HiiHandle, \r
+ LinkCount+1,\r
+ Header->LinkEntry[LinkCount]\r
+ );\r
+ }\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the Advanced Error Reporting structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityAer (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
+ gShellDebug1HiiHandle, \r
+ Header->UncorrectableErrorStatus,\r
+ Header->UncorrectableErrorMask,\r
+ Header->UncorrectableErrorSeverity,\r
+ Header->CorrectableErrorStatus,\r
+ Header->CorrectableErrorMask,\r
+ Header->AdvancedErrorCapabilitiesAndControl,\r
+ Header->HeaderLog[0],\r
+ Header->HeaderLog[1],\r
+ Header->HeaderLog[2],\r
+ Header->HeaderLog[3],\r
+ Header->RootErrorCommand,\r
+ Header->RootErrorStatus,\r
+ Header->ErrorSourceIdentification,\r
+ Header->CorrectableErrorSourceIdentification,\r
+ Header->TlpPrefixLog[0],\r
+ Header->TlpPrefixLog[1],\r
+ Header->TlpPrefixLog[2],\r
+ Header->TlpPrefixLog[3]\r
+ );\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the multicast structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityMulticast (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
+ gShellDebug1HiiHandle, \r
+ Header->MultiCastCapability,\r
+ Header->MulticastControl,\r
+ Header->McBaseAddress,\r
+ Header->McReceiveAddress,\r
+ Header->McBlockAll,\r
+ Header->McBlockUntranslated,\r
+ Header->McOverlayBar\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the virtual channel and multi virtual channel structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityVirtualChannel (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
+ UINT32 ItemCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
+ gShellDebug1HiiHandle, \r
+ Header->ExtendedVcCount,\r
+ Header->PortVcCapability1,\r
+ Header->PortVcCapability2,\r
+ Header->VcArbTableOffset,\r
+ Header->PortVcControl,\r
+ Header->PortVcStatus\r
+ );\r
+ for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
+ CapabilityItem = &Header->Capability[ItemCount];\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
+ gShellDebug1HiiHandle, \r
+ ItemCount+1,\r
+ CapabilityItem->VcResourceCapability,\r
+ CapabilityItem->PortArbTableOffset,\r
+ CapabilityItem->VcResourceControl,\r
+ CapabilityItem->VcResourceStatus\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY)\r
+ + Header->ExtendedVcCount * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the resizeable bar structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityResizeableBar (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
+ UINT32 ItemCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
+\r
+ for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
+ gShellDebug1HiiHandle, \r
+ ItemCount+1,\r
+ Header->Capability[ItemCount].ResizableBarCapability,\r
+ Header->Capability[ItemCount].ResizableBarControl\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the TPH structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilityTph (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
+ gShellDebug1HiiHandle, \r
+ Header->TphRequesterCapability,\r
+ Header->TphRequesterControl\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
+ GET_TPH_TABLE_SIZE(Header),\r
+ (VOID *)Header->TphStTable\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the secondary PCIe capability structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+PrintInterpretedExtendedCompatibilitySecondary (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCap\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
+ gShellDebug1HiiHandle, \r
+ Header->LinkControl3.Uint32,\r
+ Header->LaneErrorStatus\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
+ PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r
+ (VOID *)Header->EqualizationControl\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE) - sizeof (Header->EqualizationControl)\r
+ + PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Display Pcie extended capability details\r
+\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] HeaderAddress The address of this capability header.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+PrintPciExtendedCapabilityDetails(\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r
+ )\r
+{\r
+ switch (HeaderAddress->CapabilityId){\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
+ return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
+ return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
+ return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
+ return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
+ return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
+ return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
+ return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
+ return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
+ return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
+ return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
+ return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
+ //\r
+ // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
+ //\r
+ return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
+ return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
+ return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
+ case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
+ return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
+ default:\r
+ ShellPrintEx (-1, -1,\r
+ L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
+ HeaderAddress->CapabilityId\r
+ );\r
+ return EFI_SUCCESS;\r
+ };\r
+\r
+}\r
+\r
+/**\r
+ Display Pcie device structure.\r
+\r
+ @param[in] PciExpressCap PCI Express capability buffer.\r
+ @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
+ @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
+**/\r
+VOID\r
+PciExplainPciExpress (\r
+ IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
+ IN UINT8 *ExtendedConfigSpace,\r
+ IN CONST UINT16 ExtendedCapability\r
+ )\r
+{\r
+ UINT8 DevicePortType;\r
+ UINTN Index;\r
+ UINT8 *RegAddr;\r
+ UINTN RegValue;\r
+ PCI_EXP_EXT_HDR *ExtHdr;\r
+\r
+ DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
\r
- Print (L"\nPci Express device capability structure:\n");\r
+ ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
\r
for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
if (ShellGetExecutionBreakFlag()) {\r
- goto Done;\r
+ return;\r
}\r
- RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
+ RegAddr = (UINT8 *) PciExpressCap + PcieExplainList[Index].Offset;\r
switch (PcieExplainList[Index].Width) {\r
case FieldWidthUINT8:\r
RegValue = *(UINT8 *) RegAddr;\r
// a) Root Complex Integrated Endpoint\r
// b) Root Complex Event Collector\r
//\r
- if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
- DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
+ if (DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT ||\r
+ DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
continue;\r
}\r
break;\r
// b) Downstream Port of PCI Express Switch\r
// and when SlotImplemented bit is set in PCIE cap register.\r
//\r
- if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
- DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
- !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
+ if ((DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT &&\r
+ DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) ||\r
+ !PciExpressCap->Capability.Bits.SlotImplemented) {\r
continue;\r
}\r
break;\r
// Root registers are only valid for\r
// Root Port of PCI Express Root Complex\r
//\r
- if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
+ if (DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) {\r
continue;\r
}\r
break;\r
default:\r
break;\r
}\r
- PcieExplainList[Index].Func (&PciExpressCap);\r
- }\r
-\r
- Bus = (UINT8) (RShiftU64 (Address, 24));\r
- Dev = (UINT8) (RShiftU64 (Address, 16));\r
- Func = (UINT8) (RShiftU64 (Address, 8));\r
-\r
- Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
-\r
- ExtendRegSize = 0x1000 - 0x100;\r
-\r
- ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
-\r
- //\r
- // PciRootBridgeIo protocol should support pci express extend space IO\r
- // (Begins at offset 0x100)\r
- //\r
- Status = IoDev->Pci.Read (\r
- IoDev,\r
- EfiPciWidthUint32,\r
- Pciex_Address,\r
- (ExtendRegSize) / sizeof (UINT32),\r
- (VOID *) (ExRegBuffer)\r
- );\r
- if (EFI_ERROR (Status)) {\r
- FreePool ((VOID *) ExRegBuffer);\r
- return EFI_UNSUPPORTED;\r
+ PcieExplainList[Index].Func (PciExpressCap);\r
}\r
- //\r
- // Start outputing PciEx extend space( 0xFF-0xFFF)\r
- //\r
- Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
\r
- if (ExRegBuffer != NULL) {\r
- DumpHex (\r
- 2,\r
- 0x100,\r
- ExtendRegSize,\r
- (VOID *) (ExRegBuffer)\r
- );\r
+ ExtHdr = (PCI_EXP_EXT_HDR*)ExtendedConfigSpace;\r
+ while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
+ //\r
+ // Process this item\r
+ //\r
+ if (ExtendedCapability == 0xFFFF || ExtendedCapability == ExtHdr->CapabilityId) {\r
+ //\r
+ // Print this item\r
+ //\r
+ PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExtendedConfigSpace, ExtHdr, PciExpressCap);\r
+ }\r
\r
- FreePool ((VOID *) ExRegBuffer);\r
+ //\r
+ // Advance to the next item if it exists\r
+ //\r
+ if (ExtHdr->NextCapabilityOffset != 0) {\r
+ ExtHdr = (PCI_EXP_EXT_HDR*)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
+ } else {\r
+ break;\r
+ }\r
}\r
-\r
-Done:\r
- return EFI_SUCCESS;\r
}\r
projects / mirror_edk2.git / blobdiff